 Hello and welcome to this presentation of the STM32-C0 System Configuration Controller. STM32-C0 microcontrollers feature a set of configuration registers located in the CIS-CFG module. The system configuration controller gives access to the following features. Enabling and disabling I2C fast mode plus high drive, configuring the infrared timer or our team module, remapping the PA11 and PA12 GPIOs to PA9 and PA10, selecting the memory accessible at address 0, status of pending interrupts from each external interrupt line, enabling and disabling safety features. The I2C controller present in the STM32-C0 supports three speeds. Standard mode, the maximum bit rate is 100 kilobits per second. Fast mode, the maximum bit rate is 400 kilobits per second. And fast mode plus, the maximum bit rate is 1 megabit per second. Fast mode plus requires a high drive capability which is enabled in the CIS-CFG module. Since high drive is controlled at pin level, it's also available for the other alternate functions. The high drive capability of the I2C1 pins can be configured per pin through the IC2CPC14 FMP, I2CPA9 and 10 FMP and I2CPB6 to 9 FMP bits. The infrared timer or IR team unit requires a modulation envelope signal that is provided either by USARTS or by TIM16. The IR mode field in CIS-CFG-CFGR1 register controls the related input multiplexer. The IR pulpit in the CIS-CFG-CFGR1 register selects whether the output signal is inverted. When the PA11 and the PA12-RMP bit in the CIS-CFG-CFGR1 register are set, the PA11 and PA12 alternate functions are remapped to pins PA9 and PA10. This is useful when these alternate functions are needed because PA11 and PA12 have no dedicated IO pads. One pin on the package can be bounded to multiple pads on the silicon, for instance PA0, PA1, PA2, PF2N RST, bonded to the pin 4 of SO8 package. When several GPIOs are internally connected to the same pin, the CIS-CFG-CFGR3 register allows assigning the one to keep setting specified by its corresponding GPIOX mode R register. The other GPIOs are forced into digital input mode, regardless their corresponding GPIOX mode R register settings. The default setting when the secure-muxing N-bit is set to flash-opt-R is described on the previous slide. It's safe because the configuration in which two GPIOs bonded together with push-pull output configuration with different output levels cannot happen. However, for some applications it may be beneficial to multiply the maximum output current on the pin by using several GPIOs bonded together to boost the total output current on such particular pin. If the secure-muxing N-bit is cleared in flash-opt-R, the user can enable output on more GPIOs bonded together in GPIOX mode R register. The user software must ensure that there's no conflict between the GPIOs. The mem mode field in the CIS-CFG-CFGR1 register selects which memory is accessible at address 0. Three memories can be aligned to address 0, main flash memory, system flash memory, or SRAM. Note that the default setting of these fields depends on boot pin, option bytes, and control bit. The CIS-CFG-CFGR2 register contains the control and status bits linked to safety. Lockup-lock control bit enables the connection of Cortex-M0 plus lockup state towards the timer's break-in puts. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. The CIS-CFG module supports four interrupt line status registers. They enable software to easily find the cause of an XDI interrupt by having in the same register all pending interrupt sources associated with a particular interrupt line. In the STM32C0, there is one interrupt line status register per peripheral capable of asserting an external interrupt. The benefit of these interrupt line status registers is explained in the next slide. The left part of the figure represents the peripherals able to assert external interrupts. The CIS-CFG interrupt status registers appear in the middle of the figure. The connection of the external interrupts to the NVIC is indicated on the right part of the figure. In addition to this presentation, you can refer to I2C, IRTIM, GPIO, interrupts and timer's training modules. For more details, please refer to application note AN2606 STM32 microcontroller system memory boot mode. Thank you for attending this presentation.