 We continue our discussion on the compound semiconductors. Particularly, we move on to the FETs and heterostructure FETs. We have just begun our discussion and as we have shown that the BLM arsenide and indium phosphide have got electron velocity versus electric field totally different from that in the case of silicon. We have seen that this is because of the transport mechanism. The electrons tend to be in the high electron mobility region that is low effective mass region at a slightly lower energy and it gets transferred on to the higher mass region where the mobility falls. So, it goes through that region and ultimately goes into the saturation region. So, if you bias the device or if the electrons enter into this high field region suddenly it does not go there straight it will go through this portion and go there. So, due to that there will be a time interval during which the electron goes through this peak velocity. So, that is shown in this graph that is time versus the diff velocity of gallium arsenide if you take. If I applied 10 k v that is the saturation field at 10 k v, but in the initial couple of microseconds the velocity is much higher than the saturation velocity because the electrons are located in the low mass region. So, their velocity is high at that field, but once they acquire energy they go into the region where the mass is high. So, the it saturates. So, if you convert it to distance we know that now with distance see by the time it has moved reached that velocity it has moved through this region. So, diff velocity versus the distance along the channel from the source will have the velocity like this, 10 k v. So, that would tell us that there is specific benefit for gallium arsenide devices and indipose by devices where if you go to short channel lengths the over the entire region the velocity will be higher than the saturation velocity. So, that will give you higher current driving capability for a given die device and also higher trans conductance that is the driving capability is better. So, device which is very popularly used in the gallium arsenide material is the is the metal semiconductor field if it transistors. Rather than using the MOSFET as in case of silicon all the most of these gallium arsenide micro wave, millimeter micro wave integrate circuits M M I C. So, those devices are made up of mesfet logic circuit. Though there are improvements which we can discuss in the next lecture other type of devices like the hemp which are being attended to now. So, here I already pointed out that you have got the source and drain which are omicontacts to the n type region which is a thin layer realized on semi-insulating gallium arsenide. Now, this contact is the gate contact in case there is no gate between the source and drain you have got this conducting channel. So, there will be it is equivalent of a resistance as you vary the voltage the current will vary across through the resistor. Now, how much is the current flow depend upon the doping here and how much is the thickness of this end region. Suppose the thin layer is very thin the if the layer is not there at all the full layer is available for conduction. Supposing this metal semiconductor contact which is the rectifying contact which is serving as a gate is present on the top of this layer there will be there will be a depletion layer below that channel below the gate because short key contact or rectifying contact will always have a depleted layer. Suppose due to that built in potential the depletion layer below that is completely depleting the channel the current flow between the drain and the source will be 0 because this is there is no carrier available layer is entirely depleted. So, if I want to bring it on condition what I have to do will be I have to reduce the depletion layer width. I can reduce the depletion layer width by forward biasing this metal semiconductor contact a plus voltage to the gate depletion layer can be open that will allow the current to flow. That means this device can act as enhancement mode type of device if it is depleted with then there is a 0 gate bias. Alternatively if the doping and thickness are such that the depletion layer width at 0 gate bias is less than the thickness of this channel then even without applying gate voltage there will be current flow because some channel is open as you can see here that will be depletion type. For example here the diagram that I have shown even without the gate voltage if there is a depletion layer like this of height h then the current flow through this region between this plus charges are the depleted layers between the semi-insulating layer and the depleted layer depletion layer there is a path for current flow. So, if the when the gate bias is 0 if the depletion layer width is less than this channel thickness a then the current will be present even at without gate bias that is depletion type of device. Now before we go into a discussion of this type of device we will see have couple of definitions. One is the pinch-off voltage. Pinch-off voltage is the voltage or the potential that must exist across the depletion layer which completely depletes the channel. So, due to the potential v p 0 present across the depletion layer if the channel is completely depleting then there is no current flow that is pinch-off that is channel is completely pinch-off from source to drain and completely. So, you can see that from the standard relations from the abrupt junction the model the pinch-off voltage will be q n d is the doping a is the thickness of the layer a square divided by twice epsilon r epsilon 0 epsilon r is the permutivity of gallium arsenide. If it is silicon it is that of silicon it is about 12.8 for the case of gallium arsenide for silicon it is 12. So, how much is that pinch-off voltage depends upon the thickness and the doping concentration. In the layers pinch-off voltage is small. Higher doping pinch-off voltage will be higher for a given thickness. So, now you can see that if the built-in voltage is less than the pinch-off voltage the depletion layer which will be less than the channel thickness that means it will be normally off. So, if I have to turn off the device I have to add additional gate voltage to the built-in potential so that the depletion layer becomes completely equal to a. So, V b i it is equal to h V b a plus V g s actually V g s should be negative because the polarity of V b i is plus here and minus there you have to add on gate voltage means actually you have to apply a negative voltage if I apply V g s so that the depletion layer widens and becomes equal to a then V b i plus V g s is equal to V p 0. So, what we are telling is if I apply add V g s to V b i then it will be V p 0 for channel the pinch-off. Now, the definition of threshold voltage so let us come back to this now. Suppose V b i equal to V p 0 even if we are slightest voltage as it applied to the gate plus voltage the depletion layer which will reduce. Suppose V b i is less than V p 0 I must apply negative voltage to the gate so that depletion layer widens to turn off the device. For example, when the built-in voltage is 0.5 volts if the depletion layer width is h I must add let us say let us say built-in potential is 0.5 and V p 0 is 1 volt then I must add 0.5 volts to the gate so that entire channel is depleted. That means the V g s will be actually what you apply will be same polarity as the built-in voltage that is gate voltage will be negative. So, if I apply 0.5 volts negative voltage then the channel will be pinch-off that is it will be turned off. So, threshold voltage is the voltage that you must apply to the gate so that when you apply that the potential across the channel is equal to V p 0. So, that V g s is actually equal to V b i minus V p 0. So, with threshold voltage threshold voltage of the mesh width is defined as the gate voltage that I must apply so that the channel is just depleted. See in the example that you have taken if V b i is 0.5 and V p 0 is 1 volt threshold voltage is 0.5 minus 1 that is minus 0.5 volts I must apply minus 0.5 volts to turn off the device that is in this verge after none. Supposing the V b i is 0.8 volts and pinch-off voltage is 0.5 volts V b i minus V p 0 is plus 0.3 volts that means I must apply 0.3 volts to bring it to conduction plus voltage because even without applying the if this is 0.8 and V p 0 is 0.5 even without the gate voltage channel will be depleted I must apply plus voltage to the gate so that the channel is just opening up that is the definition. Now, let me go into the quickly into the analysis of this device not into two great detail, but how it comes over just like in the case of MOSFET or any other FET the mesh FET also has got a linear region then the triode region and the saturation region. So, if in the linear region it behaves like a resistor that is the channel thickness is same from source into the drain end that is like in the case of MOSFET the channel charge is same from source into the drain end here channel thickness is the same from the source into the drain end. So, we are talking of the drain voltage which is very much less than whatever voltage is present here V b i minus V b which is see for example, when V g s is equal to 0 there is certain depletion layer width. Now, V g s what we are applying here is if I write just V b V g s then you have to if you want to deplete it you must make it negative. So, if I add V b i minus minus V g s this is negative. So, then depletion layer width wider. So, V b i minus V g s is actually total voltage present here. For example, if I want to give plus 0.5 minus of minus 0.1 volts that is plus 0.5 plus 0.6 volts. So, this is actually more than the V b i which we are applying here. So, then the depletion layer will widen here. So, if the V d s is very small compared to this voltage drop across this depletion layer that means drop from here to here drain to source end is negligible compared to this depletion layer width. So, which would mean if I go from this end to that end the depletion layer width is not changing. So, as a result what we can say is when I apply voltage V d s which is small compared to this voltage across the depletion layer the current will be reduced or the current voltage relationship means just like a resistor. So, V d s c is actually in fact what you are saying in doing is you are neglecting the drop between this point and this point assuming that this is very close in contact with this gate region. You cannot keep in touch with this gate region because then it will short there must be some finite space ok. I d into R is the voltage drop across the resistor R is rho L by A rho is the resistivity of the channel ok L is there rho is 1 by sigma sigma is q and d into mu n. So, this is actually this is actually the whole term is rho or 1 by sigma length area of cross section for the current flow in the along the channel is channel thickness ok channel thickness into width cross section if you take that is thickness into the width means perpendicular to this plane of this one. So, area of cross section to the current flow is A minus h that is that thickness into W. So, you can see that W to A minus h is the area of cross section. So, this is rho L by A into I d is the voltage drop ok. So, I just rewrite that we will develop on that what is A? A can be correlated to the pinch off voltage through this relationship. So, in fact you can say that A is proportional to square root of V p 0 ok and what is h? h will be see V p 0 is actually the voltage total potential present across the channel when it is depletion layer width is equal to A. Now, in this particular situation the voltage present across this is V B I minus V G S that is the voltage. So, if h is the depletion layer width when the voltage is V B I minus V G S then you can use the same equation V B I minus V G S is equal to Q and D into Q and D into h square ok. So, you can use that relationship to get that depletion layer width like this. So, this is related to V p 0 and h is related to V B I minus V p 0 that is all V G 0 that is what you have to remember ok. So, V D S is this one I have rewritten this equation whatever we have explained now ok. Now, I D therefore, I can write I D by rewriting this taking to the other side Q and D into W into A divided by that this quantity I have rewritten that. What is this quantity? This is sigma divided by L channel length into cross section cross section of the channel when it is fully open W into A is actually the entire cross section W is the depth A is the thickness. So, W into A is the cross section. So, if you see this this is the conductivity conductivity into area divided by L that is the conductance. Instead of resistance it is conductance Q and D Q and D Q and D into W. So, that you can write it as and I just pulled that out A. So, you get this one. So, in terms of the channel conductance G naught this is a G naught I can write I D is equal to G naught into 1 minus h by A. Why we are writing like this? This is you know that A is proportional to root of V p 0 and because V p 0 is present depletion layer width is A and if the voltage across the depletion layer width is V B I minus V G S h is the depletion layer width. So, you can write this as ratio of the 2 will be square root of V B I minus V G S divided by V p 0 that is the thing h is equal to Q and D see Q and D h square divided by twice epsilon r epsilon 0 is the voltage across the depletion layer. It is a standard equation if it were V p 0 that will be V B A as A is equal to this whole term into V p 0 h is equal to this whole term into whatever voltage is present across the depletion layer that is V B I minus V p 0. So, if I take A by h this term will cancel I am sorry if I take h by A this term will cancel and h by A will be square root of V B I minus V V G S by A. So, V p 0 is that A is that. So, substituting both the thing as I just pointed out I D is equal to G naught into 1 minus h by A into V D S that is what we saw. Now, for h by A A is this quantity h is the same quantity, but replaced by V B I minus V G S 0. So, h by A will be this. So, this is the I D versus V D S when V D S is small compared to the voltage drop across the depletion layer implying the resistance is actually it behaves like a resistor between these portions. The depletion layer width is remaining the same thing because the drop from here to here is not changing because V D S is very small. So, that is the thing. Now, if I take the I B characteristics of this mass set what will happen? This is constant it is actually channel conductance when it is fully open and for a given voltage this is constant. So, if I vary I D if I vary V D I D will vary linearly. V G S is actually negative. So, this will add on. So, if I keep on increasing the V G S negatively this term become larger and larger this will become smaller and smaller. Depletion layer width will become wider and wider. So, channel conductance total conductance will become reduced current will reduce. So, for a given gate voltage there will be linear relationship. So, V G S equal to 0 1 minus V B by V P 0 into V D S. So, if I increase the gate voltage the depletion layer width increases channel thickness available current for current flow will reduce. So, current is reduced. So, you can see several linear characteristics you can obtain by keeping on increasing the V G S till you pinch off the channel completely. When I pinch off the channel completely the current will be 0. Now, what will happen if I increase the drain voltage further? As V D S becomes larger and comparable to V B A minus V G S. What we are telling is I increase the V D S initially when the V D S is small the depletion layer is constant everywhere. Now, as I keep on increasing the voltage the drop from the drain to the source region becomes comparable to the depletion voltage across the depletion layer width depletion layer. The voltage across the depletion layer was V B A minus V G S. In fact, if you take the magnitude it is V B A plus magnitude of V G S. So, that is plus here minus here. Now, if you move in this direction there is additional plus voltage here. So, this is V B A minus V G S from here to here. If I take the drain end the voltage from here to here will be for example, it comes from here V B A minus V G S rise from here to here. From here to here further V D S is V D S rise is there. So, total voltage drop across depletion here will be V B A minus V G S which is the drop there plus the drop across the channel. That is exactly what you did in the case of MOSFET. So, voltage drop across the depletion layer at this edge will be more than the voltage drop here by an amount equal to the V D S. Even in the linear region it will be there, but it is negligible compared to this voltage. So, because the voltage drop is more here we can see the depletion layer width will be something here H naught as move here it will keep on increasing. So, that is what we are saying here at the drain end the V D S as V D S becomes larger and comparable to V B A minus V G S that is the voltage that is present at the source end. Then the potential drop across the depletion layer increases at the source end at the source end from V B A minus V G S to V B A minus V G S plus V D S at the drain end as you move from the source to the end of the channel. So, as a result depletion layer width will be wider the thickness of the channel reduces gradually from the source to drain because potential drop here is something here it is more by an amount equal to V D S. So, depletion layer gradually decreases increases from here to here and the channel thickness decreases from here to here. So, it is equivalent of a resistor if the resistor is like that if the resistor is like this constant width and increase the voltage current will increase linearly. Supposing the resistor becomes narrower at the drain end due to the depletion layer width the effective resistance of the channel increases. Therefore, even if the resistance were constant current would have increased linearly, but because as increase the drain voltage the shape of the resistance keeps on changing like this the resistance of the channel also increases as increase the drain voltage. Because the resistance increases with the drain voltage the current will not increase linearly with the drain voltage. As a result what happens is you get I am sorry just you get as a result of that there is deviation from linearity and ultimately the current will saturate. Current will saturate when this particular region thickness becomes very very small here drain end. When the depletion layer almost reaches to this end of the channel thickness it is almost closer when it almost closes the resistance becomes very very large. It cannot close any further then the small gap there. So, current will be controlled by whatever is flowing through the small gap if it you can see if the current tend to increase beyond that point the drop would increase. If the drop increases the depletion layer will be wider if it increases the it will close the channel. If it closes the channel current will tend to fall. So, depletion will open. So, what we are doing is a dynamic equilibrium will reach where channel will come to close almost closing region, but not completely closing. So, that allow whatever current is entering here to go through that thing. So, that means from here to here the drop is actually equal to V b i minus V g s plus V d s that will drop across the depletion layer and drop across the depletion layer is just sufficient to close this channel. That means the total voltage across the depletion layer now will be V b i minus V g s plus V d s that should be equal to the pinch of voltage V p 0. So, when V b i minus V g s plus V d s becomes equal to V p 0 the current will saturate. That is all the principle that is involved here. So, that is chocolate idealistic model there will changes in that, but still we can use it as a for long channel devices without any hesitation. So, what we are going to do is quickly see. So, now what we know is depletion layer widens channel becomes narrower and narrower at the drain end. Therefore, I d V d relationship is no longer linear because the resistance keeps on increasing, but when the voltage drop across the channel reaches a certain value that is say V d sat at that point the depletion layer almost close of this. You cannot the voltage cannot increase beyond that point because then the depletion layer if it closes fully current will tend to fall. So, the dynamic equilibrium at the dynamic equilibrium you reach the V d sat such that the depletion layer at the drain end has just closed just about to close. That means, voltage drop across the gate and this channel end is V p 0, which would mean that V p 0 is equal to V b i minus V b g s plus V d sat that is the condition for saturation current. We can quickly run through this. So, now actually this is you take this as a gradual channel approximation because when analyzing and finding the depletion layer widens you still use one dimensional equation along this, indicating that the two dimensional effects are not present here in this direction. So, that is called gradual channel approximation meaning the channel thickness changes gradually from source to drain end or the voltage change here is very gradually when you go along the channel length. Or in other words, L-tree field in this direction is small compared to the L-tree field in the particular direction that is like in the case of MOSFET where we also talked of gradual channel approximation. So, now with this understanding I just quickly run through the derivation not going through the very detailed. So, all that we have to see is use the same equation whatever we have been using. Take a small width same i r V is equal to i into r. What we do is take a small width d of x, determine what is the drop across that and at any x, x is in the direction. At any x take d of x channel length d of x what is the voltage drop across that. Integrate that term x equal to 0 to x equal to L channel length L and voltage equal to PBI minus VGS here to PBI minus VGS plus VDS that will give the IDVD characteristics over the entire region from linear to the saturation region. So, what is the voltage drop across this for a given ID, ID into rho into d of x divided by area of cross section. So, that rho is of course, the channel resistance which is 1 by Q mu N d and area is W into d of x I am sorry W into A minus F h. So, voltage drop across d of x can be written in this fashion. ID into d of x that is ID into L divided by sigma that is ID into rho is 1 by this divided by area, area is W into A minus H of x. A minus H of x thickness W is the width W into A minus H is the area cross section. So, all that you have done is ID into rho d of x divided by area that is the voltage drop across that. Now, what you do is all that you have to remember is a is related to root of v p 0 h minus of x is related to the voltage drop at x across this that will be that will be actually whatever voltage you are present here plus v of x there v by minus v g s plus v of x. So, H will be proportional to square root of that voltage. So, that is what we do here integrate it from v from source into the drain in this x 0 to L that is what we did. I mean do that substitute for A and H of x in terms of the v p 0 and what is the voltage present across the depletion layer? Because H of x is a depletion layer at any x that width of that depends how much is the voltage across the depletion layer that is v b i minus v g s plus v of x. So, same thing I have written integrating ID into L is that quantity. I have nothing here no changes just rewritten the whole thing because I can pull all these things on to the right hand side integral on the left hand side is ID into L right hand side you get this term. Substituting for H and A in terms of the voltage across the depletion layer is this one at x voltage at across the entire layer for pinch off will be v p 0 all that you did this is g naught. I put L down this that is g naught conductance into this quantity integrate that I will not go through that quickly that is the integral value. So, you can see that if this term are not present v d s this term is negligible I would have got ID versus v d s linear proportional to conductance, but to the gate bias there is a term which is reducing that. So, if you apply reverse bias to the gate this value will go down and you saw the linear region that characteristic or like this. So, in skipping we will back to show that linear region, but when the drain voltage becomes large enough drain voltage becomes large enough this term becomes smaller and larger and larger. So, for a given gate voltage for a given gate voltage if I increase v d s you can see that that will result in reduction of this term that is it will not increase as much as it would if this were not there it would have increased linearly, but because of this increase in v d s the current will not increase proportional to v d s, but it will deviate from the linearity into nonlinearity when and when v d s this entire term becomes equal to v p 0 at which this is the voltage at the drain end of the channel and that becomes equal to v p 0 the current saturates. So, you can see that characteristic goes on deviates from linearity then when that v d s at v d s at this voltage which is the voltage drop across the depletion layer at the drain end that becomes equal to a actually at that then at that point that is v p 0 then you get saturation. So, that is the situation that you have got. So, i d saturates when the channel is pinch drop at x equal to l this almost closes that. Therefore, v b i minus v g s plus v b v d sat that is the voltage drop across the depletion layer v b i minus v g s is voltage drop here plus voltage drop v d sat. So, that becomes equal to v p 0 this channel closes that is the drain voltage at which current saturates. So, that is what we have plotted here v d sat is given by this for a given gate voltage v d sat is determined from the applied voltage gate voltage and the pinch up voltage. So, you can actually I am not going through that you can actually simplify that and write the whole thing in terms of threshold voltage because threshold voltage actually is actually v b i minus v p 0. So, if I take v d sat in this condition v d sat equal to v p 0 minus v b i I take this that see v d sat is equal to I can write it in terms of the threshold voltage v d sat here is equal to take the whole thing to the right hand side. Then you have got v d sat is equal to v g s minus v b i plus v p 0 or in other words see that the v b i minus v g s plus v d sat when that happens that is v p 0. Now, what is v d sat is equal to v p 0 minus v g s I will take it that side minus v b i which is actually equal to v g s minus v g s minus v b i v p 0 v p 0. So, what is this quantity that is v g s minus v threshold. So, what we are telling is in the case of MOSFET also the saturation voltage drain saturation voltage is equal to v g s minus v threshold voltage and the drain voltage it goes through v g s minus v threshold the current saturates this exactly the same thing that you had in the case of MOSFET. In MOSFET also the drain current saturates drain current saturates when v g s equal to v d s equal to v g s minus v threshold. So, that is what. So, that is a nice thing about that. So, you can actually by substituting that term here v b i minus v g s v d sat or v d sat is equal to v g s minus v threshold you substitute it here use binomial theorem and simplify you get the I D versus v g s relationship transfer characteristics exactly same as that of the MOSFET that is very interesting. See this drain saturation current when we use that relationship that is v d sat is equal to v g s minus v threshold which we have found is to be true in the case of the MOSFET also then you substitute in that equation that we have derived and some approximations you do you will get I D s is equal to mu some capacitance into W by twice L into v g s minus v threshold whole square. This is exactly the same characteristics transfer characteristics of the MOSFET in the saturation region. What is in the MOSFET? I D s is equal to mu n c oxide oxide capacitance per unit area into W divided by twice the channel length into v g s minus v threshold whole square. Here all that you have to do is you can use the same equation as the MOSFET only you have to define the threshold voltage as v b i minus v p p 0 that definition of threshold voltage is different here then. So, the saturation drain current is related to this v g s minus v threshold whole square into this c capacitance capacitance of the channel instead of v oxide per unit area you have got capacitance of the channel. What is this epsilon r is the permittivity of the gallium arsenide epsilon 0 divided by thickness instead of oxide thickness you have got channel thickness instead of oxide epsilon r you have got epsilon r of gallium arsenide. You can see for this even if the mobilities are the same thing if I take the MOSFET if I take the MOSFET and if the material is the same thing this will be oxide permittivity and this is the permittivity of gallium arsenide which is about three times larger than that of oxide. So, for the same thickness as the oxide you will get drain current higher if you drain get current higher you will get the transconductance also higher what is transconductance delta i d b delta v g s. So, this quantity is large transconductance is large what we are telling is if I you take MOSFET you can get the driving capability and transconductance better than that of MOSFET because epsilon r is much higher compared to epsilon oxide. This is we are talking about the same thickness of oxide and same thickness of a channel. Now, if I am using instead of silicon if I am using gallium arsenide in addition I have got this term which is much larger than that of silicon plus when I go to short channel devices when gallium arsenide you will have enhanced velocity enhancement effect due to velocity overshoot effects. So, that tells you that gallium arsenide is a very good candidate for high frequency operation. So, this is a nice thing you do not have to remember anything else for saturation region characteristics of the MOSFET replace the oxide with the C channel. So, from this point of view if I want to increase the transconductance or increase the drain current for a given gate voltage I can achieve it not nearly with the high mobility I can reduce the channel thickness and get that, but notice that if I reduce the channel thickness the threshold voltage also will change. Just like the MOSFET in the case of MOSFET your threshold voltage depends upon the oxide thickness. Here also the threshold voltage will depend upon the channel thickness and doping because threshold voltage depends upon V B I which depends upon the barrier head V B I minus V P 0. So, threshold voltage depends upon pinch off voltage pinch off voltage as you can recall depends upon that is pinch off voltage depends upon channel thickness. Thinner the channel thickness smaller will be the pinch off voltage higher the doping higher the doping or if you can see for a given thickness or if you see V P 0 is equal to Q and A square by that for a given thickness if I increase the doping for a given thickness V P 0 will also go up. So, it is a combination of the doping and the thickness exactly like in case of the MOSFET increase the channel doping threshold voltage goes up if I increase the oxide thickness threshold voltage goes up same thing holds good here all the things that we talk of for the MOSFET increase holds good. So, the theme here will be to go to thinner channel thicknesses and may be go to higher doping concentrations when you reduce the thickness because after all the pinch off voltage depends upon the product of N D and thickness square. So, if I change the thickness it has to be accompanied by the doping if I reduce the thickness it has to be accompanied by increase in the doping. So, that I get the same V P 0 that will be a bad news because if I go to thicker thinner layer if I have to increase the doping concentration which is necessary. So, that the resistance is less you your V P 0 will go up V P 0 can be controlled, but if you increase the doping mobility will fall. So, that is one thing one has to remember now. So, this is the transfer characteristics. So, you can have normally people think that you cannot get in a J FET or a MOSFET you cannot get it is always depletion depletion mode depletion mode people think, but you can see I adjust the threshold voltage make positive I can make the how can make the threshold voltage positive threshold voltage is V B I minus V P 0 if V B I is larger than the V P 0 threshold voltage is positive that means I have to apply plus voltage to turn on the device. So, you can get enhancement type of devices with the MOSFET by adjusting the doping or by adjusting the thickness or ultimately by adjusting the threshold voltage you can get positive. If I have a thick layer then usually it will not be depleted with the built-in potential in that case it will be you have to apply negative voltage to turn off the device that is depletion type. So, usually when they talk of J FET they talk of thin layer thick layers of the channel then it will be mostly depletion depletion type of device, but today in the Gallemars integrated circuits they talk of enhancement type of device as a driving device and depletion type of device as the load device is a load resistance or the load device. You can operate it at zero bias by connecting the gate to the source you can see this is the point of operation. So, you can use it as a two terminal device by connecting the gate and the source and use it as the load resistance and this is the driving resistance. So, N channel devices can be made integrated circuits are being made logic circuits using the Gallemars and FET. Now that is three few things before we close down today few items I want to. So, this is the characteristic when we assume that the channel drain current saturates when the depletion layer pinches off at the drain end, but if the channel bits are short this can happen even before pinch off takes place because of velocity saturation. So, I will not go into the details of that, but you can approximate by approximating the velocity field characteristics in this fashion. You know that it is not like this either it goes then saturates or it goes up and comes down because of Gallemars net, but Michael Schur any paper way back and even in his written he has shown that you make this approximation you can convert that particular equation and you can write it in a form for short channel devices in this fashion. I D saturation is you can see all those terms are there W W is there this is the C of S that is the capacitance of the channel silicon and L goes up when the velocity saturation takes place as that is like in the case of the MOSFET because the mobility term gets absorbed in the velocity saturation. So, you get it is shown that you can write it in terms of this that is I D saturation is proportional to the channel capacitance that is this quantity thinner that channel higher is the drain current, thinner the current channel higher will be the trans conductance that is delta I D by delta V G S driving capability is better provided you have got enough carriers there. So, that would actually need to increase the doping concentration also when they make the channel thickness smaller please that will change the slope. So, this is the expression now this is deliberately drawn if I use velocity saturation as 10 to power 7 and if when I use this particular term which is a approximation to the entire characteristics saturating like this there is no velocity overshoot etcetera it goes on increasing saturates at 10 to power 7 that means if I go to high speed it is 10 to power 7 if I do that when I make a device do I get those characteristics what velocity I will get do I get 10 to power 7 what currents I get what trans conductance I get for some experiment people have done that for that. So, to see how the channel length affects the photomicrometer gate length LMRC and MISPAT people have made experiments for example, here this is the whole thing is the channel length the green color there is the channel n region and this red color is n plus region on the top this is the semi-insulating layer and they have put the metal here omicontact is very easy to make omicontact on n plus region rather than on n region invariably they will have they should have n plus region there. Now, I am not going to the technology of this, but what they have done is they have removed this material here etched this material ok they have etched this material say isotropic etching removed this n plus layer removed this n layer also so that thickness of the channel is reduced originally what the wafer they started had n plus layer 1.8 into 10 to power 18 so that even if you put a contact here at the end of this region it is very low resistance. So, when you apply voltage here and for when you apply voltage here that is coming right up to this point because the drop across this region is negligible. So, whatever current is flowing it is collected here similarly whatever current is injected here is injected into a channel here, but notice there is some small gap between n plus and this because otherwise this you cannot have it connecting exactly touching this gate because then it will short. So, there are two things that they did they wanted to study the effect of this n plus layer present here with this n plus layer and without this n plus layer ok. So, this metal contact distance between them is 2.1 micro the portion where they etched this n plus layer is 0.5 micro and this is actually the gate which is 0.25 micro is quarter way this is quarter micrometer 0.25 micrometer gate length channel length is more than the gate length means the contact omicontact is here n plus layer is here n plus layer here. So, you have a channel length which is more than the gate length 0.25 micro on gate length 0.25 micro channel length ok. So, the thickness of this layer n layer was 0.2 microns they have etched 1 micro on from here. So, that actual channel thickness is 0.1 micrometer ok. So, the pinch off voltage corresponded with this 0.1 micrometer thickness and doping 1.8 2.5 into 10 to 17 doping here is that is by using that formula Q and D A squared by twice epsilon or epsilon 0 you get that is a 1.7 volts that is a pinch off voltage. So, now what they did was they made the MOSFET with the n plus layer going all the way up to this point like this. So, in this case channel length is 0.5 microns gate length is 0.25 microns. Suppose you etch off this n plus layer from this end completely that is n plus layer is absent up to this point only in this point here just below this contact n plus then the channel length is from here to here that is 2.51 microns. So, that second case is 2.51 microns channel length, but gate length is 0.25 microns. So, here we have got situation where 1 case channel length is 2.1 microns and in other case channel length is 0.5 microns in both cases gate length is 0.25 microns. So, that is the situation they have done the case 2 n plus retained here 1 case retained you retained n plus in the first case that is removed. So, they made measurements on that without n plus that is no n plus layer channel length is 2.1 micron and gate length is 0.2 microns they observed the g m as 125 milli ampere per volt per millimeter channel width. Now, when n plus layer was present and this layer was present they saw the g m was much higher. Obvious it has got to be higher because if the n plus layer is not present you have got lot of resistance from here to here. As we discussed in the case of MOSFET using this equivalent circuit there is a resistance between the edge of the channel and the source contact. There is a gate source contact that resistance is coming from here to this channel length. When this layer is present the resistance is only very small here. When the layer is absent channel length is 2.1 micron the resistance is higher. So, that is R s including that you will have g m will be much smaller come because if the resistance is absent this is g m 0 if the resistance is present it will be g m 0 divided by 1 plus g m 0 R s it is in case of MOSFET also. So, by incorporating this correction then they found incorporating this correction and using this equation g m is equal to this quantity they found to made the correction they estimated the g m all these terms are known to you v g as v threshold v p 0 everything is known they calculated the v of s saturation velocity. So, when they did that they found that without n plus they got velocity about 1.1 into 10 to power of 7 after making the correction neglecting the resistance they got about 10 to power of 7 saturation but with the n plus they got 1.9 into 10 to power of 7 that is all that you do is measure g m substitute for all these known quantities v p 0 is known and find out the such velocity from that. Since you have made correction for the resistor ok the difference in these two cases is when this is present carrier is injected straight into this channel very close by an n plus layer is present carriers are injected into the high field region suddenly there they can go through the velocity over suit effect whereas, if this layer is not present carrier is injected here into the channel by the time it has reached here it has reached its saturation velocity because there is a drop here. So, when this n plus layer is not present the channel region here the under the gate region there is no velocity over suit effect it has already reached the steady state value but if this n plus layer is present the carriers are injected right here into the gate where the fields are high. So, it goes through the velocity over suit effect. So, what we are telling is the result from that is with gallium arsenide if the source region n plus is very close to the gate region the carriers get injected into the channel cold right away into the channel it suddenly experiences the effect of the high field and it experiences the velocity over suit effect and the average velocity is that you get in the channel is much higher than 10 to power of 7 centimeter per second saturation velocity is 10 to power of 7 it is almost twice you get transconductance almost twice you get velocity almost twice you get frequencies almost twice all that happens. So, that is telling you that gallium arsenide devices definitely have the merit particularly when you go to even as smallest channel lengths which are about 0.25 microns you can do that. Now, the question is whether you can get self aligned structure that has been reported I am not going to discuss that you can get very self aligned n plus with respect to that you can get using tri layer gate structures it more complicated. So, I am not discussing right now because of shortage of time. So, that is the story. Now, what we are saying this if I have to have in summary gallium arsenide has got high impact to get high velocity and high performance. Now, if I want to get higher transconductance you can get the short channel effect and increase the velocity saturation effective velocity to about twice 10 to power of 7. But for a given W VGS etcetera I can increase the gm by increasing the capacitance that can be done by increasing the by reducing the channel thickness. But reduction in channel should be accompanied by increase in doping. So, that threshold beauty can be adjusted to the required value. So, the ultimate thing is even here we are haunted by the problem of high doping effect. So, what is the way to go use say modified structure use gallium arsenide substrate where you can have carriers where there is no doping that type of structure we will discuss that is heterostructure devices and amped devices we will discuss in minus lecture.