 Hello everyone, my name is Ms. Shweta Spatil, working as an assistant professor in electronics and telecommunication engineering department at Valchand Institute of Technology, Solapur. Today's topic for the discussion is the carry look ahead adder. Learning outcomes. At the end of the session, the learners will be able to design a 4-bit ripple carry adder, design a 4-bit carry look ahead adder CLA. Contents. First is the ripple carry adder RCA, second is the 4-bit RCA, third is the timing analysis of 4-bit RCA, fourth is the carry look ahead adder CLA, fifth is the 4-bit CLA and sixth is the CLA algebraic formation. Ripple carry adder. The full adder can be used in the creation of multi-bit adder. The simplest architecture using full adder is the ripple carry adder RCA. Full adder are used to create some and carry out of each bit position. 4-bit ripple carry adder. This is the block diagram for the 4-bit RCA. Here 4 full adders are used for the 4-bit ripple carry adder. Here full adders are located at position 0, position 1, position 2 and position 3. This full adder may be called as half adder because C0 that is seen is equal to 0 here. The C out of each full adder is used as the C in for the next higher position. The sum of position 1 cannot complete until it receives the carry in C1 from sum in position 0 and so on for other C in. In this way carry ripples through the circuit from right to left. This configuration is known as RCA ripple carry adder. RCA sum does not become valid until the carry propagates or ripples through the chain of full adder. So that each subsequent full adder needs to wait for the carry to be produced by the preceding stage. The carry is said to ripple through the circuit thus giving this approach its name ripple. Its delay becomes considerable when scaling to larger input sizes. Example if instead of yarn that is 4-bit if we take 32-bit, 64-bit delay becomes considerable. A simple analysis of timing can be stated as if the time for full adder to complete its positional sum is equal to T to the base FA then the time for yarn bit ripple carry adder to complete its computation T to the base RCA is equal to yarn into T to the base FA. Timing analysis of 4-bit ripple carry adder, this is the block diagram for that. Each full adder can be implemented by two half adder and one OR gate. It gives the same two table operation like the full adder. The carry ripples through the adder chain here. Full adder 0 takes three level, level 1, level 2 and level 3 of logic to complete the computation of full adder 0. When C1 reaches the FA1 its first half adder already completed its computation because it doesn't require any carry from full adder 0. This means only two more levels of logic that is level 4 and level 5 are needed to compute C2. From this it is concluded that number of logic levels for 4-bit RCA is equal to 9. This analysis determines the number of logic levels in the adder. The inputs to the adder are A, B and C in and are always assumed to update at the same time. The actual gate delays can then be plugged into find the final delay. Number of logic levels for yarn bit RCA is equal to 3 plus 2 into yarn minus 1. Carry look ahead adder. In order to address the potentially significant delay of ripple carry adder a carry look adder was created. Additionally, circuitry is included to produce an intermediate carry in the signals immediately instead of waiting for them to be created by the preceding full adder stage. This allows the adder to complete in a fixed amount of time instead of one that is case with the number of bits in the RCA adder. A carry look ahead adder contains circuitry that determines whether previous adder stage produces carry. 4-bit carry look ahead adder. Same structure like the RCA 4 full adder are located at position 0, 1, 2, 3 but here carry of the preceding stage adder is not given to the next adder position 1. This circuitry produces the carry in for each stage without having to wait for the carry to ripple through the prior stage. To create carry look ahead circuits that are only dependent on the system inputs as opposed to intermediate carry out signals. This will eliminate the ripple delay. The look ahead circuitry considers whether the prior adder stage is created carry by considering two conditions. Whether a stage will generate a carry and whether a stage will propagate a carry. Let's look at the truth table of full adder. This is the truth table of a full adder. Here because of three inputs there are total eight combinations. For the input code where C in is equal to 0, C out we get like this. That is full adder generates a new carry 1 when A is equal to 1 and B is equal to 1. This behaviour can be described with the expression G for the generate is equal to A dot B because when we are considering A, B and C out at that time whatever the AND gate truth table operation is there, same operation we are getting here. For the input codes where C in is equal to 1, full adder propagates the incoming carry 1 when A is equal to 1 and B is equal to 1. This carry 1 is propagated at the output as an C out. Here this one is coming as an C out, this one and here even though there are two one, one is going to be propagated as an C out. This behaviour can be described with the expression P is equal to A plus B. The entire expression for the carry out can be written as C out is equal to G plus P dot C in. C out is equal to A dot B plus A plus B dot C in. Here G is written as A dot B and P is written as A plus B. CLA algebraic formation, the expression for the subsequent carry terms written as this. C1 is equal to G0 plus P0 dot C0. The C1 expression only depends on the inputs A, B and C0. For the C2, we can plug into the expression C1 to create the expression that only depends on A, B and C0. Instead of this C1, we get the expression G0 plus P0 dot C0. Similarly, we get the C4. All of these expressions only depend on inputs A, B and C0. These are the references. Thank you.