 So, welcome to this lecture on advanced digital system design. In the course digital system design with PLDs and FPGAs. In the last lecture we have looked at how to reduce output delay in finite state machine. There were two techniques basically to decode the output from the next state instead of the present state. The second technique was to encode the output in the present state ok. So, quickly before getting into today's portion we will run through those slides quickly. So, let us look at this. So, basically our aim was to reduce the output delay and so these are the two techniques we said output decoding from next state. So, in the normal course of time we decode the present state to generate the output. Our idea is that hopefully there is a you know if you put the output logic here and followed with a set of flip-flops. So, that when the clock comes you know you get the output along with the present state. So, the only output delay is Tcq that is the idea. So, that is how you know we have put it from the next state logic you have output logic and the output flip-flops. Now, there are two paths to register to register two different kind of paths. There are many paths maybe if there are three flip-flops you know you know 3 x 3 9 if there are two outputs and 3 x 2 6 paths in this side. But here at least by the number of terms this particular path has more terms Tcq, T next state logic, T output logic and the setup time ok. Earlier one advantage is that this is coming you know kind of one after the other. So, it could be optimised earlier if you look at the earlier diagram this output logic was after the register boundary. So, there is no way it can be combined with this. So, there was no kind of optimisation possible there. But it may happen that this two put together can become as equal to the earlier one. Then we have an advantage because everything is same the clock cycle is same, clock cycle is not affected and the output delay is reduced. So, that is the advantage of this scheme and the other scheme is to use the present state as output definitely there are lot of points to kind of ponder. Because how many number of outputs are there, how many number of state flip flops are there, what is there, one could be greater than the other one and things like that. But at least we have seen that when the number of outputs are like equal to the number of flip flops. And if the pattern is unique for each state straight away we can use one of the flip flops as for one output and the other one for the second output there is no harm. But if there is any kind of repetition like in this case S1 and S3 has the same output pattern okay. So, in that case we will be forced to add an extra bit that means the present state the state flip flops will be 3 flip flops though we have only 4 states. This is to decode the output from the state because there are repetition as far as output pattern is concerned in this case. So, we add extra bit to kind of demarcate them and but still we end up having at the cost of one flip flop our output delay is reduced. And we have seen another example much more complex example where one output pattern is repeated twice and one 3 times. Then we are forced to add 2 extra bits to make a difference like 0 0 0 1 1 0 and as I said there are 5 state flip flops or the present state flip flop. But that you know account for like you know 2 raise to 5 32 pattern but we have only 4 output there are only 2 raise to 4 possibilities. But because output is repeating in state we are forced to add this to extra bit you know. So, the rule is that you will identify the state with same output values from these identify the state where one output pattern repeat maximum. And additional bit to make the output pattern distinct you do not have to worry about whether something is greater than or less than if you try this algorithm this will work out. And it is a good thing to try you know it is a really good thing to try the tools may not do it. Because you know that we have already seen that the various attributes the tools normally allow the sequential kind of encoding the gray coding or the 1 out 1 and things like that 1 out 1 as a possibility of this happening or because output can be delay can be reduced we will see that later when we look at the FPGA. So, that is what we have seen in the last lecture today we are going to look at a serious issue called synchronization okay. And that is related to an issue in a flip flop called metastability basically it is not it is an issue inherent in a cross couple latch okay. Since we build flip flop out of a cross couple latch the same problem comes in the flip flop and we build data path and the finite state machine using flip flops. So, we are again have the same problem. So, it all start with the latch but we do not have you know time to look at from the transistor level or at the inverter level down to here okay. Actually normally if you learn that way you can get a good grip on it. But we will abstract it as far as the flip flop is concerned what is the rule to follow and I will tell a gist of it why it is happening and how to handle it that should equip you to handle most of the situation you come across. We are not again discussing all possible advanced technique to do the synchronization which I hope you can follow it up with the basic and this course we are already you know it contains quite a lot of things now to add this is maybe little too much of a scope. So, let us look at the problem of metastability in the flip flop. So, we have already learned that in an edge triggered flip flop. So, you have a clock D and Q normally a behavioral kind of description is that when the clock edge comes whatever is at the D is propagated to Q with a delay. But we know that for that to happen properly okay the data here as to arrive sometime before the active clock edge that in this case the positive edge and that time is called setup time or TS not only that the data after the clock edge it has to remain there for sometime that time is called hold time. So, unless the data the input meet the setup and hold time the Q will not get this copy of this D copy or the value of D the D will not be transferred to Q properly okay. So, that is what is I mean we have many a times we have learned that for successful transfer of operation of the edge triggered flip flop you have to meet the setup and hold time at the input many a times it is not discussed what happens if it is not met okay. So, that is what we are going to do today. Now, the game is that so this is the essential behaviour of the flip flop the data should arrive setup time before the clock edge data should remain kind of hold time after the clock edge active clock edge. And if so happens from the active clock edge with some delay this output appears okay. Now that means that though we say in a functional way many a times when you learn at the beginning you draw kind of the waveform without delay there whatever you know the edge whatever is the value at the edge it is transferred to the output you know that is how it is done at a behavioural level. But there is no magic you know there is nothing can work like magic just an edge comes the output cannot instantaneously goes there. And you also would have studied a master slave flip flop which is working as an edge triggered flip flop because you most of you would have learned master and slave configuration. And that is the essential logic circuit for edge triggered flip flop and most textbook give 2 cross couple latch one after the other. So during the negative clock period the master is in the transparent mode when it goes positive the master is cut off and the slave whatever is captured in the master is transferred to the slave and you get the output okay. So there is no magic there is no like edge trigger magic you know as soon as the edge comes you know as if something happens during the edge you know nothing happens during the edge in digital you know that either it is 1 or 0. So something happened to the master latch during the clock period is low something happened to and that is cut off something happened to the slave latch during when it is high whatever is captured in the master is transferred to the slave okay. So that is why this setup and hold time come and as I said I am not going to have an analysis due to lack of time but then you can definitely go back and look at the architecture of the master slave not only what you have learnt any master slave there are different you know master slave architecture though some things are not called the master slave you can take the like if you remember the 7-4 TTL series you can take 7-4 D, 7-4 flip flop and look at the internal diagram you will find that there is a kind of master slave architecture which is not same as what you have learnt in say in the text book and the number of gates used will be less and the propagation delays also will be less in those configuration. But the analysis is same so what I am saying is that the game in a gist so that you know I do not leave some curiosity kind of like if I say accept as it is and you do not know where it is coming from suddenly a magic. So I just want to tell that when the clock period is low the master latch will be in the transparent mode okay. So master latch is capturing the input but the latest when it can capture is sometime before this is getting cut off okay because when this edge comes and when it turns positive master input is cut off okay. So but the master latch to kind of set there is a cross couple latch delay okay. So that delay before this clock edge is a setup time and we have learnt that there will be because the master is enabled during the negative the slave is negative period the slave is enabled during the positive clock period. So there will be inverters in the clock path. So there will be like normally you will have the master latch delay minus inverter delay will be the setup time because that is the latest a master latch can set before the clock edge happens okay. Now the clock edge comes now because of the inverters in the clock path it takes some time to cut it off input to cut it off. So during that time nothing should happen to the D then the master latch will be upset. So upset in the sense the value will be upset. So there is a hold time which is equal to the you can say the inverter delay in the clock path. So that is a hold time. And now when this clock period is enabled the slave latch will take some time to set that is the propagation delay okay. So that is how this comes you know as I said during the negative clock edge clock period the master is in transparent mode. So before it is cut off what is the latest the master can latch that is the setup time that is a cross couple latch delay minus the inverters any inverters in the path. And when it is cut off when it goes to positive that inverter delay has to be kind of met because then only it will be really cut off that is the hold time. And then when it is you know when it the slave is enabled the master output is latch down to the slave. So that latch delay plus any inverter delay in the clock path if you analyze it you will get that is the propagation delay now. So that is how this comes that means once again to for the D to go to Q you have to meet setup and hold time that is all. But what happens if this is not met okay that means the master is getting cut off and you are still changing the input okay. So what happens then what happens is that again that need a little bit of analysis which I cannot kind of which we have to go back to the cross couple latch. So since as I said the lack of time we will just kind of abstract it. What happens is that if the setup or hold time is not met many things can happen. One thing the bus can happen is that like suppose the output was 0 here and you are trying to drive a 1 upon the clock edge that means we are expecting this 1 will come here okay. But if the setup or hold time is not met then we are not sure the whatever the 0 at the output may remain there 0 or it might become 1. So we cannot say maybe it will change state or it may not change the state okay. Still an acceptable behaviour there is no harm because earlier it was 0 we are expecting it to go to 1 since it is the data is coming in this changing in this window it is not you know setup it is not the data is not setup properly. So data is not transferred still it is okay because it is 0 this is 1 and we are hoping that next clock edge come. So if the data remains and normally the data does not remain just like that data will remain for 1 or 2 clock period and the data is transferred properly. So a misstrigger is a very good thing you know the bus thing you can hope for if the setup and hold time is violated the bus one can hope is that let it misstrigger that means instead of going to 1 let it be 0 there is no harm because earlier it was 0 and the next clock edge it becomes 1 okay. Now another effect of this metastability in flip flop this behaviour is called metastability another effect of that is that if the data is changing within this window close to the clock edge it will take the output will either become 0 or become 1 but it will take a long time to resolve like that say output was 0 it was going to 1 but it would not transit fast it will take some time and settle it to 1 okay. So that is another issue which is already bad because in a register to register path we say t clock is greater than tcq plus tcom plus tsetup and we have fixed the maximum tcq. So if it takes long time to resolve that will violate the setup time at the destination flip flop and that can cause metastability there okay. So it can propagate this old game can propagate from one flip flop to the other is very bad the worst case you know. So two things either it misstrigger it takes long time to misstrigger like even for output to resolve it takes long time third effect is that it can get stuck in between the logic levels. Suppose you know that in a 5 volt say the lowest high value is say 3 volt and the highest low value is 2 volt we will expect always the logic want to be greater than 3 volt and logic 0 to be less than 2 volt but what happens is that in the case of metastability it may happen that the such a flip flop can have a output which is 2.5 volt okay. Now that is very dangerous if that 2.5 volt goes to a logic circuit a combinational circuit what can happen is that it can drive the transistors inside to active region. So instead of kind of a switch it will act as an amplifier any noise it will drive to saturation so it will start switching okay. So there could be lot of errors if it is not kind of in the design it is not taken care this metastability can cause lot of errors okay. The misstrigger is very safe because as I said it may go to 0 or 1 still it is okay but if it gets stuck in between and that whatever is being driven can also get into metastability. So it is a disastrous thing and many a times this issue is not taught in the basic course but it is a very serious thing you know and most of the time the design practices a noise does not consider the metastability it is a really bad thing to do. But most of the time because of the reliability these devices are very fast and the probability of that thing happening is less we are saved but this should be kept in mind. So that is the basic issue what is called metastability okay. In an edge to get flip flop if the setup or whole time is not met we are not sure of output it can take longer to resolve it can get stuck in between which is the worst kind of thing. So that is what I have summarized here if setup whole time is violated flip flop can sample input wrongly output could be 1 or 0 that means in the case if it was 0 before it may remain at previous value or transit to a new value output may take a long time to resolve if the input changes close to clock edge. The worst case output can get stuck in a non logical value and it can remain there in such a state for indeterminate amount of time we do not know how long it takes you know maybe it will come out of it after 1 second 1 hour 2 hour 1 day we are not sure okay. We cannot say and it is a probabilistic thing you know we cannot definitely say that this will happen or if it happens it comes out with certainty okay it is a probability. So that is metastability but let us come back to the data path and sequential circuit as I said we use flip flops and combinational circuit okay. So all the data path are built of the flip flops or registers and combinational circuit. Similarly the FSM also use the registers the state registers and the combinational circuit next state logic output logic and so on. So now this has potential chance of like probably there is a chance of flip flop getting into metastability but when we design we analyse all the register to register path and we choose like at the destination register we always try to meet the setup time by choosing the proper clock period like we will say t clock is greater than that path delay that is taken care in the analysis while simulating all that we make sure that the clock period is not exceeded. Similarly at the destination register we also make sure that whole time is not violated but is violated we add extra combinational delay and sort it out you know so we take care of these both condition and if there is a skew of the clock which we have not I think formally learned in this course which we will do when we go to the FPGA I will club that part in the case of with the FPGA because there is a reason to do that we will see that when we learn I mean how to take the skew of the clock in the analysis we will see that okay but a proper designer takes care of the clock period take care of the skew take care of the whole time violation again with this skew and all that so everything is done properly. So you have a data path register combinational circuit register we say okay the clock period should accommodate the tcq t comp and the setup done the clock period is chosen and if there is a skew that is taken care similarly to avoid the whole time violation here we have to make sure that the minimum delay of this flip flop plus the minimum combination delay should be greater than the minimum whole time. So that is also taken care similarly with the FSM you have the logic here decoding the next state and output from the present state and we again here make sure that the clock period is met t clock is tco plus t comp t logic plus the t setup time and the whole time again tcq t logic t comp minimum should be greater than the t whole minimum this is all taken care. So what is why are we worried about metastability okay. So the question is that we take care of in a data path in an FSM we take care of the destination register setup time and the whole time okay. So why like that is an essential part of the design and the timing design then why do we worry about the metastability in flip flop because it is only violated then the metastability happens. So that is the question we take care of the setup time and whole time violation in register to register path in sequential circuit and data path and when can metastability happens in data path okay. So that is the question. So look at this picture then you might get a like or look at this picture where things can go wrong like we have analyzed this path you know from something clock comes the output change it propagates through here and it comes here nothing can happen because we have taken care the clock period is greater than this path delay. So where things can go wrong that is so we will let us put this picture of the data path of the sequential circuit now look at where things can go wrong and I am also showing some input here directly coming to this combinational circuit. Now you know that we have some input to this register we have some input to the combinational circuit and we are not sure where it is coming this is coming from. Similarly the state machine has inputs external inputs maybe some inputs are coming from the data path some inputs are coming from some other place. So now the crux of the problem is these you know these inputs we are not sure where it is coming from it is okay if all the inputs are coming from a register clock by the same clock but assume your data path has 2 clocks and this is the clock and there is another clock 2 and there is a register which is clocked by the clock 2 that output is coming here then that has no phase relation with this clock and this data you know propagating through the combinational circuit may not meet the setup time here okay. So there could be a problem of metastability here okay similarly these inputs we do not know where it is coming from maybe it is not from the same clock or it is coming from a process which is not related to this clock say example is that something is moving and there is a limit switch it touches a switch and that switch output is coming saying that the limit is reached here so that probably that movement is driven by a motor which has got nothing to do with this clock. So that process has no relation to the phase of the clock here so it can violate the setup time at this input. So whenever there are inputs which is not synchronous to the clock you are clocking the registers they can cause metastability in the respective register. So this input can cause metastability here this can cause metastability in this particular input flip-flop okay now look at the state machine once again this the state flip-flop to the state flip-flop path absolutely no problem we have taken care of the clock period whole time this queue and so on. But you see there are inputs from maybe from the data path which is clocked by the same clock but maybe one of the input is coming from elsewhere which has no phase relation to this clock then that can cause metastability in this flip-flop because it propagates through it does not matter because it is coming randomly this logic won't do any good you know like if it is quite random with the clock this logic delay I mean doesn't it makes no difference okay because the whole pattern is shifted by a constant delay as well as the kind of the probabilities are concerned it doesn't upset the probability of a setup whole time violation because a constant delay will not do any good. So these inputs which are not synchronous to the clock are the culprits of metastability in a sequential circuit so and we call that as asynchronous inputs okay so asynchronous inputs in a data path like this or like this or in a sequential machine sequential finite state machine the asynchronous input can cause metastability in the flip-flop okay. Now the name like the solution is in the name itself the metastability happens because the input is not synchronous input is a synchronous so if somebody ask you what is the solution like you know even if you have no clue you can say yeah asynchronous input is causing the metastability so synchronize it okay like if it is synchronous it doesn't happen you can boldly say synchronize even if you don't know how to synchronize so these are this is one of that type of question to answer it is very easy but you may not know how to do it okay. But maybe in an interview you can kind of impress people maybe that question can give you a good job you know like why metastability happens in sequential circuit is asynchronous input what is the solution you say synchronize it you know then you get the job you get a good salary. So we will see how to kind of you know synchronize it so when I want to bring clarity to that asynchronous input to a sequential circuit can cause metastability in flip-flop. When we say asynchronous input it is an output from flip-flops working on a different clock reaching the destination it is output generated by some process not synchronized to the sequential circuit clock as I said maybe something is moving which is touching a switch that movement has got no relation with the clock which we are clocking the input registers. So that those are asynchronous input how to solve the problem as I said synchronize the input to the sequential circuit clock okay that means that you have to there are edges which is changing randomly the input is changing any time. But now we have to make it change with respect to the clock of the our system clock like we have a sequential circuit or a data path now we have to make sure that this input which was kind of no phase relation to the clock we are clocking the data path of sequential circuit we have to make sure that this input change in phase okay with a constant phase relation to this clock okay. So that is simple because suppose assume this was a kind of scenario this input was coming from outside going through the combinational circuit to the some flip-flop in a sequential circuit now this was asynchronous okay. Now how to synchronize it what we do is that we put a D flip-flop put that asynchronous input connect that to the D of the flip-flop and the Q you take it and give it to this particular combinational circuit. So this is the target sequential circuit or data path this is the synchronizer we call it as single stage synchronizer because there is only one flip-flop okay. Now if you look at the clock waveform a clock comes and whatever is the analog input here if it is like this then it appears here with a delay of TCO every time you know anything like even if it changes before upon the clock edge only it changes a state and you know that now it has become synchronous because every time after the clock it appears neatly with a delay. Now we are sure that when the next clock edge comes here it is setting up properly because much before that the data is set up here. Now you have the time for it to propagate through the combinational circuit and meet the setup time okay. So that is how it is synchronized it is same now like you have a tcq plus tcom plus tsetup that should be less than the clock period okay. So we have kind of synchronized we made sure that irrespective of the input change here the output is synchronized to the clock edge. So just a flip-flop that is all what we need to synchronize okay but fine I mean that sound great you know the really great. Once again a clever student will ask a question is the problem solved. Now we said that this is changing with no relation to the clock and that comes here and upset the destination flip-flop causing metastability here. But now we have the same issue here we have put a flip-flop and said fine now the data appears with a delay and it is the setup time is met here but what about this flip-flop okay. Now the data at the input of this flip-flop has no relation to the clock here. So now this can get into metastability. So we have not kind of solved the problem right looks like this is a kind of cheating you know you shifted the problem okay. So we did not solve the problem we shifted the problem. And the question to ask is again is there a good thing to shift the problem at the outset at least that is the problem with the pictures you know I have drawn a picture at the kind of a raw impression is that we have not kind of improved upon the situation. But it is not so because in a like you see there is a thick line here and there is a very thin line here okay that should give you a clue in a sequential circuit there could be 20 flip-flops and an asynchronous input reaching the 20 flip-flops can put all the 20 into metastability okay. But now we are catching that analog input in a single place okay. Now earlier it might propagate through different combinational delay you know we know that when you say a comm here we have multiple paths if there are 20 flip-flops here there are 20 different paths and depending on the delay we are sure that maybe at least few of the flip-flops can get into metastability because the path delay could be different. But now that means this input is sampled at different time by different flip-flops. So with the random behavior of this input we are sure that 1 or 2 can get into metastability say I mean I am say under the quotes because we have to really see the probabilities which we have no time to analyse in this class. But I suppose you get the picture but then the situation is improved because we are put a single flip-flop and sampling it it is tightly controlled there is no path delay it is directly coming here and if at all a flip-flop get into metastability is this flip-flop not all these okay. Now the only hope we have is that instead of all the flip-flops getting into metastability we have a single flip-flop might get into metastability and we are hoping that before the next clock edge it comes out of metastability okay that is that is the best hope we can have in a single stitch synchronizer that it may happen that this solve the problem it may happen that this get into metastability. But if it gets into metastability it comes the output comes out of metastability with a proper margin so that it can propagate through the combinational circuit and meet the setup time for the next clock edge okay. So we assume that definitely the analog input cannot be a very narrow pulse it has to be at least one clock period duration so that even if it misses one it is caught in the next okay. So naturally and we know that because we have put a flip-flop here it has to be there for at least one clock period then only it can propagate through that so there is a latency the use of synchronizer will add a latency. So it will be detected by the sequential circuit only after a clock and that also necessitate that the input pulse would should be more than one clock period wide you know to be able to properly propagate here. So this is how the synchronization is done we have not completely solved the problem. But we will look at it you know as I said we have isolated the problem to a single flip-flop a single place sampling is done earlier the sampling was done at multiple places at multiple instance of time because of the variation in the path delay now it is done in one place okay. So if it is solved it is solved for everything if it is not solved it is not solved for all other flip-flops. So it is better than the earlier case earlier we had no control like some might get into metastability some may not but here it is tightly controlled. So let us come to that so that is what is listed here okay. Now the final analysis is that the synchronizing flip-flop can get into metastability but the problem is isolated to synchronizing the flip-flop but we are assuming that before the next clock edge it comes out of the metastability and we also assume that the input remains valid for one more clock cycle to be correctly sampled and captured by the synchronizing flip-flop in next clock. So now the good news so this is a single state synchronizer this is a synchronizer this is a sequential circuit the good news is that this the probability of a flip-flop remaining in metastability decreases exponentially with time okay. Now mind you read carefully the probability of a flip-flop remaining in metastability decreases exponentially with time that means that by if this analog input sorry asynchronous input violates the setup time or hold time and if this get into metastability as the time passes the chances of it coming out of the metastability it is a chance it is a probability is higher and higher as you give 1 second extra the chances are more you give it more time you have more chances of it coming out of the metastability it is probabilistic we cannot say deterministically 100% of the time it will come out but we increase the probability okay. So the metastability we can only handle probabilistically so what we do is that we will reduce the probability of you know or we will increase the probability to such an extent that in the lifetime of the system we are building this happens very rarely you know that is a basic idea behind it okay. So what is the time available for you know the flip-flop to resolve that time is called metastability resolution time that is the time metastability resolution time is the time available for this output to resolve come out of metastability okay. So now if you look at it you have a full clock period available t clock but you know that once the output get into metastability it should come such that the setup time is met here by the next clock edges. So if you have a clock period it has to be resolved t clock-t setup-t combination delay then only if it is resolved it will be correctly setup here. So for a single state synchronizer the metastability resolution time that is a time kind of available for the output to resolve to a valid state is nothing but that is called tr the metastability resolution time is t clock-t comp-t setup so that is clear okay. Now say that this has to be ready t setup plus t comp you know which is subtracted from the clock period that is it. Now hour it will be good if you can increase this okay. So suppose we like you know the situation is like this we found that you know there is an asynchronous input we try to synchronize it we put a flip-flop and we do some analysis we find the tr and find the probability there is a analytical expression for doing it we can model that and get an expression then we find that the probability is not very low that is remaining in metastability then we have to increase the tr so that to make that probability very low that is again. So suppose we have calculated this we found the probability and we find that it is still high there is a high probability that will remain then we have to kind of increase it. Now one way of increasing is that to reduce the clock period but that is you know that is not on because we have a when you design a circuit we have a clock target okay depending on the performance we need like we are doing some computation and we have a requirement of a throughput. So many operation per second and we know the data path architecture how many clock cycle it takes for the computation of the result we are looking for. Then we fix the clock period and we go back and design to meet this clock period requirement. So we cannot arbitrarily kind of reduce the clock period so our aim is suppose to increase the tr because we find the probability is still high so we want to reduce it. So what to do next like t clock cannot be reduced okay sorry t clock cannot be increased that will affect the performance. So the next question is that and the setup time it all this depends on the technology you are working with suppose you are working with 22 nanometer technology the setup time is fixed for a flip flop nothing can be done about it okay. So we may not be able to do anything with this so the question is that can we make reduce this combination delay okay say 0 can we make it 0 okay. So look go back and look at the single state synchronizer we are asking whether we can make it 0. So no magic we cannot do any magic the problem is that this flip flop output is going through the combinational circuit and reaching here. So to make it 0 what we do is that we block it okay that means we put another flip flop here okay that means this flip flop output is going to yet another flip flop input advantage is that there is no combinational circuit in between. So as far as that path is concerned the combinational circuit is not there so that is called a double state synchronizer okay. So that is what we do a double state synchronizer our aim is to reduce the probability of once it get into metastability decrease the probability that it remaining in metastability. So we give more time so now you see that there is a clock period here between these two and this has to resolve setup time before the clock period. So the resolution time metastability resolution time of the first flip flop in a double state synchronizer is now increased it is a t clock – t setup earlier it was only one stage it was t clock – t comb – setup okay. Now we have reduced it and nothing comes free we know that in input changes it will take two clock cycle to propagate it here. So there is a latency after the input changes after two clock period only the input will reach the sequential circuit. So that is the price we pay we have a latency of two clock period okay. Now suppose you find the tr now it is better than earlier you find the probability you find oh no it is still kind of probability is quite high you want to still reduce. So we have to increase tr further okay. Now we are already at the tether end we have only two terms one is t clock and t setup. The game is to reduce t setup as I said this is fixed and we cannot do anything and now we are forced to increase the clock period. But if you increase the clock period the performance of this sequential circuit will suffer we want to do we do not want to do it. So now the next question then to ask is that let us not reduce the frequency of this clock but let us reduce the frequency of this clock okay. So what we do is that we will put a clock divider like assume that the clock is coming from this side we put a clock divider say divide by 2 or divide by 3 or 4 like that and then give it a log clock to the synchronizer but the sequential circuit will work with the original clock. So that is how that you know if we increase t clock system throughput will be affected. So let us keep the system clock as same and we reduce the clock frequency by dividing the system clock and that is called multiple cycle synchronizer because it takes multiple clock cycle to synchronize okay. That is why it is called multiple cycle earlier it is double stage it will be 2 clock cycle to synchronize. Here it is multiple clock cycle to synchronize so that is the game here in a multiple cycle synchronizer wherein you have the clock of the system could be sequential circuit or a data path which is divided by a counter mind you when I say modern counter n is not a huge number like say 20 or 64 or 128 this modern is like 234 like that you know it is not a big counter we cannot have such a kind of large discrepancy between the synchronizer and the system clock. So now you see the TR is now because this was a clock period when you divide by mod n the clock period is increased by n okay. So divide by 2 the clock is divided by 2 so the clock period will be 2 times t clock. So in a modern counter the clock period is n into t clock so the TR is nothing but n into t clock minus set of time. So now we are like improved the TR by order of like if it is 2, 2 times if it is 3, 3 times or 4 times and things like that. So we have really improved and this should be sufficient like if you find the probability of a double set synchronizer is that offer is not good enough if you give it 2 times or 3 times it will improve because we are talking about exponential okay. We say the probability of that remaining in metastability decreases exponentially with time. So if you give twice it goes exponential and the advantage you get is exponential so normally this should be sufficient okay. So now you know that the latency is 2 clock period but the clock period itself is n into t clock so it is 2 n t clock there is lot of latency here like if something happens it takes if suppose n is say 3 it takes 6 clock cycle to reach here which you have to see whether it is kind of tolerable for the system you are working with okay. So it is a multiple cycle synchronizer which reduces the probability of this particular flip-flop remaining in metastability for long I know like this remaining in metastability okay. So n is 2 or 3 and there is many times people instead of doing like this using a counter because at the end of it like when you say suppose you say there is a mode 3 counter or mode 4 counter it is 2 flip-flop okay. So use 2 flip-flop for synchronizing and 2 flip-flop for counter some people okay. Now there is another issue here which we have not kind of address you see there is a because of this mod n counter there is a skew between this clock and this clock okay. Now you see that this clock is coming with a delay of this counter okay. So and this clock comes early so like if you analyse this path to this path the available time is not t clock t clock minus t skew. So like there is this skew affects very badly because it eats into the time available because now it is not that t clock is greater than tcq plus tcom plus t setup it is t clock minus skew should be greater than this particular path delay. So normally what is done is that since that to avoid that combinational the large path with this skew happening a d skew flip-flop is put so that the problem comes here that means you say t clock minus t skew should be greater than tcq plus t setup to to kind of not to affect the large delay path. So a d skew flip-flop is added here in the multiple cycle synchronizer. So I think we are coming to the end of the lecture. So what we have looked at is the problem of metastability in flip-flop that stem from the an issue in the cross coupled latch which is used in the extra grid flip-flop. So we have to meet setup and hold time and I said clearly explained in somewhat detail that it comes from the master latch the setup time with some clocks you know clock path inverter delay you have to subtract it. Then that delay of the clock path will add to the whole type then the slave latch delay is a propagation delay and we say that for a successful operation it has to be met if it is not met three things can happen the output can be valid so it can be 0 or 1 we are not sure it can be it can take long time to resolve it it can get stuck in between and this happens particularly in a sequential circuit or a data path with asynchronous input because all register to register path we do the proper analysis for clock period and the whole time violation. So nothing can happen go wrong but the asynchronous input can create trouble because it is not synchronous with the clock it can change any time and asynchronous means any input which is not having a phase relationship to the clock we are using for the sequential circuit. The solution is to use a synchronizer that can be achieved by a single flip-flop but if that can get into metastability that is better than many flip-flops getting into metastability and our hope is that it comes out of metastability by the next clock edge and we have also seen that the more time it has for to resolve more the probability of it is coming out of the metastability. So idea is to give more time for it to resolve so we have seen the metastability resolution time for a single stage flip-flop it is t clock-t-com-t setup to remove t-com we put two stages of synchronizer then it becomes t-clock-t setup time and if that is not enough we reduce the clock of the synchronizer by dividing it then we have n-t-clock-setup as the resolution time the latency is 2n-t-clock and this counter can add skew in the path the clock path that can affect the total clock period available. So sometime we add a discu flip-flop so that is about the synchronization so I have address the issue I have already given a solution so what is remaining is maybe little more detail one more solution and something specific to the state machine when the input is asynchronous and something about the reset then we can wind it up I am hoping that in the next lecture half way through we can wind it up. So this is an important topic I was doubting whether I will be able to cover that in the course but then not to talk about is it kind of if not good after learning you know so much about how to design and all that. So I think it is an important topic please go back read it and if you want additional material you can kind of look at the text books if it is available or look at some papers the white papers which is available in the with the manufacture so that this can be learnt well. So I wish you all the best and thank you.