 Hello, and welcome to this presentation that describes the linked list management support by the LPDMA and the GPDMA. The first approach to configure a DMA transfer consists in initializing the channel memory mapped registers. This is called direct programming mode. However, the same channel can only be reconfigured when the ongoing transfer is completed. In order to decouple software preparation of transfers from their execution, the linked list approach is more convenient. Each item in this linked list is called a linked list item or LLI. The LLI is mapped in memory and contains an image of the values to be initialized into the DMA channel registers. Thus, DMA channel register programming becomes an indirect operation. The base address in memory of the data structure of the next LLI, n plus 1 of a channel X, is the sum of the linked base address of the channel X, which is a static value, and the linked address offset, which is provided by the previous LLI. The data structure for each LLI may be specific and contains the list of channel registers to be initialized. By using the UT1, UT2, UB1, USA, UDA, ULL, plus UB2 and UT3 when present, the user can select which channel registers will be updated during the link. Therefore, only the difference between two consecutive LLIs has to be programmed. The left part of the figure represents the DMA register file. The right part represents the LLI1 and 2 allocated in memory. This figure describes the link operation when LPDMA channels 0 to 3 and GPDMA channels 0 to 11 are used. The address of LLI1 is the sum of a base address programmed in the CXL bar register and the offset present in the CXLLR register. LLIN provides the offset used to locate LLI N plus 1. When the link is performed, the channel X linked list register file is updated from the values read in the LLI1 data structure. Later when the transfer related to LLI1 has been completed, the LLI2 data structure will be loaded into the channel X linked list register file. Since all UXX control bits are assumed to be 1, the entire channel X linked list register file is updated. The CXLLR register contains control bits that enable the user to select which registers of the channel X linked list register file will be updated during the link. In the example on the right, it is assumed that only the CXTR2, CXDAR and CXLLR registers will be updated when linking from LLIN to LLIN plus 1. Control bits related to registers that are not updated are cleared. These are UT1, UB1 and USA. Control bits related to registers that are updated are set to 1. These are UT2, UDA and ULL. This capability of selecting the registers that are updated is very useful to minimize the memory footprint and accelerate the link when consecutive LLI's share common configuration settings. For example, when two consecutive transfers are performed from the same source peripheral, it is not necessary to reprogram the source address. This figure describes the link operation when GPDMA channels 12 to 15 are used. These channels support additional functionalities, such as block repetition, interburst offset and interblock offset that rely on two registers called CXTR3 and CXBR2. Thus the LLI size is extended to 8 fields. During the link, if all UXX bits are set to 1, the 8 registers of the channel X linked list register file are updated from the LLI present in memory. The CXLLR register of channels 12 to 15 supports two additional bits, UT3 and UB2 used to determine whether the CXTR3 and the CXBR2 registers will be updated during the link. In the example on the right, it is assumed that only the CXTR2, CXDAR and CXLLR registers will be updated when linking from LLI N to LLI N plus 1. Control bits related to registers that are not updated are cleared. These are UT1, UB1, USA, UT3 and UB2. Control bits related to registers that are updated are set to 1. These are UT2, UDA and ULL. This figure depicts the DMA channel execution and its registers programming in run 2 completion mode. In this mode, a full sequence of LLIs is processed by the DMA without software intervention. The first LLI may only perform a link as indicated by BNDT equal to 0. BNDT stands for block number of data bytes to transfer. Once the data transfer is completed, a link occurs when the LLR register is non-null. Then the next LLI is loaded and an iteration occurs. See the yes arrow between valid user setting test and executing once the data transfer from the register file. Initializing LLR with value 0 completes the channel transfer at the end of the currently active LLI. Note that the DMA controller parses the initialization performed by software and raises a flag called USEF in the case of a configuration error. The DMA controller raises a flag called DTEF when an error occurs during a data transfer and raises a flag called ULEF when an error occurs during a link. The TCF flag is set to 1 when the channel transfer completes successfully. This figure shows the overall and Unify GPDMA link list programming, whatever the execution mode, run to completion or link step. The software can reconfigure a channel when the channel is disabled and update the execution mode to change between run to completion mode and link step modes. When LSM equals 1, there is no automatic iteration. The channel transfer completes when the data transfer and link of the current LLI are performed. Software is in charge of reactivating the channel after a possible reconfiguration in order to handle the next LLI. In addition to this presentation, you can refer to other presentations on the GPDMA and LPDMA, DMA overview, DMA transfers hardware and software views, autonomous DMA and low power mode, DMA circular buffering and double buffering, DMA 2D addressing, DMA register file, DMA error reporting, DMA input-output LLI control.