 Hello and welcome to this presentation of the ARM Cortex-M33 Core, which is embedded in all products of the STM32-L5 microcontroller family. The Cortex-M33 Core is part of the ARM Cortex-M group of 32-bit RISC cores. It implements the ARM V8M mainline architecture and features a three-stage pipeline. In addition to scalar integer instructions, it also supports a single precision floating point unit and SIMD integer instructions used to improve the performance of DSP algorithms. The processor implements ARM trust zone technology using the ARM V8M security extension supporting secure and non-secure states. The Cortex-M33 has two AHB5 master ports enabling concurrent instruction and data transactions. Interrupts received from STM32-L5 peripherals are handled by the Nested Vector Interrupt Controller or NVIC. The memory protection is in charge of assigning security and privilege attributes as well as access permissions to instruction and data requests initiated by the core. This is based on a security attribution unit and two memory protection units, one per security level. Several debug units are implemented. Two protocols can be used to communicate between the serial wire or the debug port, named SWJDP and the external debug probe, either serial wire or JTAG. Invasive debug is performed by means of the breakpoint and watchpoint units. Invasive debug, the Cortex-M33 supports two real-time trace capabilities, the Embedded Trace Macro Cell or ETM and the Instrumentation Trace Macro Cell or ETM. Trace packets are output to the External Trace Port Analyzer through the Trace Port Interface Unit or TPIU. STM32-L5 microcontrollers integrate an ARM Cortex-M33 core in order to benefit from the powerful performance of its 32-bit processor architecture and particularly high level of deterministic processing. All Cortex-MCPUs have a 32-bit architecture. The Cortex-M33 was the first Cortex-MCPU released by ARM. Then ARM decided to distinguish two product lines, high performance and low power, while maintaining the compatibility between them. The Cortex-M33 belongs to the high performance product line. The Cortex-M33 processor is a low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications. The processor is based on the ARM V8M architecture and is primarily for use in environments where security is an important consideration. This slide highlights the differences between ARM Cortex-M4 and Cortex-M33. The V8M mainline is a superset of the V7M architecture. Trustzone is a new feature enabling the core to switch between two security states, secure and non-secure. The AHB buses used to communicate with the STM32-L5 bus matrix are compatible with the AHB-5 specification which supports the secure attribute. Trustzone is by default disabled in the STM32-L5 and in this case the Cortex-M33 offers the same kind of features as the Cortex-M4, some of them being enhanced. An interesting new capability is runtime stack overflow checking which is achieved by programming stack limit registers. Note that the PMS-AV8MPU present in the Cortex-M33 is not compatible with the PMS-AV7MPU present in the Cortex-M4. In terms of performance, the Cortex-M33 is better than the Cortex-M4 as indicated by the result of CoreMark and EMIPS benchmarks. The processor core implements a Harvard architecture supporting concurrent instruction fetch and data load store transactions. The instruction pipeline features three stages, a fetch stage, a decode and simple execute stage and a complex execute stage. Most arithmetic operations only take two clock cycles to execute. The Cortex-M33 has neither a cache nor internal RAM. Consequently, any instruction fetch transaction and data access is steered to the internal bus matrix. This bus matrix selects the output AHB5 Masterport according to the address. Two AHB transactions can be in progress at the same time. For instance, an instruction access from flash memory using the CAHB Masterport and SRAM access using the SAHB Masterport. The Cortex-M33's bus matrix is connected to the STM32L5 MCU's AHB5 multi-layer bus matrix enabling the CPU to access memories and peripherals. Since transactions are applied on AHB Lite, the best throughput is 32 bits of data or instructions per clock cycle with a minimum two clock cycle latency. One of the outputs of the Cortex-M33's bus matrix is the private peripheral bus or PPB which is internal to the CPU. It's used to access memory mapped registers present in the NVIC, SAU, NPU and debug units. Security Attribution and Memory Protection in the processor is provided by the Security Attribution Unit or SAU and the Optional Memory Protection Units or NPUs. The SAU is a programmable unit that determines the security of an address. The NPU is banked between secure and non-secure states. In the STM32L5, the SAU supports eight regions. Each region is defined by an address range and secure attribute either non-secure or secure non-secure callable. Any access that falls outside the programmed regions is marked as secure. For instructions, the attribute determines the allowable security state of the processor when the instruction is executed. It can also identify whether code at a secure address can be called from non-secure state. For data, the attribute determines whether a memory address can be accessed from non-secure state and also whether the external memory request is marked as secure or non-secure. If a data access is made from non-secure state to an address marked as secure, then a security fall exception is taken by the processor. If a data access is made from secure state to an address marked as non-secure, then the associated memory access is marked as non-secure. The NVIC and debug units are described in separate presentations. For more details, please refer to these application notes and the Cortex-M33 programming manual available on the www.st.com website. Also visit the ARM website where you will find more information about the Cortex-M33 core.