 Today, what we will do is you know go through some representative CMOS technology and you will recognize that all that we have studied so far is very relevant and it is in fact being implemented in you know state of the art CMOS technology. So, what I thought I will do is you know walk you through some representative nodes we will start with 180 nanometer generation CMOS technology and then progressively look at scaling look at 130 nanometer, 90, 65, 45, 32 you know each one being 0.7 x of the previous technology ok. So, let us then start with this what I will do here is essentially I will make use of these papers which are published in conference called IEDM which is an annual conference called International Electron Devices Meeting which is a premier conference in electron devices and any new device technology which gets developed gets reported in these conferences for the first time. So, what I have done is that I have taken a series of papers published in several past several years right. We will go through these papers one by one of course, we will not really read the entire paper, but I will highlight a few important things to draw your attention to some of the very important technological implementations. Let us look at this paper here now you know which is essentially you know high performance 180 nanometer generation logic technology and just to be consistent you know 180 nanometer technology and all subsequent technologies of course will be implemented by various companies right various foundries right. Just I have picked papers published from Intel just without any bias with to any company, but just to tell you a representative technology and also with respect to their technology Intel's technology we will see how the technology has progressed right. So, this is essentially a 180 nanometer generation logic technology. If you see here 180 nanometer generation logic technology has been developed with high performance 140 nanometer gate length transistor you see I had told you that the so called technology node, but the gate length of the transistor could be less than the technology node right. So, this technology node is 180 nanometer however the gate length of the transistor is actually 140 nanometer. It has 6 layers of aluminum interconnects right. The interconnect in this technology is still aluminum however later on you will see that they have migrated from aluminum to copper in terms of the interconnect and the dielectric between interconnects which is multi level metal interconnect. If you recall we had discussed this in our CMOS process flow between one metal level to the other metal level you have an insulator and that insulator is silicon oxide except that it is little bit variant of silicon oxide. It is fluorine doped silicon oxide the idea of doing doping it with fluorine is to reduce the dielectric constant of silicon oxide. That is why they say it is a low epsilon, epsilon is a dielectric constant because in the interconnects you want to minimize the parasitic capacitances parasitic resistances and hence you need to minimize the capacitances. This is opposite of high K gate dielectric these are low K gate dielectrics. So, you minimize the interconnect delay and interconnect capacitances. The transistors are optimized for a reduced 1.3 to 1.5 volt operation. You see the transistors operate at low voltage right at 1.5 volt maximum not beyond that right. The interconnects feature high aspect ratio metal lines and all that and using this technology they have demonstrated a 16 bit SRAM with certain you know memory cell size and this is sort of a demonstration of the technology right. What they are showing here is that not only they have developed the transistors, but they have put together the transistor to make a circuit and in this case the circuit is static random access memory which is a representative circuit. Eventually in this technology is a logic technology you see here logic technology not a memory technology. Logic technology will be used to build microprocessors which are very high end logic chips, but microprocessors on chip will have cache memory right. So, these SRAMs will be used for cache memories in the microprocessors these are not going to be stand alone SRAM chips to be sold. So, they have been able to demonstrate that SRAM circuit can also be implemented using this technology. So, let us then just go through some key highlights here and you know they give the introduction why do you need you know scaling and all that right that is very typical right. Now, let us come to the transistor right. So, the transistor is sort of illustrated in this figure right you have CMOS technology right you have N channel and P channel transistor right. Figure 1 illustrates the structure of the MOS transistor and isolation used in this technology. The isolation as you know is a shallow trench isolation correct not a low post isolation you have made a trench inside the silicon and that isolates the neighboring transistors. Start with the P minus P plus epitaxial silicon wafers followed by the formation of shallow trench isolation. N wells are formed with deep phosphorus and shallow arsenic implants they are not used in this particular case antimony and indium yet, but nonetheless they use phosphorus and arsenic combination for N well. While P wells are formed with boron implants that is how they are forming these wells. And then you know they also have the electrical gate oxide thickness is 3 nanometer gate oxide what they show here is a electrical thickness. When we talk of CV characterization subsequently from next class we will see what is the difference between physical thickness and electrical thickness. Electrical thickness is always little more than physical thickness. So, if they are saying 3 nanometer is their electrical thickness their physical thickness could be something like 2 nanometer less than 3 nanometer for sure. And they have ensured that this dielectric has realized sufficient reliability as you know they will demonstrate and the gate lengths have been patterned using deep UV lithography it is an optical lithography essentially shallow source drain extensions. Remember all that we talked about in terms of source drain engineering they have used solosuricion with the arsenic for NMOS boron for PMOS these are source drain extension for N channel and P channel transistors. Halo implants boron and arsenic are used in both cases for improved short channel characteristics low N plus P plus junction capacitance values you know that is fine side wall spaces are formed using CVD nitride. Remember the nitride spaces that we talked about that is in fact used to isolate deep source drain junction from your shallow extensions they make use of that. They use silicide titanium silicide remember the parasitic region that we talked about after the gating of the transistor there is a contact and in between there is a silicon and if you convert it into a silicide you get lower resistivity and in this technology they are using titanium silicide. So, that the typical on polish and source drain regions with a normal sheet resistance of 3 ohm per square that is the kind of sheet resistance that you can get which is a very low sheet resistance by the way. So hence this is how the cross section would look you see there is a N channel transistor in a P well there is a deep source drain there is a shallow extension there is a spacer which separates the two and there is a silicide here and similarly silicide will be on poly as well as on this junction and this is a PMOS transistor complementary metal oxide silicon technology. So, this is how you would define the transistor and then you will have to characterize a lot of things you will have to make sure that the isolation is sufficient for that you need to characterize the breakdown voltage of these that is between this and this. If you apply two voltage it should not break down you know the breakdown voltage should be more like you know 5 10 volt right. So, for all practical purposes these two are perfectly isolated. So, they are essentially demonstrating all these characteristics you know you can go back and go through these papers these papers are certainly available if you are an IEEE member or if your institute is subscribing IEEE journals you will certainly have this listed in the IEEE publication. Another important aspect that we had discussed all these reliability issues remember I said when you do the gate oxide reliability there is something called TDDB which is time dependent dielectric breakdown. Even though you are going to operate your transistor at very low electric field such as maybe in this case 6 mega volt per centimeter right you what you do is that you apply large electric field and characterize the breakdown times and based on that you sort of extrapolate it and say that in the real use condition certainly this will be reliable up to 10 years. They have done a similar thing what we have discussed right these are typical reliability characterizations. And here they show typical N channel and P channel characteristics this is drain current versus drain voltage the so called output characteristics which are well behaved going up to 1.5 volt for N MOS and minus 1.5 volt for P channel transistor of course your N current is more than the P current because of the electron mobility being higher than the hole mobility. This is sub threshold characteristics your threshold voltage is you know about 0.5 volt or so and below that this is a IDS in log scale and VGS in linear scale right it is a semi log plot really and this really is a sub threshold slope as we have already discussed. And again notice that depending on whether you have 0.05 volt here or 1.5 volt here you will have different characteristics that is essentially due to the Dible effect drain induced barrier lowering. If you have larger drain voltage for the same gate voltage you get larger current because your drain electric field will influence the injection at the source side especially in these nanometric dimension transistors. So, this is just to show that your poly silicon gate because of the solicitation has reasonably low resistivity right sheet resistance is of the order of 3 to 4 ohm per square which is fairly good. These are typical VT versus length plots remember what our discussion there is a reverse short channel effect I told you whenever you use a halo invariably you will have reverse short channel effect and then usual VT roll off that you will have you know in this region here right this region here VT is coming down. This is VT measured at 1.5 volt on the drain and this is VT measured at 0.05 volt on the drain and this difference is essentially your Dible right VT at low voltage on the drain is always higher than VT at high voltage on the drain right your Dible can be characterized based on that. So, they have NMOS and PMOS devices which have a sub threshold slope of 90 millivolt per decade remember 60 is the best you can get but you will never get 60 because you have 1 plus C D over C ox term which is always more than 1 right. So, because of that it will be more than 60. So, they have been able to achieve 90 millivolt per decade and their off currents are of the order of 3 nano ampere per micrometer we always specify off current in terms of ampere per width unit width depending on how many microns your transistor width is you multiply that you get the off state current and your on state currents saturation drive currents are 0.94 milli ampere for NMOS and 0.42 milli ampere for PMOS. So, in other words your on current you know to off current ratio is almost 10 power 6 it was if it were to be 10 power 6 then it would have been 3 milli ampere here but it is not 3 milli ampere it is close to 1 milli ampere correct which is reasonably good on current to off current ratio this is NMOS this is PMOS same story reverse short channel effect and typical V T roll off the V T's are negative again lower drain voltage higher drain voltage. Short channel threshold voltage roll off are shown in these figures right threshold voltages at 1.5 volt drain buyers are 0.3 volt for NMOS and minus 0.24 volt for PMOS and these results are of course better than any previously published bulk or SOI devices you know they are trying to say that you know they have been able to come up in much better devices. Subsequently they have also made use of these transistor and built what is called ring oscillator and from that they extract inverter gate delay if you were to build a simple inverter a not gate what is the gate propagation delay you have a input transition from low to high how long does it take for output to go from high to low that is your propagation delay and they have been able to get the propagation delay and typically you know it is very difficult to measure propagation delays of the order of you know these propagation delays that they have or of the order of few picoseconds so you do not construct just one single inverter because if you want to construct one single inverter you will have to measure the time resolution of the order of picoseconds what you do is that you cascade the inverters a large number of inverters are in series very interestingly if you have a odd number of inverters in series and connect the output of the last inverter back to the input of the first inverter create a feedback circuit that starts working as an oscillator that is why it is called a ring oscillator ring meaning you have created a inverter ring you need to have an odd number of inverter otherwise it will go if you have even number of inverter it will go to a steady state it put will also be steady output will also be steady but if you have odd number of inverter you can do this exercise yourself output will try to change the input and you know it will keep changing right it will become a oscillatory circuit so you do this oscillator you measure the oscillators time period and you know how many stages of inverters you have and you back calculate the delay per inverter and that is what is done typically and they do it for unloaded ring oscillator meaning there is no extra load on the oscillator the only load is the subsequent inverter stage operating at 1.3 and 1.5 at room temperature they have been able to get very low you know delays of the ring oscillators we will come to this in a minute but this is typically what is plotted gate delay as a function of gate length if you have a long transistor your delays are also more that is why we are scaling right I mean the reason why we scale is that the circuit starts operating faster as we have discussed in the very beginning as you start shrinking this gate length the gate length is decreasing here the delay is also decreasing and the nominal gate length for this technology is of the order of 150 nanometer and at 150 nanometer your gate delays are of the order of 10 picosecond again if you operate this at lower voltage your delay is little longer little more and if you apply higher voltage for this circuit not very high I mean if you apply very high voltage you will break down then you can decrease the delay a little further one good way of benchmarking the transistors is to really plot this so called DC performance metric what is DC performance metric this is a x y plot with on current on the x axis and off current on the y axis and requirement for a good transistor is that for any given off current whatever that off current is that let us say 10 nanometer off current I want to be furthest right of this curve if you have two technologies for example if I have a new technology which looks like this this is much better transistor because for the same leakage current it is giving you much much better on state current right on state current is much larger so your on to off current ratio is huge so that it will be less leaky it will not consume large static power at the same time it will be very fast right so it is essentially a 2 D plot of off current versus on current and you want to really create your transistor to really go along this you know towards the right and off course n MOS tends to be for the same leakage current to the right of P MOS simply because you have much better electron hole mobility compared to hole mobility. But what they are trying to do here is that the field simple they say this work and there are some previous works you know from references these are empty symbols so what they have plotted here is that these empty symbols are to the left of all these are P MOS transistors from previously published papers and all these empty symbols here are n MOS transistors from previously published papers and all they are trying to say is that compared to previously published P MOS devices these are much better because for the same off current your curve is to the right you get much higher on current and that is what you want to generate. The way you generate this curve by the way if you want to generate such a curve you cannot generate this curve with a one gate length transistor what you do is that you the using the same technology you print transistors of different gate lengths gate lengths from 130 nanometer 150 nanometer 200 nanometer 300 nanometer so on and so forth as your gate length is increasing your leakage current decreases your on current also decreases so all these points here you see correspond to shorter gate length because these are large on current and large off current all these points here correspond to a longer gate length P channel transistor and that is how you generate series of these points by characterizing transistors of different dimensions and you plot a universal curve which is a off current versus on current curve similarly for n channel transistors these are the transistors which have very high on current and off current which are coming from very short channel 130 nanometer kind of transistor whereas along this these are longer channel transistors and that is how this is generated and they do the interconnects you know interconnect is essentially aluminum in this case they are not yet used copper but the only thing that they have done different in interconnects is to use fluorinated silicon oxide as I mentioned earlier here you see fluorine is added to a silicon oxide to reduce dielectric constant and improve interconnect performance the use of SIOF as an interlevel dielectric reduces the dielectric constant to 3.55 compared to 4.1 for undoped silicon oxide remember silicon oxide the dielectric constant is around 4 4.1 right and whereas whereas that comes down to 3.55 you see thermal oxide if oxide is grown at let us say high temperature thousand degree centigrade then its dielectric constant is more like 3.9 that is what we used earlier when we were talking of gate dielectric 3.9 we round it off to 4 but here we say 4.1 because this oxide is not thermally grown it is a deposited oxide because you already have a metal line and top of metal line you have to put oxide so there is no silicon to grow oxide you will have to do a chemical vapor deposition of the oxide and invariably these oxides which are done at low temperature because you already have a metal tend to have little higher dielectric constant and hence the dielectric constant is of the order of 4.1 after fluorine doping it comes all the way down to 3.55. So they actually build SRAM cell this is the cross I mean not cross section the top u of the SRAM cell wherein you have 6 transistors this is a 6 transistor SRAM cell this is the interconnect stack you know starting from the transistor at the very bottom these are the contacts metal 1, via 1, metal 2, via 2, metal 3, via 4, metal 4 and so on and so forth going up to 6 levels of metals in this case. And you know using all this they have been able to show a working SRAM and you know this is what they are sort of summarizing 180 nanometer generation logic technology has been developed and demonstrated with high performance reduced power transistors aluminum interconnects with low epsilon silicon oxide with fluorine doping dielectrics are used to meet interconnect density and performance requirement the technology yield and performance capabilities have been demonstrated on a 16 megabit SRAM which operates at greater than 900 megahertz frequency. So eventually if you have to build a microprocessor if the cache has to respond at that frequency it would respond at that frequency. So they have been able to start from the basic semiconductor processes using all the process integration know build the transistors demonstrate a simple circuit like ring oscillator characterize the gate delay and take it forward to make an SRAM cell and show that the SRAM is working. So this is really a demonstration of a technology but still this technology is still not after this it may take another year for you to make a real product because your real product is going to be microprocessor subsequently. Then you will have to make a microprocessor make sure that the yield is good right and you know that requires lot of optimization. So let us now look at the subsequent technology which is you know the 130 nanometer generation logic again logic technology right because Intel does not make standalone memories right the only product they offer and that is their essentially lifeline is microprocessors very high end microprocessors right and hence this is the logic technology not a memory technology again. Now 70 nanometer transistors although it is a 130 nanometer technology you see the gate length is 70 nanometer they have dual VT transistors remember something that we discussed there is a leakage power problem you need to really make sure that you minimize the leakage power at the same time you need high performance. So what do you do it turns out there only is few critical parts in any complicated chip it is important to make the transistors in the critical part very fast transistors and hence make only those transistors low VT transistors and others could be high VT transistors right. So as a result of that you get very fast chip as well as low power consuming chip. So in other words here you have two flavors of N channel transistors and two flavors of P channel transistors one is called a low VT transistor and other one is called a high VT transistor and hence it is a dual VT transistor technology and what else six layers copper interconnects a big departure from aluminum to copper because this is the only way to scale the interconnects very briefly may be we will look at the issues in interconnect scaling well let us get started you know what they have here. A leading edge 130 nanometer generation logic technology with six layers of dual damasin copper interconnects dual damasin is a particular process sequence which is used to realize copper interconnects right we will not really go over the details of that process sequence dual VT transistors are employed with 1.5 nanometer thick gate oxide the gate oxide thickness has gone down compared to what it was in the previous generation operating at 1.3 volt previously it was 1.5 maximum now it is 1.3 you see high VT transistors have drive currents of 1 milli ampere and 0.5 milli ampere per micron for NMOS and PMOS while low VT transistors have 1.17 for NMOS and 0.6 for PMOS respectively so two flavors of transistors again they have been able to make an SRAM cell demonstrated SRAM cell demonstrated the technology on a 18 bit SRAM. The you know typical process flow is the same thing except that you have a two dual VT meaning you will have to create two different N wells two different P wells. So, that doping concentration is little different in two N wells and little different in two P wells and that is how you get dual VT technology for N and P which means more photolithography step little more complex technology but that is worth it only if you do that you would be able to get the best of it. So, various technological features this is how a transistor looks N channel transmission electron micro graph of showing a 70 nanometer gate length source drain ultra thin gate electrode you know polysilicon silicide at the top and so on and so forth or else will remain identical you will use halo you will use shallow extension you know except that you may change the dose because the transistor gate length is going down especially halo dose you may want to manipulate. Shallow source drain extension regions are formed with arsenic for NMOS boron for PMOS boron and arsenic halos are used this will remain same silicon nitride is used for the spacer correct followed by the silicide here is cobalt silicide as opposed to titanium silicide cobalt silicide gives you much better lower resistance compared to titanium silicide. Again the demonstrator well behaved NMOS and PMOS right is the story looks similar right you know you will see similar graphs here except that now you have a high VT and low VT two flavors and sub threshold plot drain current in a log scale versus gate voltage for low drain voltage and high drain voltage. And the Dible for the 70 nanometer NMOS device is measured to be 100 millivolt per volt that is how we specify the Dible right what is the difference in VT per unit voltage on the drain unit voltage change on the drain and that is how they are characterizing the Dible. And this is again the typical off current versus on current right and they are sort of saying that you know this again two flavors unfilled and filled high VT and low VT there are two flavors of PMOS and two flavors of N channel transistors. These are some important matrix such as VDD gate length oxide thickness you know they are comparing 180 nanometer generation which is the previous paper that we discussed and this generation supply voltage from 1.5 to 1.3 gate length from 130 to 70 oxide thickness from 2 nanometer to 1.5 nanometer and so on and so forth. You see off current has increased a little bit from 3 to 10 nano ampere per micron. Typical threshold voltage roll off threshold voltage versus gate length N channel P channel N channel positive and P channel negative VT low drain voltage high drain voltage this is because of Dible. This is now high VT and this is the low VT transistor. So, again they characterize delay the ring oscillator. Now, they have depicted in slightly different fashion in the previous paper you saw delay plotted against gate length here delay is plotted against off state current of a transistor. Remember off state current is inversely related to gate length. In other words if you had to plot gate length here this would have been a lower gate length may be 100 nanometer here may be 200 nanometer here may be 500 nanometer here. 500 nanometer will also have I am sorry I got it the other way around. This would be 100 nanometer this would be let me see if I can delete this let me just take it away that is. So, this needs to be sort of reverse right 100 nanometer is out here 100 nanometer also results in large leakage current longer channel length also results in small leakage current correct I mean let me write it here. So, that becomes very clear. So, this is 100 nanometer transistor let us say 100 or 100 70 nanometer in this case right they have gone down to 70 nanometer right. So, this would be something like 70 nanometer out here and this may be 100 nanometer and this may be 200 nanometer. So, the gate length is the lowest here and the lowest gate length gives the lowest delay and when the gate length is increasing the leakage current also decreases as is evident here lower leakage current because you have larger gate length the current on current will also be lower just as off current is decreasing on current is also decreasing and hence you will get larger delays correct. It is essentially you know looking at this delay versus gate length or delay versus leakage current you know one and the same essentially. So, the peak performance is increasingly limited by the R C delay of the interconnect now why is that let us look at what is happening with scaling right. What have we done over scaling you know we have started from let us say technology of the order of 250 nanometer quarter micron technology 180 nanometer 130 right 90 65 45 and so on and so forth right. And let us look at what happens to delay we know that as I scale transistor transistor becomes very efficient in other words if we are talking of gate delay or inverter delay over the technology generation inverter delay or gate delay has been decreasing and that is why in the first place we want to scale you build any gate it could be a not gate and gate or what have you right. So, so called gate delay decreases gate delay decreases because remember gate delay depends on transistors and transistors with scaling become efficient smaller transistors are always better and the so called C V over I metric become better as I start scaling down the transistor. What is the story with interconnects interconnects it turns out the story is completely opposite unfortunately what is an interconnect you know interconnect is a metal line let us say this is metal 2 and there may be another neighbouring metal 2 line here this is another line running at the same level. And let us say there is another metal 1 underneath M 1 between these 2 you have inter level dielectric 2 metal levels between that you have a dielectric that is how you have insulated connect this is metal 1 what is scaling of interconnects scaling of interconnects is scaling the dimensions of the just as scaling of the transistor transistor dimension has to come down and transistor distance has to come down and same here with the interconnect right the interconnect the dimension has to come down what is the dimension you see this is the so called line width we call it line width we print the metal line metal line is a long metal line how long it is it depends on where is this metal going from inner chip from one location to the other location inner chip this is the thickness let us say t and this is length. Let us normalize the length unfortunately the chips are not becoming small the chips are really becoming bigger and bigger you would have thought that with scaling because you are trying to bring down the number of transistor the chip should become smaller right that is why we said 0.7 x so that the chip area comes down transistor area comes down and all that. But what has happened over the years is that with scaling we also put in more transistors in a new technology we are not just happy with the performance gain that comes just because of the mere scaling we want to increase the number of transistor very significantly compared to what it was earlier. So, if previously you had million transistor you want to put 4 million transistor in a new chip in a new technology and hence you continue to use the same area or even bigger area. So, in other words if you are looking at a chip the chip size from one technology to the other technology really does not scale if anything it is becoming bigger the chips are becoming bigger. What is interconnect? Interconnect is essentially a metal line which takes the signal from one location to the other location inner chip you see. So, the message here is that the length wise it is not really helping us you know it is really becoming as big. So, let us look at normalized length what happens with interconnect scaling what happens to what is interconnect delay? Interconnect delay depends on R and C of the interconnect this is the RC delay due to interconnects. Scaling I need to scale the width I need to scale T if I go from this technology to a new technology of metal interconnect in that the thickness has come down the width has come down what is the implication resistance goes up because your cross section area for conduction is going down. So, per unit length you see if you have to look at ask the question what is resistance per unit length? What is L rho L by A let us say I am interested in R per L it is rho by A how is A scaling? A has T and W as a result your interconnect resistance per unit length goes up as K square which is not a good thing this is not the end of the story. So, the message is that interconnect lines are becoming more resistive with scaling not the end of the story there is even more serious problem and what is that serious problem? You would have thought that at least because I am making the interconnect smaller the capacitance should go down because capacitance should be due to let us say this metal line and another metal line there is a coupling capacitance and the area for that coupling is T I mean this you know that is determined by this width that is coming down and hence it should go down. Yes, this the so called parallel plate capacitance or inter metal capacitance indeed goes down, but there is a more serious issue and what is that? I am also decreasing the distance between the two metal lines in the new generation of the technology. So, the new generation of the technology has M 2 lines which were far apart have been brought very close to each other. So, there is a new capacitive component which is intralayer capacitance earlier this distance was very large you could have ignored that capacitance. Now, this is increasing very dramatically. So, net result is that with scaling your R is increasing your C is also increasing as far as interconnects are concerned. C is increasing very dramatically because these interconnects lines are coming close to each other and hence the R C delay of the interconnects is increasing. So, if you were to look at interconnects in older generation technology 250 nanometer and beyond interconnects were after thought you never bothered about interconnects. They are ideal metal lines take signal from one location to other location they do not contribute any further delay. So, it was non existent compared to gate delay your interconnect delay was very very low, but what has happened in the recent past is something like this. Your gate delays are increasing your interconnect delays are increasing and hence interconnects are becoming bottlenecks. It is like you know just imagine your road network in the city you have the fastest driving car and that is transistor for you that is a gate for you, but you know you have a very bad road network. Then you are limited not by the speed of the car, but you are limited how fast the roads will allow you to travel right. And these are the roads interconnects are the road that allows you to take signals from one location to other location and that has become a serious problem. And hence you see that in this technology there are lot of things that are being done to minimize R and to minimize C. In previous paper we saw fluorine was doped to minimize capacitance. And today I mean in this technology we see aluminum is replaced with copper because copper has lower resistance compared to aluminum R C delay becomes much better and that is exactly what is done here. And they have optimized this fluorinated oxide and that gives a K of about 3.6 and this is again hierarchy of interconnects and they have used this to build what they are showing here is that if they are used aluminum you see with decreasing pitch, decreasing pitch is two metals are coming closer to each other. Your delays are increasing if you had used aluminum it would have gone up like this because you use copper you could decrease it. At the same pitch copper technology gives much lower delay compared to aluminum technology and that is what they have done. And they have been able to make an SRAM and demonstrate that you know 18 bit SRAM is operating now at what 1.6 megahertz much higher frequency right. So, actually it is not very clear here you know I take back what I said I mean the previous one was a lower density SRAM was at 900 megahertz, but this is a higher density SRAM you know that is operating at little lower frequency you know as you start increasing the density there is also an impact on the you know speed of the SRAM that you can build. Whereas, the ring oscillators obviously are much more efficient compared to the basic technology is much better previous generation was 10 picosecond 10 to 13 picosecond now it is a 7 picosecond right. So, you know you can clearly see a better technology and if you go down to 19 nanometer now what has happened now 7 layers 6 layers have become 7 layers of copper 19 nanometer has a 15 nanometer gate line transistors from 70 it came down to 15 nanometer now. It has it is using a strain silicon channel we have not discussed about strain silicon channel, but very soon down the line you will start discussing you know strain silicon also. So, we will postpone the discussion for the time being this uses 1.2 nanometer oxide it is even thinner than previous generation and nickel silicide instead of cobalt silicide it is nickel silicide now there is a you know some more optimization and. So, this is a cross section of a transistor channel is strain silicon 1.2 nanometer gate oxide 15 nanometer gate length nickel silicide is shown here at the source drain and at the polysilicon and they have been able to make a 60 SRAM cell using the technology right this here just shows that you have silicon and 1.2 nanometer oxide and you know polysilicon gate and typical of current versus on current for n and p channel transistors. And they are just showing here you know as a function of here different technology nodes we already looked at 180 nanometer technology 130 nanometer in 180 nanometer you had the 100 nanometer, 130 nanometer, 70 nanometer gate length, 19 nanometer, 15 nanometer gate length this is what I said now we have a departure in terms of what gate length you print is actually smaller than the so called technology definition 90 nanometer, but in the past they were exactly identical we have had the discussion on this in the one of the earlier lectures. Why nickel silicide because with scaling cobalt silicide will start increasing the resistance whereas, nickel silicide gives very low resistance and that is why they have gone to nickel silicide. Again multi level metal interconnects now instead of fluorine doped oxide they have done carbon doped oxide you know again new improvement you know that is how you need new newer and newer materials k has come down to 2.9 instead of 3.5 again to decrease the R C delay of your metal interconnects. And they again show that with carbon doped oxide you can get significantly lower R C delay as you start decreasing the pitch as compared to aluminum oxide with fluorine doped oxide aluminum with fluorine doped oxide copper with fluorine doped oxide and this is copper with carbon doped oxide which is much better. And they have been able to do an SRAM here and this SRAM operates at you know 2 gigahertz which is much higher frequency. I suspect that you know the previous paper that probably should have been 1.6 gigahertz that could be a typo there you know rather than 1.6 megahertz you know that is more like it because on 180 nanometer you had a you know 900 megahertz very close to gigahertz right and you know then you have 1.6 gigahertz and now you have about 2 gigahertz or little more than 2 gigahertz. So, this is about 19 nanometer and if you come to 65 nanometer all that has happened really is gate length has scaled on further 35 nanometer 8 levels of copper interconnects interconnect hierarchy is also becoming more complex and SRAM cell is also shrinking continue to use nickel silicide. And let us see if there is anything that I want to highlight here. So, this is a typical trend right. So, on a 65 nanometer technology the gate lengths are 35 nanometer this is a typical cross section of a transistor n and p channel transistor ID, VDS characteristics and sub threshold characteristics this is off current versus on current typical DC performance metric. And this is the same for p MOS transistor this is a very nice cross section showing different levels of metal interconnects. And they have made an SRAM this is a 70 megabit SRAM test vehicle and they have been able to you know a show that this SRAM operates at frequencies close to 2 gigahertz right and that they have been able to demonstrate right no major departures. Then at 45 nanometer you see very significant departures and what is that for the first time you see high k gate dielectrics along with metal gate here high k metal gate for the first time. For define nanometer logic technology and transistors feature 1 nanometer EOT that is equivalent oxide thickness, but they actually use a hafnium oxide gate dielectric which is thicker than 1 nanometer. They use a high k gate dielectric dual band edge work function metal gates 2 different metals 1 for n channel 1 for p channel transistors. So, what they have been able to show here is the following you see this is gate leakage here and this is oxide thickness EOT when you use S I O 2 EOT and S I O 2 are 1 and the same you see from previous this is a 45 nanometer generation at 65 nanometer generation they were not able to scale the gate oxide thickness. Because the leakage current as we started decreasing the gate oxide thickness leakage current suddenly started increasing because of direct tunneling current because from 19 nanometer to 65 nanometer they did not have a mature high k gate dielectric technology they could not scale the oxide thickness. They kept the oxide thickness as is and then the leakage current kept was you know kept at the same same level. Now with the high k technology the EOT came down, but the leakage did not increase the leakage also came down because it is a EOT of 1 nanometer, but indeed it is a thicker physical oxide direct tunneling is suppressed and hence you got the best of the world. You got lower EOT and lower leakage current that is why you want to use high k gate dielectric that is illustrated very nicely here showing the trends in different technologies. So, this is a high k and metal gate is different for NMOS and PMOS. So, what is the typical process flow they do STI shallow trench isolation wells and adjust the VTs the deposit high k gate dielectric using atomic layer deposition ALD is atomic layer deposition of that dielectric. They do a disposable gate metal gate remember the discussion that we had. So, poly silicon is done as usual gate patterning source drain extension spacers everything is done source drain formation nickel solicitation and then you deposit an insulator then poly opening you H back the poly poly is removed that is what we mean by disposable metal gate poly was sitting there as a place holder. So, that you get self aligned transistors then you do one metal for PMOS transistor which has a work function appropriate with P channel transistor do patterning of the gate and then again do a NMOS work function metal deposition you need two metals for defining two different kinds of transistor and you know you complete the transistors and then of course you do the multilevel metal interconnects. So, this is again to show that with high k your gate leakage has come down very dramatically if you had used the silicon oxide or even so called nitrided silicon oxide you would have had a very high leakage current, but now that is not the case this is the typical v t versus gate length threshold voltage roll off that we have seen measured at low drain voltage and high drain voltage that is for N channel and this is for P channel transistors typical off current versus on current plots right this looks similar everything looks similar and now typical delay versus off current remember this is how it looks when you have very large off current it means the smallest length transistor has the highest leakage current and hence because you have built the inverter using the smallest length transistor you have the best delay that you can get and the delays are now of the order of you know very low delays of 5 picoseconds or even less than 5 picoseconds reliability of the transistors again they have characterized T d d b by accelerated testing you know extrapolation right just to show that these high k gate dielectrics are as reliable as silicon oxide then they have actually made not only SRAM in this case they have actually made a microprocessor they have made a single core microprocessor and dual core microprocessors and been able to show that you know you can actually get a fairly good circuit working with all these new technologies high k metal gate and so on and so forth right and that is what happened in 45 nanometer technology and in 32 nanometer technology you know the high k and metal gate continued right it continues to be high k and metal gate transistors right we have stuck to that right now going forward will continue to use high k and metal gate but it is called second generation of high k and they have tried to do some optimization improve the hafnium oxide performance improve the metal gate performance and so on and so forth right so 32 nanometer the actual gate length is you know much lower than little lower than not much lower than little lower than 32 nanometer you know it is just showing that previous generation technology and this is a 32 nanometer technology and off current versus on current the typical plots that we have seen all these are off current versus on current plots right trying to indicate that they have been able to optimize these transistor for a given off current they have been able to get as large on current as possible typical output characteristics IDS versus VDS notice that the difference between N and P has come down if you recall 118 nanometer technology your P channel current was almost 50 percent of the N channel current now using the so-called strain engineering which as I said will be discussed in one of the future classes we are able to enhance both electron and whole mobility is and so much so that the whole mobility can approach very close to electron mobility and that is why you do not see a huge difference between electron and whole mobility and electron and whole current N channel and P channel current the difference has come down this is a typical sub threshold plot that you would see and typical V T versus length plot V T is decreasing with decreasing channel length right. So, all these is consistent with what we have been discussing and they have again made an SRAM and they demonstrate that you know SRAM works fairly well with this 32 nanometer technology right. So, what we have been able to do in this lecture is really to look at representative CMOS logic technology not memory technology these technologies are not for DRAM fabrication not for flash memory fabrication not for even SRAM fabrication but to make a very high performance microprocessors. So, there performance is the key you want to make the transistor which gives the lowest delay and various techniques we have seen right all the source drain engineering channel engineering is consistently used in all these transistors and as we have continued to scale the technologies we have transition from silicon oxide to high k gate dielectrics to metal gates and so on and so forth. Similarly, in the interconnect arena we have gone from aluminum and conventional silicon oxide to doped silicon oxide copper and thereby minimize the R C delay of the interconnects very significant right. So, hopefully now you know you should be able to read up any CMOS technology paper and be able to understand that you know based on all the discussion that we have had so far right. So, we will stop this lecture today and starting from next lecture we will actually start looking at electrical characterization that is C V characterization and I V characterization.