 Hello, and welcome to this presentation of the STM32 Octo-SPI interface that will present the features of this interface which is widely used to connect external memories to the microcontroller. The Octo-SPI interface integrated inside STM32 products provides a communication interface allowing the microcontroller to communicate with external single dual quad or octal SPI memories. This interface is fully configurable allowing easy connection of any existing serial memories available today on the market. The external device is memory mapped which allows any system master to access it like any other memory of the system for read and write operations. Applications will benefit from the easy connection of serial external memory with only a few pins required. Thanks to the memory mapping feature, external memory could be simply accommodated in the existing project when more memory is needed whether it be flash or RAM. The Octo-SPI interface offers high flexibility for frame format configuration to address any serial flash from single data lane up to eight data lines. As with regular quad SPI, the user can enable or disable each of the phases, configure the length of each phase, and configure the number of lines used for each phase from one to eight. A new signal RWDS acts as either a write strobe during write operations or a read qualifier during read operations. The Octo-SPI supports the new hyperbus mode which combines the command and the addresses in a single initial phase. As with the regular frame format, hyperbus mode also uses a read qualifier and a write strobe during the data operation. The Octo-SPI supports variable or fixed external memory latency as defined by the hyperbus protocol specification. The Octo-SPI integrated inside STM32 products offers three operating modes which will be explained later in this presentation. Communication with external memory supports single or dual data rate operation. The Octo-SPI supports three different modes of operation. Indirect mode where it behaves as a classical SPI interface and all operations are performed through registers. Status polling mode where the flash status registers are read periodically with interrupt generation or memory mapped mode where external memory is seen as if it is internal memory for read operations. In indirect operating mode the Octo-SPI behaves like a classical SPI interface. Transferred data goes through the data register via FIFO. Data exchange is driven by software or by the DMA using related interrupt flags in the Octo-SPI status registers. Each command is launched by the writing of an instruction, address or data depending on the instruction context. A specific mode has been implemented in the Octo-SPI interface to autonomously pull status registers in the external flash. The Octo-SPI interface can be configured to periodically read a register in the external flash. The return data can be masked to select the bits to be evaluated. The selected bits are compared with their required values stored in the match register. The result of the comparison can be treated in two ways. In ended mode if all the selected bits are matching an interrupt is generated. In ORD mode if one of the selected bits is matching an interrupt is generated. When a match occurs the Octo-SPI interface can stop automatically. The Octo-SPI also provides a memory mapped mode. The main application benefit introduced by this mode is the simple integration of an external memory extension with no difference between read or write accesses of internal or externally connected memory except the number of wait states. This mode is suitable for both read and write operations and external memories whether it be RAM or flash they are seen as internal memory with wait states included to compensate for lower speed of external memory. The maximum size supported by this mode is limited to 256 megabytes per instance. A prefetch buffer supports the local execution therefore the code could be executed directly from the external memory without the need to download it into the internal RAM. This mode also supports SIOO mode which is supported by some flash memories which allows the controller to send instructions only once and remove the instruction phase for the following accesses. The Octo-SPI has five interrupt sources timeout status match when the masked receive data matches the corresponding bits in the match register in automatic polling mode, FIFO threshold, transfer complete and transfer error. DMA requests can be generated in indirect mode when the FIFO threshold has been reached. The Octo-SPI is active in run, sleep, low power run and low power sleep mode. An Octo-SPI interrupt can cause the device to exit sleep or low power sleep mode. In stop one or stop two modes the Octo-SPI is frozen and its registers content is maintained. In standby or shutdown mode the Octo-SPI is powered down and it must be reinitialized afterward. The Octo-SPI is a specialized communication interface targeting single, dual, quad and octal communication. Most of the external serial memories are supported. In multiplexed mode the same bus can be shared between two external Octo-SPI memories. Be aware that the chip select or CS of the Octo-SPI-2 required for the multiplexed mode is not available for all packages. Multiplexed mode is a major feature supported. This mode enables the communication with two external memories sharing a single STM32 H7A3 and B3 Octo-SPI bus port one on the right hand picture simplifying PCB footprint and design. Note that the two memories do not need to follow the same protocol. For example, one memory can work in hyper bus mode and the second one in standard octal bus mode. To enable such configuration only an extra chip select pin is needed to select the second memory on the bus. This also allows the release of the unused port pins for other functions. In this mode an internal hardware arbiter located in the IO manager block, the white block in the picture, selects alternatively the octo-SPI-1 or octo-SPI-2 depending on their transfer requests. This arbiter embeds time counters to limit the maximum transaction duration for each octo-SPI. This tuning of the sharing of the octal-SPI bus bandwidth avoids the starvation of one of the octo-SPI ports. Once the initial setup of the time counters is done the arbiter operation does not require any software management. Wearable applications require low power management together with high quality HMI. This can be achieved using the STM32 H7 octo-SPI interface to store in an external flash all the graphical content needed like background images, high resolution icons or fonts to support multiple languages. Additional audio data for ring tone can also benefit from the large space offered by the external flash. The low pin count needed to drive such devices allows a very optimized system integration. You can refer to peripheral training slides related to RCC, interrupts, DMA and GPIO for additional information. For more details please have a look into the application notes AN5050 about the octal-SPI interface.