 So, welcome to this lecture on VHDL in the course digital system design with PLDs and FPGAs. Last class we have looked at the we have completed the delay modeling and we have started some examples. So, that we apply what we have learnt and we could not complete that part. So, I am planning to complete it not only designing something but you know give a code and kind of work out what is the possible circuit which it implements or given to a synthesis tool what it synthesize. So that you get experience you know back and forth given a circuit how to code it for synthesis or given a code how to kind of make out what is implemented it is very useful when you really work in a design team you may have to work with something which is designed earlier and most of the time it is done like that you know you have you are in a team you join a team there is something going on and you will be given some responsibility many a times you will end up with some very log of VHDL code and you have to activate modify it debug it and rarely there will be enough documentation. So, to know looking at the code what is underlying hardware it represent is a very useful thing to do that is what we are going to do today. In addition to even designing some circuit so let us quickly run through what we have done last class and so that we can continue kind of smoothly from there and let us move on. So this is what we have seen the kind of an example program to illustrate the various delay model. So, we have created a signal A it is a kind of empty entity because we just wanted to see the waveforms and we are using instead of port we are using everything as signal. We form a signal A with some pulses and that is what is shown here and X is A after 5 nanoseconds so it has a pulse would minimum pulse would 5 nanosecond propagation delay 5 nanosecond and so you apply you get a delayed version of this with all the pulses less than 5 removed. Next is reject 3 nanosecond inertial A after 5 nanosecond where in it is exactly same but everything below 3 is kind of rejected so you get this and this is a transport delay with a 5 nanosecond delay. So you get Z as a delayed version of A that is what is shown here and we also have looked at how to write a VHDL code to not only to synthesize but to verify some timing condition on its input okay. It is quite useful because sometime you may have to like you have some timing violation happening in the simulation and suppose it is random and you want to catch it and you can do like that do this way though the timing analysis will show up but definitely this is another way static timing analysis can report the whole time violation the slack and all that but yet this is a practice and a useful thing we are doing. So our aim is to write a code which checks the setup and whole time violation of the D with respect to the clock. So basic idea is to keep track of the event this particular positive edge of the clock and any event on the D the idea is that when there is a positive edge of the clock subtract the last event on D make sure that it is greater than setup time. Similarly whenever D changes subtract the last event on the clock then you know make sure that it is greater than the whole. So we have the entity here we define a two constant setup time and whole time to be conveniently kept in one place so that you can modify it in one shot and we have a process with both D and the clock and sensitivity list which is required because we have to catch the event on D and this is the behavioral code and this is the main code which checks for the whole time violation if there is an event on D make sure assert is asserting the true condition that the time of the event minus the clock event is greater than the whole time and update that time and if there is a positive clock edge assert that the time between that time and the last event on D is greater than or equal to setup time and update the clock time and that is how it is done and as I said that the 0 nanosecond we do not want it to report an error. So we make sure that that is avoided by this statement and we have seen the syntax of assert a true or expected condition and then if it is violated report a message and you can specify what should the tool do by this level for not warning it is just printed on the console and for error and failure it just terminates the simulation process. So that is the syntax of assert and then we started with examples we have seen the VHDL code for a demultiplexer the most proper code is this when you have S is a select line y is a input a, b, c, d are the output when it is 0, 0, y goes to a rest all are 0, 0, 1, b goes, y goes to b then so on you know c, d. So we have this is ideal kind of coding for the most proper coding for the demultiplexer because there is no priority and for all the select line values we are specifying the output and all the outputs are function of the same as and y so it is nice to combine this way. But there are many other ways to do it and we have seen you can write equation for a, b, c and d in terms of the input and the select line. So this is a0 is y0 node of S1 and node of S0 and when it comes to d it will be d0 gets y0 and S1 and S0 because it is 1, 1 and since it is a 1 to 4 4 bit demultiplexer you have to write the equation for all the 4 bits. And now looking at this equation you know seeing this symmetry you can make out that this can be easily put it in a generate loop with index going from 0 to 3 for this and this is fixed anyway similarly for this and so on. So we can combine everything into generate loop like for i in 0 to 3 generate a of i is y of i and that means you just take the first statement put i here, i here similarly take this i here, i here and so on then you get this and please remember that this is not a loop in a conventional sense that like in a sequential language you go you know kind of execute one and execute the other. It is just a concise way of writing this like this you know this is literally replicated 4 times and you get all the big equations. So it is a shorthand you have to write with select for each output A, B, C and D. This is quite right because no problem because even in the hardware A output can be separated from the circuit for the A can be separated from the B. Absolutely no issue if you write like that you get the circuit you want but the synthesis tool has to infer now they are saying that A, B, C, D is part of a single high level block called demultiplexer. I mean that is only trouble with this code for these simple things the tools will do but you have to be careful. Similarly you have the when else you have 4 of them A gets Y when I say 00, L 00 because we only talk about A output similarly B, C and D. Another version of the case we do not say 00 everywhere we make it at the beginning then only change is indicated here then instead of case you can use if there is like you know that if as a priority definitely as it is written you say S is 00 then S is 01 that means not of 00 but since we are enumerating all possible values of S and when you say and you know S is not of 01 and 01 then everything reduces to same as case. So it is not a problem this syntax does not give a problem but still the most elegant code will be to use the case and as in case you can initialize all the values at the beginning and you know represent only the change here you could use another way is using any for each of the outputs separate like you say if S is 00 then A gets Y else A gets 00 and if it is exactly like writing the width select or when else once again it is technically correct but the ideal code would be to combine everything all the outputs together as a function of A and Y. Another version is you know everything is initialized at the beginning and only the change is indicated here and this is what we have maybe stopped at the last lecture we have we are writing an 8 bit ripple adder okay for the figure only shows a 4 bit ripple adder to save space but the idea is same you know you have the cascaded full adders full adders take A B inputs A carry input and it produce a sum and a carry out and the carry out goes to the next carry in of the next full adder and so on okay. And the issue with this ripple adder is that if you take the C4 or sum 3 it uses C3 and when you say you take the case of sum 3 in the worst case it propagates from C0 to C1 C1 to C2 C2 to C3 and C3 to S3. So, there are if you assume two levels of circuit in each of and or then you have eight gate delays by the time you come here and you can imagine if you go to the S7 you will have the 16 gate delay and that adds a lot of delay okay. So, there are circuits ripple adders which or sorry the adders which gives less delay and so this is simple you have the sum equation sum of i is ai x or bi x or carry i carry i plus 1 is ai and bi or ai or bi and carry i which when you expand you get ab ac and bc C being the carry and to make the code need we have a C in which is C0 and C out which is say in our case C8. So, to make the code clean not write everything in a single loop and not write anything outside we have defined a carry which is 9 bit and we assign the carry 0 as C in and the carry out as sorry C out as carry 8 otherwise we will end up writing you know one assignment 1 repetition for with C in for the kind of sum 0 and the carry 1 then the last one with the carry you know C out and all that that is avoided by this game. Now also I mentioned is very unusual like all the many times when you read the textbook you will design lot of combinational circuit which is all designed with a truth table when it comes to the adder somehow surprisingly you kind of quickly make a full adder then cascade it. But that is I mean if you go by the principles of what you have learnt if you want an 8 bit adder then you make a truth table for you know a and b which are 8 bit so it will be 16 bit 64 k truth table yeah one definitely we cannot work it on the paper then you implement a circuit which essentially should give you an and or circuit which is 2 level or 4 level or whatever depending on all the complexity. So, actually if you do that what you get is a carry look at adder and since that is complex one should you know go for a modular approach at least in the case of the adders it is possible because of this structure you add something then you have a carry which is going to the next level and the next level you do the same thing. So, because of the modularity because of the symmetry it is possible to design a kind of modular ripple adder modular adder it may not be possible in every case things can be not very symmetric symmetric or regular. So, many times it is not amenable to such scheme but this at least is amenable to that so we do this ok. So, that is a basic game now. So, as I said now the as you are taught the kind of carry look at adder is derived from here not an issue but the basic game is that in a carry look ahead adder is that when it comes to this stage instead of using something already defined this stage will work with B1, A1, B0, A0, Z0 to generate both S1 and C2 that is a basic game ok or when you come to the stage 3rd stage instead of just using B2, A2, S2 and already formed C2 we will build we will use B1, A1, B0, A0, Z0, C1 everything I mean to generate so that in one shot it is generated not rippling through the stages that is a game. So, let us quickly maybe that gives a kind of revision and some practice in coding that is what you know shown here. So, this is the adder equation S of I is A of I, X or B of I, X or C of I no confusion whether be it ripple adder or carry look ahead adder the thing is changed the game is not there is nothing complex with complicated with that the problem is here so we attack that. So, C of I plus 1 is AI, BI or AI or BI and CI and this is now for clarity this is called generate G AI, BI because if both are 1, 1 you know that the sum is 0 and there is a carry out definitely there is a carry out ok irrespective of the carry input to that stage is 0 or 1 both are 1, 1 the sum is 0 carry out is 1 if the carry input is 0 no change if the carry input is 1 sum will become 1 the carry out is 1. So, absolutely no change so that is called generate the carry is generated at this stage but if any one of them is 1 AI or BI is 1 then the carry is generated if input carry is 1 ok. So, C1 is 1 if A0 or B0 either of them are 1 and C0 is 1 no that is a game. So, we call that is propagate that means if AI or BI the carry before I know the carry input is propagated to the carry output. So, we define two things GI which is AI, BI AI or BI now the game is very simple like you say you take this C2 is nothing but A1, B1 or A1 or B1 and C1. Now usually the C1 comes from the previous stage ok. So, what is done is that you substitute the equation for C1 here and expand it and you get a two level and or okay that is only the game you know that is what is the carry look at adder. So, the problem is that as you go the higher indexes because it is you know expanding more and more product terms will come in the implementation that is what is shown here. You can work it out I think maybe you have studied. So, it is very simple a C1 is nothing but G0 which is A0, B0 or kind of A0 or B0 and C0. So, that is P0 okay. Similarly, when you come to the next stage C2 is A1, B1 that is G1 okay or A1 or B1 and G0. G0 is nothing but what is generated in the previous which is the carry input to this stage. So, which is nothing but A0, B0 okay or A1 or B1 and A0 or B0 and C0 and that is how the propagated from the beginning okay. So, when it comes to the third stage you have kind of three AND gates and one G2 which is nothing but the kind of A3, sorry A2, B2 and so on. So, it goes like that. So, even if you put say G0 is nothing but an AND gate here, P0 is an OR gate here. So, you get a three stages of delay for any of the stages there is a rupling is avoided but it is a very complex circuit and now at least at a simplistic level we will not be able to write a loop because the sum is no issue, sum is simple but the carry is something which is which go on expands. So, with a signal as we have learned now it is very difficult to write a carry look at adder you can write with variables since we have not looked at it, we will delay that kind of coding for a moment. So, we will just write look at this code you know the equivalent code in VHDL that is what we are going to do. So, I am not showing the entity, entity is same you have like in the previous AB is 8 bit, sum is 8 bit there is a C in and C out, there is a signal which is carry internal carry, internal signal which is kind of 9 bit. So, that all holds good here but in addition we need now GNP generate and propagate which is for each stage. So, we have an 8 bit vector as early in the earlier case we have the carry 0 which is C in carry out, C out which is carry 8. Now, we write a loop not only for the sum but also for GI and PI because that is regular every stage need that only thing is that may be the second stage use the not only G1 the G0 also it is using but does not matter we can generate it parallely in a loop. So, this is the loop index loop label for I in 0 to 7 generate G of I is AI and BI, P of I is AI or BI and sum of I is AI X or BI X or carry I. Now, we are forced to write it each carry equation separately the carry 1 is G0 or P0 and carry 0 that is shown here G0 or P0 and carry 0. Similarly, carry 2 is G1 or P1 and G0 or P1 and P0 and carry 0 G1 or P1 and G0, P1 and P0 or C0. Similarly, it goes and you have to write up to carry 7 does actually matter because many a times you write an 8 bit or 16 bit or 32 bit maybe even 64 bit luckily we are not yet in 128 bit we are the number representation as on now like double precision it can be 64 bit. So, it is not a big deal even if you do not write a loop you can still implement that just because the code is longer you will not end up with any longer I mean any bigger circuit luckily this is hardware not a C code. But definitely if you write this scheme in a C it might kind of similar style in C you might get a very you might take longer time to kind of execute such a code not a problem in hardware though we will definitely see how to write that in a loop. So, but after all you know this is for a practice you know we have looked at the ripple adder code we have looked at the ripple adder carry look adder and but when it comes to the VHDL normally you want an adder you just write you know it is an 8 bit adder then AB is 8 bit vector some is 8 bit vector just say some gets A plus B if you want to carry out we have discussed in the arithmetic section how to write that you know we have seen that you can adopt that scheme but now when you write such a scheme it depends in the library code of the tool how this plus is written okay it will mostly will end up with a ripple adder when it comes to FPGAs or PLDs at least in FPGA there are kind of dedicated adder resorts we will see that they will use that built in resorts to implement the ripple adder which will be much faster than implementing any other adder be it a carry look add or carry select or carry skip or whatever you say a simple plus in the case of FPGAs will be much faster because it is in silicon built into the silicon but if you do anything else it will use the programmable wires which is going to add delays and it is going to occupy lot of logic resources which need to be interconnected and it is going to be delayed. So, ultimately when it comes though we have done some practice with adder when it comes to an adder really we are going to use most of the time the plus operator within that. So, let us take an example of a shift register those who have done an undergraduate program sometime it is little bit you are confused about the shift register because somehow this shift is kind of coupled register you know you have learned a block called shift register in a very particular very restricted fashion and it very simple thing is made very complicated okay. So, when you say shift okay suppose you have a register 8 bit register D7 D6 up to D0 okay this is a MSP this is a LSB suppose you want a left shift by 1 okay like this is stored in a register you want to output say suppose this is kind of save for it is there it is not changing and you want a shifted version of this left shift by 1 okay. It is very simple you take the D6 as the shifted version of for the 7 D5 is used as D6 or D-6 D0 is used as sorry this is I am sorry this is D-1 I will change that so this is D-1 and you append as 0. So, basically when you say shift alone it is just a wiring it is when you say a fixed shift okay when you say shift left by 1 or shift right by 2 it is always a wiring there is no hardware is required okay absolutely take this 6 or 7 you have 5 or 6 and 0 as 1 okay shift left and you append as 0. So, it is just a wiring but now you want to store and suppose this is changing and this is changing continuously screaming as in a pipeline then you need to store this somewhere and that can be stored in a separate register mostly it is done like that very rarely that it is pushed back to the same register. In a serious circuit you will be any computation there will be stored in a separate register but it can be pushed back to the same register and that is what you have studied in undergraduate. So, anytime you say shift this particular picture comes to your mind and sometime it can create little kind of confusion. So, that is what I have shown here you have a source register some kind of wiring for a fixed shift and destination register and wiring could be you know whichever way you want maybe it is everything is shifted by 4 that can be kind of you know all the LSB least significant go to MSB when it comes here maybe this part can come down here depending on the requirement okay. So, it depends on the application the computation but this is what you have learned where the source and the destination register is same. That means you take the queues you have a register which is kind of okay this maybe can be called queue also being the output but I hope the concept is clear then here you take the queue shift it and put it to the D of the same register okay that is a shift register. Now, suppose what happens if it is the shift is variable that means when some control signal is active then you say let us call one control signal called left or right. If the left or right is one then do a shift left by one if it is you know if it is zero then shift right by one. So, the shift is variable now either shift this way or shift that way that definitely you cannot wire it because now depending on the control signal you have to get this or that and that shows a MUX okay you have to have a MUX. So, when you have a variable shift then you need to use a multiplexer. So, I am showing a scheme where in either say you take the queue 6 the D6 part I am showing just one then if it is a shift left then the queue 5 is pushed here if it is shift right the queue 7 is pushed if not if either of that it is not true then maybe the same thing can be pushed okay. Now, it depends on the select line if select line is only one bit then you can choose between those two if it is two bit then if it is for 00 you retain the same you pass the same it is 01 do the shift left. So, 10 you do the shift right 11 again maybe the pass the same or whatever okay. So, when you have a variable shift you use multiplexer in this case it is an 8 bit register. So, you can use 8 multiplexers which is all 3 to 1 okay. But it is possible to view instead of 8 kind of single bit multiplexer maybe you can view it as a kind of huge 8 to 1 8 bit multiplexer. That means that you assume a huge 8 bit multiplexer here the output is going to all the 8 registers and there is connection here to all the inputs and so on okay. You can view it that way also there is does it matter and you can have the coding also written that way whichever way is convenient. So, let us look at a universal shift register which allows you to do the shift left shift right and you can hold the value with the same or you can parallely input some value okay. Like you can load it parallely you can shift left you can shift right. So, we have a register which goes from D7 to D0 when you are shifting left there is an input called ln which goes to Q0, Q0 go to Q1 and so on okay. And similarly when you are right shifting the Rn goes to the Q7 and Q7 go to Q6 and so on. And okay I have not shown the clock but the clock is there reset is there. So, the select line also we have a for take the case of a 6th or the 7th stage Q6 then the D6 you have a MUX here which is 4 to 1 MUX. So, we have two select line when it is say some value Q5 for shift left comes when you want a right shift the Q7 is put in and if you want parallely load something then this input which is coming from the outside PI6 is loaded the 6th bit and if it is not you retain the value recirculate the value okay. And this MUX is repeated kind of 8 times. So, that is what the real the hardware is and now we write the code and when we write the code you could write it as you know one kind of 4 to 1 MUX single bit repeated 8 times or as I said you can have you can think of a huge MUX where the 8 bit output is there and input is also 8 bit because after all the we are connecting all the inputs down here. So, but it is you can expand it to bring clarity to it. So, whichever way you view it but that is hardware. So, this is the library close for it and this is the entity where clock and reset are the input left and right in is a input all single bit select line is because the 4 to 1 multiplexer you have 2 bit parallel in is 8 bit because there are 8 is an 8 bit register and the Q is also 8 bit okay. Now you are you can sense already that okay. Now I am showing there could be a little yes okay. So, we have to maybe kind of you know assign a signal and we have to declare a signal called Q here which I have not done but we can do that instead of a port here we will declare a signal you imagine that this has some other name and we have a signal Q here because we have somewhere we are going to say you know the Q is comma on the right hand side not the right thing to do. So, we have to declare this a signal sorry for the minor error but assume that the Q is signal here. So, now we say process reset clock begin if reset is 1 then Q is other 0 we are resetting all the register contents else if clock tick event clock is equal to 1 then case select is parallel load when 00 we are parallel loading Q gets P in that means Q 7 down to 0 get PI P in 7 down to 0 that is a meaning here then that is a parallel load shift left when 01 Q 0 get L in. So, that is the Q 0 Q 0 is getting the L in and then we can write a loop where for I in 0 to 6 loop Q I plus 1 get Q I for the shift write Q 7 get the write in you can say write in and Q 6 get the Q 7 that means Q I gets Q I plus 1 in opposite to that N loop and if others in other case that means when 1 1 is there or all other cases Q gets Q since we are saying Q is coming at the right hand side this has to be a signal cannot be an output. So, for simple cases you do not verify so that is why it happens you just write the code. Now, you can also write you know that is a code and this is how you should design you know simple thing but when you start you draw the block diagram and you write the code and after a while you know this will be in your mind for simple things at least. So, you can still you know code it with this in keeping this detail in the mind but the complex thing at least the all the block should be shown so that everything is clear. So, let us write this instead of the loop as a single MUX you know that is what we are going to write you know that is how the code is here. If reset is 1 then Q gets other 0 else if clock tick event clock is equal to 1 K select is when 00 Q get P in but when 01 we are going to see it as a single MUX now Q 7 down to 0 get Q 6 down to 0 and L in that is what is shown here Q 7 down to 0 gets Q 6 down to 0 Q 0 and L in now this part get this part you know that is what is shown here and for the right shift it is opposite Q 7 down to 0 get R in which comes at MSP and Q 7 down to 1 ok. So, R in go to Q 7, Q 7 go to Q 6 and so on when others Q gets Q ok that is a code and this is the most elegant code as far as the universal shift register is concerned. So, let us take another example ok which is little bit kind of arbitrary so please have a look at the circuit ok. Now this shows first of all an 8 bit register because you know that this output is said 7 down to 0. So, this definitely are 8 flip flops 8 D flip flops the clocks are connected together reset is connected together 8 bit register the output is combined added with an A7 down to 0 that goes here to a 2 to 1 MUX and when a signal called LOC is there then when LOC is 0 the B gets loaded LOC is 1 this sum get loaded ok. Now we have seen that a set of registers with a preceding combinational circuit can be coded in a single process. So, we are going to write a single process for this but the question is what about this ok. Now this comes looks like at least in the picture it looks like it comes afterwards but then you know that this is a kind of circle and this is also behind though it uses an input called Q this plus this adder comes here you know so you can transform this block schematic like this you know it is same we have you know the plus is put here and z is taken here you know it is exactly same. Now we can look how to code it you know. So, we know that how to code a flip flop you write a process with clock and reset if reset is 1 then this z will be other 0 or the appropriate you know we might use a signal because this is used internally. So, we can define some output assign that and all that then we are everything is synchronous it is upon the clock. So, we say in the clock even clock is equal to 1 if LOC is 1 sorry LOC is 1 then we say this output gets a plus z ok else it gets b that is all ok. So, I suppose you get the picture so we say that if LOC is 1 the output is upon the clock it is under the clock a plus z else it is b. So, it is very simple code. So, we have the library declaration the package 1164 and unsigned mainly because we are going to use this plus and plus is overloaded for standard logic in this particular library and this is a entity now mind you I have put some kind of arbitrary name for it but because when you kind of give a example like that you should not write some obvious name so that the students can detect it. So, this is how I write the kind of questions whenever I give a question I do not write a counter or some legible name or even you know even these names sometime I change so that is not easily obvious like when you go back from a VHDL code to the block diagram. So, here the ports are clock and reset and LOC are single bit input a b which is 8 bit input z is an I know 8 bit output as I said since we are going to use z as an input we are going to define a signal called q which is also 8 bit and we assign z the q to z so that we can use q being a signal internally. So, this is the main the code a single process for this so if clock even process reset clock begin if reset is 1 then q is other 0 else if clock even clock is equal to 1 then we say if LOC is 1 q gets a plus z else b. So, that is it if LOC is 1 then q gets q plus a yes this is instead of z we are saying q plus a because q is the signal q plus a else q gets p and f. So, this is the one which is representing the 2 to 1 marks and this plus represent the adder which comes before the 2 to 1 marks and everything being in the clock even clock is equal to 1 it goes to a register or you get goes to the D of the registers all the bits you know the q7 goes to the D7 and so on ok. And say end if for this one this is the end if for this end process for this end the architecture ok as I said you intend it properly so that people can make out after an experience you know you look at the code you know you can draw the block diagram. So, that is how this particular block diagram is easily very easily. So, just you have the picture here you can write the code or you can even tell your team members to write the code suppose many a times you are designing you do not have to write the code you know you come to a block level RTL diagram and give it to somebody you can code it and the coding is not a big deal designing is a big deal. Once you get to know come to this level then the coding is 1 to 1 you know just look at the picture and you write few lines of code it does not matter you know you see this much you have a register 2 to 1 marks and plus and it does something that is all coded in a very few lines 1, 2, 3 maybe if when I say line you know 3, 4, 5 lines it can be coded because there is very few lines are required for to bring the hardware to code the hardware okay. Now, let us do the opposite okay here what we have done is that you have given the circuit or known the circuit we have go ahead written the VHDL code and we have done that for a very simple known circuit like the ripple adder, the carry looker adder, the shift register and now we have given some kind of random circuit without worrying its functionality and we have coded it it is simple as soon as you put this kind of the block diagram then you can code it. Now, we do the opposite you know somebody has given you a circuit okay. So, a VHDL code you have to kind of make out what the circuit or the block diagram or the RTL whatever you call is okay that is a basic game here. So, let us see and as I said I have made the entity something input something some kind of random names I have not given any kind of sensible link to it I have not shown something is in board something is reset nothing it is just ABCD. So, let us see whether we can make out what is the kind of circuit. So, we have the library close package 1164 for standard logic package unsigned maybe for the I do not know for what maybe the plus if there is plus and standard logic added maybe for this kind of relational operator maybe I have to check you can check that and this is the entity and in that we have 3 single bit A B D single bit input 1 input which is C which is 8 bit 1 output which is Z which is also 8 bit okay. Now, in the architecture we have given some name arc underscore this name of this is the name and we declare a signal Y which is also 8 bit. So, naturally one can assume it is something related to Z and the begin Z gets Y. So, Y is nothing but Z we are kind of circumventing the trouble with output signal that cannot come on the right hand side. So, the moment the Y comes it is nothing but Z. Now, we have a process as a main code which has A and B in the sensitivity list. So, we are sure that A and B are input okay and you say begin and you say if A is 1 then Y is other 0 else if B tick event and B is equal to 1 then and that is end if here okay. So, we are very clear looking at this code that this is nothing but a register and Y being in the assignment it is an 8 bit register where A is the reset asynchronous reset and B is the clock. So, we can already draw a 8 registers with A connected to asynchronous reset B connected to the clock okay. Now, whatever is written here comes to the D because that is synchronous that is written within it and you see that it say that Y which is the output itself equal to C which is input that means whatever was a register output is taken is compared with C if it is 1 okay that is 1 then you see Y i plus 1 is Y i and Y 0 is D. So, it is a kind of shift or a MUX which is doing the shifting it is a single bit shift which is a left shift the least significant bit gets D. So, that is all so it is a register where A is a reset B is the clock at the input is a shift register the shift register work if Y equal to C that means otherwise it remembers its own value which we do not say else. So, it remembers its own value so that means Y is equal to C go to a 2 to 1 MUX which is the Y equal to C output is a select line of that MUX at the input of the select line is a shift or the same value goes to the input that is it. So, that is what is shown here we have an 8 bit register. So, these are thick lines 8 bit the output is Y which is same as Z the clock is B reset is A and the Y goes to compare with C and the output of it is a select line which select a MUX when it is 1 then the shifted version of the Y along with the D Y 6 down to 0 and D goes to the Y otherwise it retains itself you know it recirculates itself that is what is the code shown here. So, maybe you know you have one more nested if then if there is another if inside that comes before okay. You know that this is the IS priority if you write one more if that comes before that you know that is simple like that it goes like that you know you start with here the first if the second if third if and so on okay. So, that is how the block diagram is drawn very simple if you nothing to worry like if somebody kind dumps a huge code to you and you do not know what to do then you sit quiet go from top to bottom at the beginning you will be thoroughly confused you will curse your boss and do not worry sit with the code look at it again start to write you know the look at the signal start writing what are the signal what are the sub blocks maybe the process maybe procedures you start making a simple note of each block what could be that and start drawing pictures gradually things will emerge the clarity will bring will come up and you will be able to decode all the circuit maybe after drawing the circuit you will even find that you could have encoded much much better way in a very simple way elegant way concise way and which is documentation wise better and so on. So, that is why I have illustrated this and okay let us take maybe another example I do not know whether I will be able to complete this but let us look at it at least let us start with it. So, here is little more complex okay I have cooked up something so that to little bit confuse you but it to kind of it to make some sense out of it okay. So, we have library 1164 package unsigned package because somewhere we are going to use plus or something like that some entity UV are the input which is 4 bit W is output which is 8 bit okay. Now, I tell you if you get this in a test paper or an exam you should apply you know you should apply your mind you know there is one thing in real life where you have to get through the answer quickly though I am not kind of convinced that the testing somebody's competence is by doing things fast you know doing things fast represent some experience may not be the intelligence or capability but when experienced guy can do things faster which is many a times you do not have to design you know so fast as a sprint or something like that but it looks the present situation looks like that you know the whole everybody is kind of working hard to keep the moods low true or every two months you have to have a new cell phone which is not really required frankly in my opinion but when you have such a problem you should my advice is that you should guess probably what is this kind of circuit which takes 2 4 bit value and 1 8 bit value sometime looking that will bring some clarity you have to do some kind of investigation somebody called detective work or research somebody called whatever you should be able to give a guess. So, let us come to architecture declaration region now there is something funny happens here there is a type D type 1 is array 3 down to 0 of standard logic vector 3 down to 0 ok. Now we are declaring a D type 1 as something which is a 4 values each of which is 4 bit ok now and we have declared a signal called y which is same as this that means it essentially means y 3 is a 4 bit vector y 2 is a 4 bit vector y 1 is a 4 bit vector y 0 is a 4 bit vector ok. So, for whatever reason it is defined like that that is how it is defined you know you have 4 values each of which is 4 bit and we have declared y. So, you have y 3 y 2 y 1 y 0 or other way y 0 y 1 y 2 y 3 each of which is 4 bit and when it comes to the this one another data type which is type D type 2 is something similar is array 3 down to 0. So, it is a 4 values or 4 locations of 7 bit. So, this is 4 locations of 4 bit this is 4 locations of 7 sorry 8 bit you know 7 down to 0 8 bit and we have declared a signal x which is of this type D type 2 that means you have x 3 x 2 x 1 x 0 each of which is kind of 8 bit ok. So, we have declared 2 signals y which is y 3 y 2 y 1 y 0 4 bit each of which is 4 bit and x 3 x 2 x 1 x 0 each of which is 8 bit and we are declaring a constant called term which is a 4 bit vector which is initialised to 0 that means this is nothing but like 4 bit 0 4 0s ok. That is what is declared here maybe now we are coming to the end of the lecture. So, we will see what is the code here and we will kind of look at it how to decode what is written in the code come out with the proper circuit for it that is what we are going to do. So, that gives a good practice that is my idea going from the circuit to the code to circuit and so on. So, in this today's lecture we have seen basically the carry look ahead adder a symbol adder with a plus operator. Then we have looked at the shift register which is fixed shifting which is nothing but the wiring with registers. Then the variable shift with multiplexers and then we have seen a universal shift register. We have put some arbitrary block diagram and we have written the code and now we are again back to some code to work out the block diagram. So, I suggest now look at these examples and work out your own example and practice it ok. So, I wish you all the best and thank you.