 Welcome friends, we are into the 8th session of ARM web development. I hope you so far have been following the classes and enjoying that too working on the lab. And in the last session we covered basichow constants are being managed for both logical and arithmetic data processing instructions ok. So, that is for operand 2 of the logical or arithmetic data processing instruction. If you remember R n which was operand 1 we I will explain you with a diagram. So, today in this session we are going to talk about logical instructions as well as arithmetic instructions and how if we do operate on R 15 that is program counter how it is going to be impacted ok. This is very interesting topic where you will understand the basic operations done by the processor as well. The freedom that you have to work on the PC registers as any other general purpose register is very unique to ARM, but you need to be very careful with what what to expect when you modify the values of R 15 ok. So,today session will be focusing on these two aspects. The first two will be on the logical and arithmetic processing instructions and then we take an example of multivit arithmetic that is you know that ARM supports only 32 bit data or registers right, but then may be some scientific applications where you need to do operate on 64 bit data or it could be even 96 bit data. So, if that is there is there any support from ARM so, that you can even operate on data which which are higher than 32 bits. So, we will see some examples and the instruction will support them and then the most interesting part will be how R 15 could be used as operands or as a destination register and to achieve different things ok good. So, we are back again with the format. So, if you remember in the last class we spent whole session talking about how the operand 2 is if it is given as a register and along with some shift operation or an immediate value because some shift operation. So, if any of these values are given as an operand 2 how does barrel shifter take that operand 2 and operate on the immediate value a shift operation as well as some constant that you have some one with instruction how it takes them and then prepares the value for ALU ok. So, again I am repeating the operations performed on the using using the barrel shifter is to prepare the operand 2 for the ALU ok it is not the ALU operation itself for the say. So, to just clarify suppose you have a left shift logical or rotate or anything any operation you do or on the barrel shifter is only to prepare the operand 2 for the ALU then what the ALU does is based on this opcode the opcode is what the instruction as such it could be and or or move or compare anything. So, before doing this operation the barrel shifter tuples the operand for it. So, that is what we talked about in the S I A S I A in the last case ok. Now, let us see what are the different operations supported by the ALU if the barrel shifter has done its job and then it has given the operand 2 here and operand 1 anyway is always taken directly from the register file. So, you cannot do any barrel shifter operation here if you want to do it suppose you want to have both the operands you want to do some barrel shifting operation ok. Barrel shifter means what I am saying is any logical operations you want to do and both the operand then what you should do is you should perform that operation on R and separately and the register and then keep that ready and then you can work on the any logical operation that you want to perform on R M and then give it to you should not do it on both of them. If suppose you want to do it on only one of the operand then you want to make sure that that operand is here. So, that in the same instruction it is done ok I hope this is clear and you know these values are this is the destination register where the outcome of this has to go and this any of course talks about R N and this operand could be a just an immediate value or it could be a R N followed with some shifting operation or logical operations on the barrel shifter and then the operand is coming here. Now, we are going to concentrate on various operation that ALU supports provided these operands are ready ok after the respective functions are done. This is the set of operands available the operations that ALU supports. Now a simple move ok this is very unique because it is a single operand instruction of all of them if you see the parameters here all of these other instructions have two operands to operate on whereas, except for this move which operates on only single operand. So, these are the only unique single operand instructions what does it do? It takes the value. So, this single operand is it is R N or R F whenever single operand is there in an instruction especially move on N V N the in the operand is treated as operand 2 not operand 1. What is the reason? Operand 1 comes directly from register 5. So, you cannot perform any shifting or rotating operation with the help of barrel shifter whereas, operand 2 has the facility because that is the way the architecture is defined designed. So, operand 2 goes through the barrel shifter before entering ALU. So, when you have a single operand the single operand is assumed to be coming from the operand 2 N V. Then what happens to operand 1? There is no move instruction does not even look for operand 1 at all ok. Now this is a generic way any instruction is defined. So, you should be able to understand this. So, that next time when I show you this or when you see in any of the manual you get a clear idea. This part of it explains about what operation is requested by the instruction from the ALU ok this is the opcode. Though the whole instruction is as a binary of an instruction itself is a then be considered as opcode from the application perspective, but within assembly the opcode is only talks about the ALU operation. Then it will be followed by optional parameter ok. The clever brackets indicate that this may be there and may not be there in an instruction. Now by now you all be familiar with this this is the conditional mnemonic. It could be EQ or NE or AL there are so many which on table I had shown you earlier whether or less than or equal to or whatever conditions and this this condition is based on the conditional flags ok. If suppose if this is provided suppose MOV EQ is given then if EQ condition is satisfied only this instruction will be executed otherwise it will be considered as a no op. But it will go through the pipeline and the execution stage it will not perform anything and you all feel the presence of this instruction in your register or in a flags in the flags ok. This you understood now S is again I have explained multiple times this if it is present then the S bit in the instruction will be set and which will indicate that this instruction is free to modify the flags based on the operation it performs that those flags may be impacted. So, it is not that when you put yes all the flags will be affected it is again depends on the instruction some instruction may affect only one or may be three or it may not affect one I will show you where uniqueness of this happens, but otherwise this is indicate that this instruction when it is executed if it is modifying any flag any conditions it will be reflected in the condition of the CTSR ok. And this is the destination register and this is the operand operand to that we are talking about. So, this can go through some value shift in operation before moving into R D the value is moving to R D that is all about MOV 1 and you know that MV MOV just moves the operand to MVL complements that that is the not operation on it and then moves the value to R D. Now, this is a whole set of instructions are there please do not read this now I will come to this point this more later. Now, let us talk about every instruction what it does and it is very simple and operation of you know by a Boolean operation. So, this bits in operand operand 1 and operand 2 are ended with each other and the result is written into ok. And again this has a condition the you know this can be mentioned here and operand 2 is ended and with R N and then the result is written into R D. So, exclusive R does an exclusive R operation and subtract there is a operand 1 is subtracted from operand 2 it should be very clear which is getting subtracted from the. So, always the convention is the first is considered after the destination register the first is operand 1 and the second is operand 2. So, subtract subtract this value from this ok whereas, reverse subtract does the reverse of this ok that means, it is subtracting this operand 2 sorry it is subtracting the R N the operand 1 from operand 2. You may wonder why there are 2 instructions required for this. If you remember the diagram earlier what I showed you just we will go back I said only the operand 2 is going to the barrel shifter right. Suppose you are interested in the operation ok here we come back. So, here you want in the reverse of that you want operand 1 to be going to the barrel shifter. Suppose you are interested in sorry if you are you want to subtract this from this, but this one you want to want it to go through the barrel shifter. So, that is achievable in this RSV you can write it this way then it will take the operand 2 flow is always same, but if you want to subtract the operand 2 from operand 1 this is becoming easier right. This will always be the second value which you are subtracting it is going through barrel shifter here the reverse is happening right it is on this side of the subtraction. So, that is what the convenience given to the compiler and the assembly program you can use anything, but you should be aware of what is getting subtracted from 1 ok. So, add a simple addition now this is add with carry what is the need for it? I will explain this when multiple add a arrow I told you that there are additions possible where the operands could be more than 32 bit by ok. So, that kind of additions when you want to do you perform 32 bit addition and then that carry if it is coming you want to posit on to the next set of value that you are going to perform arithmetic operation on. So, for that the carry flag is passed on to this instruction. So, this is the convenience if you want to consider the carry also to be added with the operand 2 you will be able to use this instruction to perform. So, I will show you an example here and then we will understand that. Now, subtract carry actually you are supposed to just subtract when you are subtracting a operand 1 minus operand 2 the carry you wanted to subtract some, but here it is what is written is carry minus 1 what does it mean? If suppose carry flag is set you are not subtracting anything, but if carry flag is 0 you are actually subtracting 1 why is it so? Actually your intent was to just subtract carry. The reason being in the ARM processor the carry flag is cleared by a subtract that needed a borrow ok. It is actually a reverse of what happens if suppose there was a borrow the clear carry flag is cleared when the subtract operation was performed. So, in that case you have to do the reverse of what you would have done if carry flag was set when you needed a when the subtract operation was a borrow right. So, to to comprehend this what is being done the SBC is implemented internally this way, but as an as a programmer we do not have to worry about this ok. You can as well as when you want to do a multiverse subtracts what you should do is you first subtract the lower words with the S Y S is required where you want that subtraction to affect the flags then only you can use that carry or a borrow flag carry and borrow flag are same ok. So, the carry flag that you can use it for the next instruction we using a sub carry subtract with the carry this you will be doing it for the subsequent higher word words that you are subtracting ok. And why do you have to do a S here also because you want this instruction also to impact the flags. So, that you can build the next higher word operation. So, as you are new for example sub here, but you can do the same thing with the add also ok you have to do add S here and then ADC S here if you want to do multiverse addition. So, this is the way this is performed ok. Now reversal RSC is again just reverse similar to RSV, RSV with the carry also you do, but operand 2 comes here and operand 1 comes here ok. And then these two are all Boolean operations R operations it is just a it performs an R operation between 1 and 2. And this what does it do? It use a complement of this and then answer to the operand 1. So, I will tell you what is the need for this ok this is to clear up some bits ok. In a particular positions you want to clear some bits you need to whatever bits you want to do clear initially that you will be mentioning it here and then you do a do a not then those bits will become 0 and when you and it with them the operand 1 those relevant bits will become 0 here. So, you are effectively clearing those specific bit position by mentioning them in the operand 2. So, this does this job I hope you are clear with this set of instructions I will show you some examples in the subsequent slides. Now, what are they? This is actually this note is not 11 for this instruction ok please ignore this. When any of this test is done what does it do? It actually does a AND operation with the both the operands operand 1 and operand 2 and based on the result it will impact the flags, but it took the result will not be written into any destination register. So, you would not be mentioning anything here it only takes 2 operands there are no you need to mention only 2 operands which need to be tested against each other and you would not be mentioning any R D the destination register. So, what does it mean? Test means it is actually comparing 2 values and see whether they are same or not because when you and it with you know the same bits the if they are set you will get the same value again ok. So, based on that it will set the flags and you will know that they are equal the values are same the bits are same test equal it what does it do? This actually does the XR of that and then it compares whether the particular bits are all become 0 because when you XR the same value with the same other 2 such value then you will get the 0 here. So, if you are getting 0 flag set that means, they are equal ok. So, that is the no job. So, compare is it is comparing 2 things that actually performs a subtraction and then flags are impacted and CMN is a actually it performs a I add operation and then impact the flag. So, basically these instructions are provided where you want to look at the flag, but you do not want to really perform a chain you are not interested in the outcome of these values ok. Only the flags you want, but not the actual result coming out of this instruction then you will use this ok. This is about compare and test test are called on the Boolean operation as well as compare is performing the arithmetic operations ok ok. Let us see some examples what we make the things clear. The data processing operations may be classified as logical arithmetic the logical operations are all of them ok even the P, U and the test the logical operations understand that ok. So, it is a working on the bit level ok it is not trying to understand the values of those bits it just does a Boolean arithmetic or Boolean operations like r x r r n and then affects the theory flags if it is a flag. Now, when you perform a Boolean operation or logical operations on base the overflow flag is unaffected right overflow is useful only when you are doing a signed operation right. So, when you are doing a Boolean operation there is no interpretation of signed or unsigned right. So, because of that overflow flag will not be affected even if you have a S bit set in any of these instructions ok. Now, R D is not after is a special condition we will have another you know last session we will be talking about that. So, let us not worry about that. Now, carry flag of course, this will be affected based on the if suppose you perform any shift left or the type left or an logical or arithmetic shift the bit last bit coming out will be impacting the carry flag ok. And if it was LSL 0 I have talked about this in the last session it will preserve the carry flag of the previous value whatever was the previous value ok. And 0 flag will be set is the result what you get in the end of the operation if it happens to be 0 you will get a 0 flag set ok. So, only this n flag will be when bit 31 is set. So, only these 3 flags should be operated by the logical operation, but not B flag. So, these we should remove that and you should also know the reason for that ok. Now, let us see take some time just freeze for some time if you want more time find out what is the right answer for this. Why is B flag underrated by the logical data operation? It could be since B flag and C flag are always the same of any logical operation or because it will delay the execution of logical operation or B flag is valid only when the arithmetic operations I think in my discussion I have already told the answer. So, this is C ok. So, B flag plays no role when logical operations are performed you should remember in this ok. Now, I told you that compare and PQ there are two instructions what do they do and why are they why there are two instructions. Both doing the checking whether operand 2 1 and operand 2 are the same or not ok. Then what is the difference why is given as two instructions for this both do not write this result ok. You know that compare and PQ both will not write the result because R D is not mentioned. So, the in both I am telling you both are equal in the in these two aspects. Now, we will see where is the difference coming there is a minor difference in their behavior compare affects all the flags why it does a subtract operation internally right and then the result is not written, but it performs a subtract operation operate operand 1 is subtracted from operand sorry operand 1 minus operand 2 it does ok that is what I have to say. So, operand 1 minus operand 2. So, and you know any arithmetic operation will affect all the four flag. So, compare does that. So, it will affect all the four again you should remember in respect to of whether S is mentioned or not actually compare always affects the flags it is not based on S that is one important thing about compare and test. These instructions even C M N as well as the other test ES other instructions the four instructions which do the comparison job they always affect the flags irrespective of whether S is mentioned or not. Some compiler some assemblers may crib if you may give warning or error if you put S some may accept it, but internally the they they set the S ok those are the flags are set that is one important point I missed open the last slide. So, PQ affects all the flags except V flag. So, that is the difference you see. So, of course, then why there are two instructions use TEQ when you need to preserve the best state of V flag while performing equality check. Suppose you want to perform a equality check you have an option to choose one of these instructions then if you are dependent on the previous value of V flag then you better use TEQ because if you do a compare that will may be that may be overwritten by this operation. So, if you want this to be preserved perform PEQ. So, that you can use that in a subsequent instruction how do you use it may be you will you will put a less than or greater than side values you can compare and then based on that you can choose to execute an instruction or not. So, if you are using V flag remember to use PEQ before that if it is needed if you want to do a comparison job ok. So, that is all about logical operations. Now, let us talk about arithmetic these are the things why this compare and the compare end is also listed under the because they are internally performing the subtract operation which I told you. So, they also fall under this category they operate on 32 bit into here of course, because that is a width of our registers. Now, one thing I have mentioned earlier, but I am just discussing on this point only the programmer of that compiler. So, why compiler because if suppose you have declared an unsigned in U your name of the variable is U and then signed in yes you have declared two variables with with one being unsigned and another being signed and then you do a addition or subtraction and then you are comparing whether if this one is more or less you are comparing unsigned values or signed values while writing a program you may have mentioned the variables to be unsigned or signed. Then compiler knows that ok this variable is signed or the other one is unsigned and then it will accordingly choose which flag to look for when it has to do a comparison ok. As far as the processor is concerned what is stored in a register is an integer of course, that is the bit integer, but it does not know whether it is holding a signed value or unsigned value. So, the processor when it is performing any arithmetic operation it will impact both the flags based on how you are going to interpret. So, it does not know that whether what you have really put inside the register is an unsigned integer integer because the representation is how you interpret the value is different in case of unsigned or signed. So, any arithmetic operation will impact both the flag and you are free to choose one of them based on what you know about those variables ok. So, this is very important point number that. Now now again I told you that any of the arithmetic operations also can be followed with the appended with a S or more. If there is some S then the assembler when it is generating the binary of of course, for this it will put that S bit set inside the instruction. So, then processor will know that ok when I am doing this I need to impact the flags ok. So, if S bit is set only we will be talking about this flag otherwise in another instructions change the values of the flags condition flags. So, B flag will be set only when the over flow occurs if the values interpreted where choose complement value. One more thing I you need to remember that internally ARM processor I think most of the processors in the market negative numbers are represented as choose complement and they are heated like choose complement. The arithmetic what it does is a choose complement. So, if it is a negative value it is a choose complement form ok. If suppose if you are maintaining once complement and then you are trying to put that value into it if your interpretation is once complement and actually processor is choose complement then you will have a different values. So, you should remember that most of the processors are most setting in the market everything treats the negative values as choose complement. So, when you are treating the signed integers you meet it treat it as a choose complement value. If it is negative you have to if MSB is set you will complement all the bits and the add one to it to find out the magnitude of the negative value ok. C flag is set if this very simple if bit 31 is set the C flag will set. So, these are all the results which are coming out of the instruction ok not the operands this is a after the operation is performed what is the result and based on those conditions these flags will be set provided a S is there and N flag is set if MSB is set. So, you may interpret it based on the N flag if you have to as a choose complement then it is shows the negative value ok that is it. So, this is all about how arithmetic operations impact the fact. Let us see some more details of it add instruction as the value on R n with the operand 2 and R m that is the operand 2 if it could be a register coming from R m or it could be immediate 12 bit why I put 12 here that you you know that the immediate constant value whatever is the space provided for the instruction by the instruction is only 12 bits of constant or combination of both. Suppose you are doing a shift operation then you will have a constant associated with the R m will be a operand 2 ok the subtract instruction that is the same thing only thing is it does operand 1 minus operand 2. So, operand 2 is again coming from many of these. Now, reverse subtract is operand 2 minus operand 1 ok very useful because barrel shifter has more operations for operand 2 ok that is why if you want to do a operand 2 minus operand 1 and, but I you want to do more a barrel shifter operations on the operand 2 here then you will be able to perform this using this instruction or reverse ok. So, you can do along with the carry if you want to do a multivariate arithmetic you can use any of this instruction this will be covered ok an example for this multivariate arithmetic will be covered soon ok it will be in a few seconds or minutes. Now, this is what add C is instruction as the value of R n and operand 2 ok together with the carry flag. So, if carry flag is set then one more will be added to this value if it is 0 it is same as add there is no difference. If there is no carry flag if carry flag is 0 the addition of R n plus operand 2 will be same as what you would have got with the add, but if carry flag is set it will be one more than what you got with the add. Now, subtract with carry it is the same impact the carry flag borrow is there then it will have done it, but internally because carry flag is clear because ofis borrow borrow is there. So, carry flag is clear the result is reduced by 1 ok it is a reverse because of the increment I mentioned earlier and that is 2 with R S V reverse subtract with carry and one more thing just wanted to caution you that the some assembler may substitute some different values different instructions. So, when you are reading the this assembly listing of the instruction you may have to and more than assembler the compiler may do the ok you may not you may expect some instruction to be there, but it may have something different because it would have optimized something. So, when you try to understand assembly listing of what you have got from the compiler output you may have to think about what are the changes it has done may be you know there may be some dependency on the previous instructions also you may have to read the complete flow to understand if there are any differences in the instruction being used by the compiler ok very good. Now, let us see a multi word arithmetic. So, simple addition all of us aware we just wanted to give you an example of a multi word arithmetic that is suppose you want to perform a 64 bit integer addition. So, how first of all how will you store a 64 bit 64 bit values when you have the registers which are only 32 bit wide you will split the 64 bit value into 2 the LS part of the word the least significant word is stored can be stored in one register. So, in our example we have stored like this ok. So, we have two sets of registers one is stored here and another one is stored in this registers and you are subtracting it now sorry here you are adding it. Now, when you are adding it what is happening this first R 0 and R 2 ok you remember the format of instructions this is R D this nation register this is operand 1 and this is operand 2. So, this is operand 1 this is operand 2 and it is subtracted sorry added operand 1 is added to operand 2 and result is written into R 2. Now, why is this S n given it is very important you have to give X because you are based on this addition if you do this R plus R 0 plus R 2 there may be a carry from the result which should also be added with this to get a correct value otherwise you will get a 2 additions, but it it will not be correct. It is simple as you know when you have 12 plus 19 if you do 9 plus 2 if you add after that that one carry has to be added with this you know simple our school days we have studied about the addition. So, that is true with the multibord arithmetic also. So, when you are adding this it is all single 64 bit words. So, when you add these two anything coming out carry has to be given to these values to be to get the final result which is correct. So, you need to use add C add with the carry you have to use and very important that you have to put yes it means out on this here whatever is the previous value of carry flag will be taken by this instruction. So, you may get correct result sometime and you may get something wrong at some other time because it purely depends on what was the state of carry flag before it came here. So, these two are you know adjacent instructions and you should know you should not put any of the instruction in the domain which affects the flag and you should perform this one after the other and make sure that yes is there. Now add with carry also you are free to put yes or not, but I have put yes here because any result will be valid only if suppose even this also over flow then you will need look at the carry flag to see that the 64 bit version is as a war flown or not, but it is not mandatory if you know that I am not going to exceed the limit of 64 yeah you free to do it, but there is always better to make it a habit to do this because it is not going to add any delay or anything to your execution of the instruction it is only later on you can decide to use those flags conditional flags based on the requirement. So, this is safe way of programming in a some way. Now I want you to just hold on pass the presentation and then try to map this instruction into a 96 bit operands ok. What I showed you is 60 per bit this is 32 and this is 32. So, adds up to 64 suppose I have a multivariate I want to perform a 96 bit operation here I am interested in subtract ok. Now how do you map these registers you see a lot of registers here how do you map them into this this nine registers after 16 to one more column you have to add and then you have to map them. I want you to map these two values and the result value also. So, that when you are writing this multibord arithmetic you are clear about how to mention the preference if you if you modify change them sequence you will get different results. I hope you have already tried out let me show you hope what you have tried and what you are seeing it is correct see here. This is whenever you are doing any arithmetic as the schools school days we have learned you have to perform the arithmetic from this end right right to left. So, you have to perform the operation on the lower significant words. So, that is what is given as a parameter. So, which is operand one we know based on the arms instructions format or operand one is this that is why R 6 is here subtracted from operand 2 sorryalways mention it wrongly. So, R 9 is subtracted from R 6 that is operand 2 is subtracted from operand 1. So, R 6 minus R 9. So, you have to be careful and where the R 3 goes I have not shown here where does it go it is a result. So, let me show R 3 comes here now R 7 minus R 10 and the result R 4 6 here R 8 minus R 11 and the result goes to R 5 ok. One more and of course, the instructions you need to be careful you cannot put sub here you have to put sub C S B C along with carry and here also S B C and S C here is a must ok. If you do not do it then any carry coming a borrow from here will not be reflected for the when you are doing a third set of operation. So, this S is a must and this is optional if you want after the result is found you are interested in what has happened to the result you can put S, but this two are important ok. So, take some sample values of this and then put them in registers and then see the result ok. Now another thing what you notice here is these registers are all sequential right R 6 or 7 or 8 or 9 or 11 is it required? Is that we need to be very sure that when you are doing the operand R 6 should be here and then the next is here higher our registers should be there actually not. You can use any registers you want provided you do not overwrite on them then results you nobody can predict, but as long as you are not overwriting any of these values and you are careful when you are overwriting also ok then you will be able to see the proper value. Here you see R 9 is there in two places it impact see here operand 1 operand 2 this is operand 1 this is operand 2 it is performing the subtraction here and the flags are already affected now this result I want to write it in R 6 that is fine. Now R 2 and R 1 is subtracted and the result is written into R 9. Now what happens this is actually overwriting on one of the operand, but it is ok because this operation is already performed. So, you are not you do not need this value anymore. So, you are free to modify it, but you have to be careful when you are reusing any of the registers, but ok and then R 8 and R 11 is written into R 2. Now you see here these values are registers are all arbitrary there is no any inherent sequence as it was in the earlier example. So, why I mention this is you should remember that the ARM processor are typically you know any you know any of these operations are performed here it does not take any sequence between this you know whether you are ordering them in a particular sequence or not it just just does what you are given here ok. So, as long as you do not overwrite which is required for the next addition or subtraction you are free to use any registers you want. They treat them as a two operands to the operation that is all, but please remember that S is a must in these two cases of course ok. I hope you have understood the multiple arithmetic here I want you to perform do this with some different values both positive and negative find and find and then see the results for you to be sure about this ok. Now, it is a interesting part of the discussion R 15 why R 15 is so unique because this is a program counter because this is pointing to the instruction being executed, but the freedom that we have with ARM is this is also part of the register file though it has got separate read and write course to enhance the performance it can be treated as any other operands to any other data processing instructions. But you have to be careful about what you are doing with this other ways you will get a unpredictable result. So, you have to have a clear idea when you are using R 15 in your instruction you should have a clear idea of what to expect and unless you understand the pipeline and how internally the values are the PC are modified you will not be able to use it efficiently and correctly. So, please pay attention to this adding any two register values and a constant you could use PC for R n ok this is all of it. If you use PC as R n or R m ok you can use R n and R m also we have shown only this example as given you can have R d also I will tell you how to be careful about what what you need to be careful about. Now, suppose you are using it as R n and R m what is the difference between this R n is the operand which is coming straight from the register file and R n is the through the barrel shifter. So, it treats R 15 as a generic any other register. So, it can read from the the instruction can read from the register file, but I am saying the value is current in section 38 this I have touched upon this when I talked about pipeline. If you remember there are three stages in the pipeline in arm 7 and first is fetch ok may be a ok fetch next is stages decode and first stage is execute. Now, you have to remember when is the operands for the operation whatever you are performing is where the from register file. If you remember correctly it is done at the execute stage execute stage ok. Whereas, in arm 7 it is done in a decode stage on line in a 5 stage pipeline, but here let us restrict to the arm 7 now and then there are three stages and operands are read during this execute stage. So, if R 15 happens to be one of the operands where is the R 15 pointing when a particular instruction is in this stage. Remember before this instruction comes here the next instruction is already inside the pipeline which is in decode stage and next to that whatever instruction is there that is already fetched and it is in the fetch stage. Now, where does R 15 point to when you have instruction 1 instruction 2 and then instruction 3 suppose 3 instructions are there you are executing an an operation here add ok and then you are using the R 15 as operand here ok maybe R n or R m to write it into R d. When are you reading all R PC ok this is PC when are you reading this PC when you are in the execute stage of this instruction. But by the time R 15 is pointing at this two instruction down the line. So, each instruction you know that it is occupies 4 bytes each right 4 bytes not bits ok let me write b. So, it has already advanced by if suppose this was 1000, 1004, 1008. So, plus 8 it has gone that is why when during the execute stage when this instruction is interested in reading the operand and when this operand happens to be R 15 it will not get the its own address where it is decided it will get the 4 bytes 8 bytes and always it is in the increasing order always PC is incremented. So, it will be 4 bytes more than 8 bytes more than the current instruction remember 8 bytes more than the current instruction ok. So, if few of performing any operation on and taking the R 15 as a operand you have to remember this this actually you should take you to this even the pipeline you should remember the pipeline what is exactly happening you should not just mug up that oh ok whenever I am using R 15 I should have 8. Now, whatever I am getting is plus 8 no it is because of this reason please remember that because this pipeline different these are the pipeline stages I have gone ok. Because of this and the operand is being read only in this stage you will get a value which is 8 bytes more than the address of the current instruction ok. I hope this is very clear to you all ok. So, let us see two examples. So, that you is clear to you if you are using a PC as a RD ok what suppose RD is what the destination register the execution branches to the address corresponding to the reference. It is true right when after the any arithmetic operation or a move operation you have changed the value of R 15 because you are using that as a destination register. That means, whatever you are writing you want that is you want that to say to the processor that I am writing a new address to you please pick pick the instructions from there. So, it is supposed to do that. So, whenever RD is modified it will start by executing the instruction which is stored in that address. Suppose if you use S flag suffix is a separate interpretation for that I will talk about it later when it is appropriate. So, just for a moment you ignore this you can use SP also for R what is SP the R 13 ok. Remember R 13 is another special treatment is treated as a stack pointer. So, you can also use SP there is no sorry there is no restriction ok. So, I hope you understood this. So, let us see few examples for you to understand this. Now, assume that R 0 is holding a 1000 value 0 x 1000 ok this x additional value R 1 is having 0 4. Now I am interested in performing this operation I am I am interested in loading the R 15 with the new value. So, what happens R 0 is 1000. So, it just simply adds 4 to that and then writes into it. Now, remember that you need to be careful in whenever you are changing the value of R 15 here it is a ARM processor ARM mode. So, we are not talked about ARM mode at all. So, let us in this ARM mode the lower two bits of the addresses stored in R 15 are zeros because it is always 4 byte aligned instruction which is going to fetch. So, you have to make sure that you do not change those convention ok, because different processors may implement in a different way and then may get a different research and and if you know side effects. So, you have to make sure that the research can value what you get should not have the LSB two bits the lower two bits bit 0 and bit 1 should not be set it should be zeros. Then in the ARM mode ok we remove this I am very very particular about that in the ARM mode you have to take care of that. ARM mode is totally different which we will talk about it when I talk about you know when we touch upon the ARM mode in this execution. So, here you say I what I am trying to say is you should not add 2 or 3 to it ok R 1 you know R 1 1 you are 1001 if you write into a some processor may ignore the two bits and then access it from 1004 you know 1001 bit, but it is not good programming practice or that you do not do this ok. That is why I am telling you that whenever you are changing R 15 it is not like any other register it is a continue with the program counter. So, you will immediately see if you are running this code in your simulator you can immediately see that the execution jumps to the address what it is pointing at ok. So, the difference between this and this is and S is added of course, then you will see that the facts are affected. All 4 facts are affected because you are doing your add up function of course, and then the result is same it actually moves to 1004 only both cases, but only thing is the facts are also impacted because of this instruction. Now, another example suppose this is very you know I have complicated little bit and reading from R 15 ok and then adding it to R 2 and writing into R 15. So, here we are doing a subtract operation. So, R 15 is taken ok when this instruction is executed when it is in execute stage the value of R 15 at that moment is taken as one operand which is directly taken as R n and then R m is just R 2 which happens to be 8 here. So, you are taking R 2 and now R 15 is subtracted R 15 minus R 2 and then the result is written into R 15 again. So, PC value is taken and subtracted from whatever the value of R 2 and then written back. Now, what do you expect here? If you remember just now I mentioned that what you see in R 15 is the not the address of this instruction it is plus 8 ok. So, because because R 15 has already advanced because of pipelining pre fetching it is now trying to pre fetch 8 by 8. So, effectively what are you trying to do here from this address wherever it is now 8 by 8 plus 8 by 8 it is you are subtracting minus 8 from there. So, effectively you are bringing back the value of R 15 into the same instruction. So, I urge you to write this code you make sure that you know you do not have to do this precondition because already R 15 anyway is there only R 2 you make sure is move R 2 comma 0 x you have to 8 you do and then perform this and see what happens. You will see that the simulator will not move from this instruction because every time when it executes this instruction it is bringing the R 15 back to its own instruction. So, the pipeline will be flush flush again it will be loaded with the same instruction and then it results in the same value because what are you trying to do whenever R 15 is going ahead you are bringing it back to this location again it goes back and again so, you will be continuously in this row. So, this is a very good example to write out is try this and understand it why it is happening. What I explained in the previous slide is the reason for it ok. So, because operands are read during the executes phase the R 15 has already advanced by 8 bytes and again summarizing it. So, R 15 has already advanced by 8 bytes because it has already pressed two instructions one is in decode stage and another new one what is it is switching is in fetch more stage. At that moment you are taking the value of R 15 taking a snapshot of that value and trying to subtract it from subtract the values by R 2. When you subtract R 2 this also happens to be 8. So, you are bringing the value back to the address of this instruction. So, it will come back to this and then it will continuously be in a infinite way ok. I hope this is very clear to you. Now, one more example is instead of doing it from R 2 you could do also from the immediate value both have the same effect only thing is it is coming as an immediate constant ok. Again subtracting what happens if you do addition here it is here it will go to another 2 bytes ahead. So, you will jump 4 instructions and then start executing it for that. So, I urge you to try different things, but only thing is you have to have valid instructions maybe what I what you can do is write your assembly code with lots of move instructions maybe 10 to 15 move instructions to R 1 R 2 R 3 you move different values into R 1 R 2 R 3 maybe to have a clear idea R 0 you move it with R 0 1 2 3 4 like that and then try to in between you squeeze in this instruction and you change the instead of subtract add add it or instead of 8 you do some other addition, but please make sure that it is always divisible by 4 this constant and it should not be more than 12 bits because you remember the immediate constant cannot be more than 12 bits. If you do that you will be able to see the where does R 15 go and if it crashes that means, you have updated with the wrong value. So, debugging will be very difficult when you are modifying R 15 value. So, we need to be very careful about it ok. Another example I will show you R 13 you know that it is a stack pointer is already with the 0 1000 sorry 0x 1000 and then we are adding with 4. So, it is same no R 13 is also it is in the same way no difference ok and you could add it with a constant also you will get the same result. Now, it will jump to 1004 it is a constant jump. So, 0x 1004 whatever instruction is there it will start executing from there and what does it do here? I am just showing you that you could also have a barrel shifter operation some logical shift right with whatever is the content of R 3 you do this you will get again 8 bytes ok. I want you to try out all these instructions and see yourself what happens now one question ok. When R 15 is used as one of the operands as I showed you know like a previous examples can it can its value be more than plus side compared to the address of the executing multi cycle instruction. What I mean by multi cycle instruction? It could be this load or store multiple bytes ok or it could be a mull instruction ok or add in you know any instruction with attributes for more time actually even it could be a RS you can using RS as a register for shifting operation ok. Assume that an instruction which takes more cycles because suppose you are doing multiple store you will be having a different memory cycles ok. So, the execution stage is not completed in one cycle it could take more than one cycle. If that is the case can R 15 be more than plus side and the current address. Think for a while what happens in arm 7 KDMI with the 3 stage pipeline if a particular instruction takes more cycles to execute what happens? Will R 15 go further? See which start with 2 any instruction needs to cross 2 stages to come to execute stage. So, 2 cycles are already done. So, it is implemented by A now what I am asking is in the execute stage if that instruction takes more cycles because it is a multiple store. So, there will be more store memory cycles will be involved in storing or loading the values from the memory. During that time can R 15 go beyond 8 bytes and now keep on accessing instructions down the line think for a while ok no ok. Now, I told that it is no. So, can you reason it out after hearing this if suppose you thought it is yes. So, let us see this quiz is about I am sorry the answers ok options are there ok. This quiz is about the reason for that I said that ok it cannot be more than 8, but why? Let us see one by one operands for the instructions are read from register file earlier than execute stage of the pipeline. I am not making any whether I am not saying that either it 2 or not it is because I am saying it cannot go beyond the 8 because the operands are read the architect is read earlier than the execute stage ok. So, it cannot change even if multi cycle instruction is executed whatever you are read from the register file stage same right it cannot be more it cannot keep on changing based on the cycle instruction. Even if multi cycle instruction is being executed pipeline is stored until the current instruction is completed because of which the instruction prefix cannot happen not more than 2 instruction I had. What I am saying is even if this instruction a particularly execute stage whatever instruction is there it takes multiple cycles to complete can R 15 proceed further it cannot because unless this instruction goes out of the execute stage the decode stage instruction cannot move into execute stage and the fetch cannot move to decode and the new instruction cannot form in. So, what I am saying is the pipeline will be solved if any one instruction takes more cycles. So, that is one reason another one is even if R 15 is added by more than 8 by it is old value is maintaining temporary location saying that the other option says that R 15 is stored in a temporary location firmware. So, because of which the old value is maintained that plus 8 is there. So, it cannot be more than plus 8. So, again read this question as well as answers and then come to a consensus which one is correct ok. It may be equally confusing all of them or you may be clear about the option to choose ok. The correct option is B because there are more explanation for a book. So, that should be the reason if you are thought there are more lines are there that the option should be correct please do not do this next question I may have totally different combinations. So, the reason being the pipeline is stored when a particular instruction in execute stage takes more cycles to complete the good example will be multiple store or multiple write read or load or multiple store or load. The R 15 also stops because we cannot fetch any more instructions because decode stage also phases or fetch stage also phases and until this execute stage whatever instruction is executed is completed. So, R 15 cannot go beyond 8 bits I am talking about ARM 70 they are made not for the future processors there may be some processors implementation will be different. So, thus this particular discussion is only for this ok ok. Now, let us talk about the implemented cycle times of each instruction ok. Normal data processing one sequential cycle why is it one sequential cycle? I told you the pipeline has short you know instruction keep coming in then the effective throughput of throughput will be one instruction per cycle. If there are no stalls or if there are no flash then you will see that every one in cycle sequential cycle you one instruction will be coming out of the pipeline. So, effectively any data processing instruction will normally take one S, S is sequential cycle, N is non sequential and I this is I which is internal cycle. If you remember I have explained about these cycles earlier sequential cycle is if the instructions are accessed from the sequential addresses it will involve sometime which is equivalent to sequential cycle because memory is provided with a subsequent sequential addresses, non sequential addresses because it is provided with a totally new address it has to fetch from a different location and there might be some delay involved based on the type of memory that you are interfacing with the processor. So, N is non sequential addresses how much time it takes and internal cycle is something the processor wants to do internally some operation which will does not involve any memory access. So, that is internal. Now, let us see before we see the reasons I want you to even think about it why these are the timings given for different instructions. So, that you have a clear idea. Now, let us see what is the reason for a data processing with a register shift specified shift what I mean by register specified shift a shift value is not immediate constant it is stored in the lower 8 bits of a register if you remember RS ok. Now, when a register is holding the shift operation what constants know how many shift operations need to be performed or rotate needs to be performed if it is held in the RS there is one cycle involved in first reading that register and then perform that operation ok on the RM and then feeding both RM and RM to the ALU. So, internally there will be one more cycle explained if there is a register specific shift in the instruction that means, for the operand 2 if I had mentioned I my shift constant is in the RS that means, you have put a add R 1 comma R 2 comma on R 2 comma R 3 that is a second operand you are saying that LSL RS that is RS may be some R 5 or something. So, if you are doing the shifting operation based on the content of the register another register then it will involve one more cycle ok. Now, if suppose a data processing is on PC that means, RD is a PC what happened this instruction has changed the value of PC once the PC value is changed a non sequential cycle is started because it is not same as the sequence was current instruction is going. So, there will be a one non sequential cycle because it has to fetch a new instruction and flush the pipeline and fetch a new instruction by performing a non sequential cycle with the memory and get it into the pipeline. Now, where does it get that instruction it cannot directly get it into the execute stage it has to get it into the fetch stage then one more cycle two more cycle will be elapsed the fetch stage and then it will take one more cycle to for that instruction to come to decode stage then only it will come to execute stage. So, the next instruction which is fetched by based on the PC value new PC value return will will experience a delay of two sequential cycles. See again this particular reason is because of the pipelining I am not blaming the pipelining because it you are getting a so much of performance in a normal flow of sequence, but when you are changing the flow when you are flushing the pipeline anyway we have to live with the delay involved. So, any performance no pain with no no gain without pain right. So, you have to live with this 2 S delay because you are changing the instruction somewhere you have to fetch the next instruction it is not a next sequential instruction. So, you have to fetch the pipeline which has already the two instruction which are coming to the pipeline have to be fetched and the new instruction has to be fetched. So, that is the reason. Now, this is you are doing a register shift operation also the to find the value new value of PC you are trying to find, but you are doing some register shift operation along with that. That means, you will have one more internal cycle because there is a there is a one internal cycle. So, that is also additive. So, it is a combination of the second and third ok. I hope this is clear to you. Now, before the intersection some examples I want you to now by now you must be familiar with all the instructions whenever you see any instruction you should be able to you should come on your mind ok what is happening you should not be reading the nobody will be there to write the comments because you are supposed to write the comments when you are writing assembly code. So, whenever the familiar assembly instructions you see you should get in your mind that what is happening is that is very important to get familiarized with the reading assembly instructions. So, I argue to read lot of instructions and see what is happening there. Now, spend some time in understanding each instruction there is no sequence it is all independent instructions, but are given here to see your understanding. So, add eq does it is that flag is set please remember eq is there 0 flag is set then this is added and put into R. Please you should you know you should have got this what is tq s does it tests R 4 equality with the 3 and the s is in fact, redundant as the assembler insert is automated what I mean by that is even here is the programmer you have mentioned here or if you do not mention s also anyway it is going to impact the condition flags because all come cm compare instruction and test instruction affect the condition flags. So, s is redundant here. So, lengthy, but you should be familiar now after having listened to the last section. See here register specified shift is given whatever is the lower byte of R 2 is taken that much of logical shift write is performed on R 7. So, it is very easy LSR takes the opposite value instead of hash 0 x and constant it is taking from R 2 and we should remember that it is a lower byte of R 2 and then that many times it is going to do this operation on R 7. So, now operand 2 is prepared that operand 2 is then something with the R 5 based on this insert. So, R 5 is subtracted R 5 minus this value is written into R 4 ok. Now, what is this do this does this R 14 is moved into PC. So, this basically normally when you are calling we are not covered that. So, that is why you may it may not be familiar to you, but R 14 is a link register we will talk about it later, but actually at this moment you can think that whatever R 14 is pointing at it will start executing from that location ok. Now, what are the different between these two? The only thing is this does not impact the flags and this impact that is it. Apart from that there is one uniqueness about this ok. It will be clear to you when I talked about modes let me explain here. This is very specific because I told you earlier that I will explain this in a second. Normally when there is a mode change or exception has happened it the previous value suppose one instruction has caused an exception then the address of the next instruction which is supposed to be executed will be stored in R 14. This will enter automatically. And at that time even the flags are also copied into the new SPSR register. This is a stored program status register ok of the new mode. So, when this is executed from the new mode it is copying both the new value of PC from R 14 and then the old SPSR which was stored in SPSR is also restored back. For this moment if you do not understand do not fret I will talk about it when we have a discussion on mode changes and how exceptions are handled during that time this will become clear. But you have to remember that this is the specific special instruction which does something more ok. So, that is enough for now. So, with this we are completing the session 8. We have touched upon the logical data processing instruction then all the arithmetic data processing instruction and what are the flags get affected by each of them and how to perform multi word arithmetic. And then we talked about how PC could be used in the data processing this we saw few examples too. So, this is the right time where you have more instructions in your hand that means you are familiar with more instructions and more different ways of writing them So, this is the time for getting into a serious assembly programming and we will be given with lots of assembly sorry lab assignments and we will be able to enjoy these sessions in the lab ok. I hope this session was useful and thank you very much for your attention and hope to see you in the next session. Have a nice day. Thank you.