 Last time we discussed about the perspective, about historical perspective and trends in VLSI design. In that part of that 2 or 3 hours, I discussed with you one of the major requirement of digital system these days is called high performance circuits and high performance circuit and the other one we said low power circuit and then low standby power circuits. This particular lecture today which I am going to now go on for next hour plus, I am going to discuss something how to design this so called high performance circuit which essentially means fast CMOS circuits. We still believe that CMOS circuit will be going to be continue to have some kind of vehicle for any digital system for many more years to come. Now this topic particularly which I chose today a way of designing fast CMOS circuit called logical effort. Now why this kind of method I am suggesting? As an analytical person many of you probably are not, most of you are right now designing things on computer using CAT tools but when you are designing a chip on a CAT tool using a CAT tool, please remember that there has to be some initial, some kind of a back of the envelope calculations done by you to get typically which kind of design one should use to get the required performance. And the starting point essentially is to be done mostly in analytical way. So this part of the lecture essentially talks about how to design or start designing circuits for high performance and do it little analytically and the effort which is shown here is called logical effort. Before I start I must tell you that this I wish to acknowledge many of the people who has helped me to get to this topic. There are three people whom I want to actually thank or rather salute them. They are Ivan Sutherland, Bob Sproul and Dee Harris for their great logical effort. Actually they I salute them simply because they wrote a book on logical effort way back in 99 2000 and that is the source of today's lecture. I received this, maybe it is interesting to know that I received this first version of the book from the website of late 90s before its publication itself one of my colleague at Stanford actually forwarded me the link and I could read this book, read this part of the book then and was extremely impressed how to do a design analytically for a high speed circuits. I also wish to thank one of the same author of the book which is Dee Harris. He along with Bob Merman actually gave the first such course on this logical effort in their course at Stanford and I have been happy, I am in lucky that I could get some of their slides. The third important book which I normally refer from my digital design book is by John Rebe of UC Berkeley. He along with Dr. Chandrakasan from MIT and Nicolay from Berkeley they have written the book on digital integrated circuit design published by Prentice Hall and in their chapter 13 they have also have talked about some part of the logical effort and they just gave the word effort there. Of course there is very concise way they wrote there, this particular lecture probably expands it much more than what is written in this book. I am also thankful to many of my postgraduate students of my VLSI design course in last 25 years. They kept asking me many queries when I taught this courses and probably that has improved my fundamentals to a great extent. To start this talk I have outline for my this lecture. I will start with introduction to some extent I already give you the logical effort estimation of gates will follow then I will talk about FOX, amplifier chain of stages, branches and logical effort for other circuit families and finally I will give some concluding remarks. Now let us say you are a chip designer and if you want to design a chip for a given system you have a bewildering choices to make. This right side photograph shows your difficult situation in which you are put to before you decide what to do. So what is the what are the queries one gets into? So what is the best circuit topology for the function of you wish to implement? How large should be the transistors to actually give the performance? And how many stages of logic will give the least of the delay? Now these queries are not very easy to answer in many cases. Many of us actually go on the using cat tools you have a schematic created and start putting initial values of some width to length ratio of each transistors and start doing circuit simulations. You can see when you do such kind of this tweaking a value is never a accurate way of doing things because it may take larger time or it may never actually converge to a correct solution. So where to start? Even that is very crucial and even if you are using a cat tool. This logical effort is a method of answering many of these questions. What it does? It uses a very simple model of delay. Then it allows you to do a backup envelope calculations and therefore it is much easier to track table optimization. You can always do some kind of optimization because much it's an analytical function at your hand and then gives new names to old ideas to emphasize remarkable symmetry. So it's not that this idea of generating design method using logical effort is very different from what we were doing all the time. But this is slightly a modified and better way of doing the same thing. So who cares about logical effort? In my opinion these though people who are circuit designers and they many a time they waste too much of time simulating and tweaking circuits. And therefore they should first start with logical effort work so that they don't have to waste too much time. Then the people who work on high speed logic design need to know where time is going and in their logic which part of the logic has largest delay. And therefore to get the critical pass in the system this method may help quickly to know which is the critical path or even in a particular path which block is giving the slowest slowest propagation and hence contribute to larger delay. And the finally of course the CAD engineers need to understand circuits to build better tools. I am always of the opinion that a CAD tool designer should be a good circuit person because only then he can appreciate the problems in circuit and then can create a tool which is much more stronger in actually applications of any circuit designer. Here is an example of course is taken from Harris lecture, Ben Biddel is the memory designer for a motor old 6886 he is designing a chip 68W86 which is an embedded processor for automotive applications. Now typical some part of the circuit is shown below and now what is very easy help Ben design the decoder for the circuit shown here. Now if you see a typical circuit we have 4 to 16 decoder to a register which actually drives the register file which is 32 bit wide and 16 feet depth. So which has essentially meaning 16 word register file each has 32 bit width each bit represents a load of 3 inch size transistors 2 and complementary input of address bits are available each input may drive 10 unit size transistors. So Ben need to decide what can this requirement for this design is how many stages to use how large should each gate be and how fast can the decoder operate. Now basically when I talk about the speed you must appreciate that the speed is decided by the propagation delay that is the signal going from input to the output how much time it takes that decides essentially the speed. Speed means essentially 1 upon the delay is equal to the frequency of operation and since we are putting a data at a given rate this maximum rate with which data can enter is decided by this clock frequency or this decide by this the highest frequency available. Now here is a simple inverter shown so what is the inverter shown you have a transistor 2 transistor 1 the p channel transistor the upper transistor and your n channel transistor m 1 which is connected in a complementary mode. Now if I give an input at v in here which is common to both p and n channel as a complementary input and this is my output node now this output is connected to its load may be a similar inverter or may be a different inverter or more than one such inverters which is called the fan out or the load of the circuit through a wire which brings this output signal from the first inverter to the load part. So what essentially we are now saying that when the input changes how fast this output will change because the change in this node voltage can be decided by the capacitive charge stored from the at this node. So when we look into actually the what is the net capacitance this node is actually seeing when input is changing or input is actually given to this input a. Now how do we calculate the capacitance so we go back to theory of transistors and we look into this fact very carefully we say ok since there is a MOS transistor and in a MOS transistor you have a gate capacitance associated with the oxide capacitance and also you have a parasitic capacitance between gate and drain a gate and source gate and drain similar for n channel there is a capacitance between gate and drain and gate and source there is also a capacitance which is p n junction capacitance associated with source and drain and there is a capacitance which essentially we call drain to substrate or bulk capacitance and drain to source to this capacitance. Since there are so many capacitances associated at this node one has to then find the net capacitance. So there is a capacitance CDB2 and CDB1 coming from these two transistors at this node then there is a capacitance associated with the wire wire means any interconnect line between this node to the next load will have some capacitance and this capacitance is associated is we call as interconnect capacitance CW. Finally since you have a some kind of a load whose input will be capacitive in case of MOS technology based on systems so there will be some input capacitance of this stage which essentially in this particular case it to gate to source capacitance gate to source capacitance of both n channel and p channel and essentially one is talking about the capacitance of the gate oxides. Now if this net capacitance here which is the load for you plus wiring capacitance plus the CDB2 plus CDB1 at this the net capacitance is some of all these capacitances and that is the load which this inverter is seeing. Now unless you compute all of them one cannot see whether the capacitance will charge how fast or how slow it will discharge or how fast it will discharge. So change in this node voltage potential at the input changes can only be known what is the value of this capacitance and what is the currents these circuits are able to provide for charging or discharging. Now I will just give you the idea here how do I calculate each capacitance before we proceed further. Let us assume right now all devices all device capacitance are lumped into a single capacitor CL. So point I am saying this plus this plus this all of them together I call as a load capacitance. Assume that input V in is driven by an ideal voltage source that is at this point I can give a step input voltages 0 to 1 and 1 to 0 or 0 to V d d and V d d to 0. Now and assume that is a step source. Now we have a composite CL you know this plus this plus this. So we want to know the net capacitance coming out of it. The first capacitance you see from here this is called CGS or CGD. Similarly this is for input side obviously this also is relevant but for output side calculation these capacitances do not come into picture simply because they are not connected at this node but they may be connected to if these are driven by some other source for this source they may act like a load for them. So we proceed ahead we say okay here in inverted driving this capacity load CL in which there is a CGS CGD sorry CGS in CGD as the two capacitances these are called gate to drain capacitance and the other is the idea behind is if there is a channel existing in the transistors basically what we say the gate to channel capacitance can be divided into two parts half of it will say going to the drain side and half of going to the source side by similar logic if this is the n channel transistor half of the capacitance is lumped at the drain side half of that is lumped to the source side and we calculate this CGS and CGD both CGS values. Please remember this is the source of a P channel transistor this is source of an n channel transistor the drain capacitances are actually drain to bulk or drain to this are not taken care because they do not appear in this node okay. Now this CGS and CGS for P channel and channel will act as net sum which is appearing here then there is a diffusion capacitance due to drain to bulk capacitances you know after all there is a diode PN junction diode sitting between source and the substrate and drain and the substrate and since they these are reverse bias junctions they will contribute to a junction capacitance. So that is called diffusion capacitance CDB CDB and CDB 1 for N channel and P channel and finally there is a capacitance and of course this you can think of this they are essentially decided by something we call a model which is called linearity model k which has a factor k equivalent which decide how much is the junction capacitance how much is the junction capacitance associated because we know at different biases the junction capacitance will vary because the depletion layer will vary and because therefore we must evaluate the capacitances at given biases during the transition here of course this has been done already in earlier earlier nodes of ours but if you really want to know more about please look for ashrangian west book or any other book on digital CMOS VLSI design and find out how to calculate CDB or any device book for that matter then there is of course as I said is the wiring capacitance CW which depends on width please remember any width and length of the wire epsilon a by d if you see a capacitance the width of the wire and the length of the wire will decide essentially the because the thickness is fixed which is the oxide capacitance thickness of the field oxide and therefore it was not much different from the other side only width and length of the wire may decide the wiring capacitance longer the wire interconnect you are moving flowing larger will be the capacitances associated. So, please remember there is a wiring capacitance there is a capacitance due to the input of this stage which is your load stage and there is a output capacitance coming from your driver stage these are this is the inverter which is driving this load and is connected by wire please remember this is called fan out this is only one inverter shown or one gate shown they can be more than one such gate where this nodes is connected down up or many more and is called fan out. So, larger the fan out obviously the load capacitance will also increase now how do we calculate the different capacitances we know capacitance is delta Q by delta V. So, we can calculate the junction capacitances using simple p n junction theory we may assume the p n junction is to be abrupt or you can say step other kind of junction which is linearly graded or otherwise and from that we can calculate some constants and therefore, we can evaluate to some great extent the capacitances of the junction at different voltages. So, I can calculate C j of the junction and therefore, at different voltages and therefore, I can get C d V 2 and by similar logic I can get this please remember the capacitances here which is the capacitance between gate and source and gate and drain if you see very carefully. These capacitances are essentially given by as I say they are lumped capacitances half here and half here and one can say it is nothing, but the oxide capacitances of each. So, K s epsilon naught or rather epsilon 0 epsilon s i 2 by T ox into half half we are half on this drain side half on this drain side the net capacitance is called C g d V which is also equal to the source capacitance this is half of epsilon 0 epsilon i 2 by T ox into area of course, and using this aurea is w into l that is the obviously, these capacitances all of them are proportioned to the width of the transistor. Now, switching response you know if you want to find out the switching response what I actually start talking about switching response shown here there is an input pulse given to the last circuit shown already by me and based on that in input circuit I am going to actually try to tell you how the currents will flow. For example, if this is my inverter this is my P channel in transistor this is my N channel transistor and this is my V in input V in and this is my output this is my V 0 and it is essentially I say all of it all the capacitance lumped at the output is C l. So, this is P channel this is N channel let us say this is w by l of P this is w by l of N is available to known to us and because of that we can evaluate the currents. Now, if you see the response initially let us say when you say at T is equal to 0 V 0 is 0 therefore, V C l is 0. So, what does that mean it essentially means that this transistor N channel transistor may be fully turned on and unless this is fully turned on this node voltage cannot go to the ground. So, obviously if this voltage is going to be ground because of the CMOS action when N channel was fully conducting the P channel must not conduct is that correct it must not conduct. So, obviously initially P channel was not conducting N channel was fully conducting. So, essentially you were at this point when V in was high making N channel fully conducting and P channel switched off when I go the step down from V high to V low as it is let us say V low is 0 in our case in case of CMOS and V h is normally V dd. So, what we say that when V in goes to high to low initial condition is T is equal to 0 V 0 is 0 therefore, no charge across the capacitor when the input switches down. Obviously, at the gate of P channel you see a voltage 0 and whereas, you see a gate at the N channel you get see a voltage 0. So, obviously transistor T n turns off whereas, T p turns on call this T p is upper channels turns on on means it is conducting. So, obviously during the transition this input voltage is changing from high value to a lower value and at that start of that value what is V ds for P channel transistor the V ds for this channel is essentially V dd V 0 minus V dd because this is the drain and this is the source of a P channel. So, V 0 minus V dd and V 0 was 0. So, obviously this voltage is very high any decrease in V in towards 0 the V in minus V s which is the V gs. So, V gs minus V t starts actually increasing, but at that time initially when you are going down this is a smaller value you subtract it out of V t. So, this is even smaller this voltage across drain to source is very high. So, device enters T p starts in saturation in sat mode transistor is saturated. Whereas, if it is in saturation we know the current of a P channel device in saturation, but as the current starts moving coming from here it starts since N channel is switched off we believe of course, not all of it initially we may say all of it, but in reality some current may go through a channel. So, this power supply through P channel now provides you a current to charge this capacitance to a higher value of voltage essentially means if I plot V 0 versus T initially voltage starts rising as the current start charging the capacitor. There will be a time when V 0 becomes sufficiently high V n is already 0. You can see the V gs now is very high V gs minus V t is high whereas, V 0 minus V dd is coming down because V 0 is increasing at that time after certain value say let us say here the device then this was sat portion and then we say ahead of this the next part is due to non saturated P device. So, device enters non saturation and then you have a non saturating current which is function of V 0 and which starts charging and finally, of course, says them totally it reaches to V dd and at time taken to reach to V dd we called as the rise time 10 percent to 90 percent as we shall show you later and we say the switch as occur input has gone from high to low output has gone from low to high. Now, this is called charging transient by a similar argument one can see from here when V you have an input low and you give a transient sorry V low is 0 and you go to V h which is essentially V dd. So, initially V 0 was at V dd, but at that time this transistor was fully on as soon as the output input rises to V dd P channel switches of N channel turns on and the charge on this capacitor which is C L V dd now starts discharging through this N channel which is turning on. Now, what is the status in which T n which turns on because at initially it was at 0. So, transistor was off then when V n exceeds V t N channel turns on, but V g s minus V t is still very small V d s is very large V d d minus 0 or slightly less slightly less than V d d minus V 0. So, obviously transistor again N channel also wakes up in saturation and once it starts saturating as this capacitor start discharging the V 0 keep falling and V d s of N channel start reducing and since V n has already reached to V d d there will be a point when V d d minus 0 minus V t N is larger than V 0 minus 0 which is the V d s and then the transistor will finally enter non saturation. So, in both cases the initial rise or initial fall is because of the transistors are in saturation and the next when it actually half way down or not half way may be one third way down both devices both in the case of charging the P channel enters non saturation and in the case of discharge transient N channel transistor goes into non saturation after a while. Now, this is called transient response and the time taken essentially reflects. So, now if you see a current of a any N channel transistor or a P channel transistor one can see from here what is the current one can get typically current in a mass transistor can be given by let us say N channel first M u N C ox W by L of N channel V g s minus V t N into V 0 or V d s minus half V d s square this is when V g s minus V t N or V t N is greater than V d s. So, for this condition we know transistor is said to be in non saturation channel exists in a mass transistor let us say this is N channel shown here this is a P substrate this is your gate oxide and this is your gate and this is your V d s and this is your V s ground source is normally grounded and you are applying V g s here. So, obviously if the channel exists throughout V g s minus V d s must be larger than V t which essentially means V g s minus V t must be larger than V d s channel exists throughout and we say devices in non saturation. However, if I keep increasing V d s for a given V g s as well then it may occur that at some point of the time V g s minus V t will be less than V d s and if that occurs the channel at this end will get pinched off and if you further increase the channel will move channel point will move on the left side towards source and you say you are in saturated region of the transistor. So, since the currents in the case of non saturation is shown here only I am showing right now for N channel alone mu n C ox W by L for N channel and then we say it is V g s minus V t whole square because we say V g s minus V t is much smaller than V d s sorry I said otherwise V g s minus V t is V d s is much larger and at some point for a given V g s minus V t N is we call V d s at fixed value at which transistor will enter saturation and then half V d s square V d s square minus half V d s square which is essentially reconverted back to V g s minus V t N square. Now, the point I am trying to make if I want capacitor to charge or discharge faster from the current point of view if I had to charge faster I must provide you larger current and if you want to discharge I must also provide larger discharge current and the currents are proportional to size and of course, they are way if it is N channel it is a mobility is larger than P channel device because mobility ratio is larger. So, we see now that if I want to improve the charging transient or the discharge transient one method of doing is to increase the sizes is that clear whenever transistor has a size and transistor normally if you see a I V characteristics of a transistor carefully if you see a transistor characteristics ideas versus output characteristics of a transistor ideas versus V d s. So, you can see for a given V g s it is something like this for a different V g s it is different kind of thing V g s increasing. So, what we are trying to say you that up to this for example, device is in non-sat mode and beyond this somewhere here is sat mode if you see the resistance on this side and if you see resistance on this side of the transistor idea delta I d s by delta V d s to the minus 1 is the resistance of transistor R on. So, obviously if you see R on this in non saturation the device has much smaller resistance whereas, in the case of saturation the resistance is very high extremely high in fact. So, correspondingly R on if you see in a transistor and since the transistor acts like a resistor we can see from the figure now we go back to this slide here shown here I am now talking as if both charging and discharging transition acts like you have a voltage source you have a transistor resistor equivalent of resist transistor is replaced by resistor both for discharge and charge it will be p channel transistor resistor in discharge it will be n channel equivalent resistor and this is the load. So, how do I charge or discharge a capacitor particularly if I am charging it V out is 1 minus e to the power minus t by tau this into V finally. So, we now figure it out the charging transient essentially essentially decided by the tau which one can say typically the delay time associated is 0.69 R c propagation delay. So, what essentially is trying to say tau is time constant R c. So, and if you solve this one can say the proper time taken to transmit signal from here to here is l n 2 into this this is approximation because currents are not linear, but assuming that. So, in this case is true. So, one can say if I want to improve the speed which means the propagation delay I want to reduce R and c should go down, but c is increasing because that load is not known to me. So, if c is larger or I am not known to me only way I can change the speed is by changing the R if I want better this R should reduce and I just now said the on resistance with transistor is smaller if the size of the transistor is larger. So, one can now get from the simple calculations that all that we are now trying to tell you is that if I want to improve the speed of the inverter both resistances of N channel and P channel should be correspondingly reduced at a given input voltage for a given load such that the propagation delay time is minimized. The figure here I think having shown you figure here shows now and transient response of an inverter or switching response this is my input versus time I am giving a pulse input pulse and I figure out that even after I give my input starts rising it takes finite time before the P channel output start falling down by simple reason that there is an input capacitance also needs to be charged before this will start responding. Now, once it start N channel start turning on when the input is rising initially input low essentially means N channel is off and P channel is on the output is high. Now, input is rising as input rises the N channel turns on P channel turns off and because of that I can say the voltage at the output as we discussed just now keeps falling. Now, the definitions of these is essentially like this the time taken from 90 percent to 10 percent of output from higher to lower is called the fall time by similar logic when you are going from high input to lower input we say for when the input rises from 10 percent to 90 percent the charging transient is called rise time. But we define two other important term which we say TPHL and TPLH we say 50 percent point of the input to the 50 percent of the output the time delay is called TPHL here and for the charging transient 50 percent of the input to the 50 percent of the output we call TPLH. This we already discussed we all of you know very well this is very well done in the Ishrangian's book as well as it is given in Rebe's book. So, you do not have to this but since it was a again a video course I thought I will repeat it what I did earlier in the case of this. The net delay one can see from here average delay one can say not net if the total signal has to cross the inverters you have to go through an average delay of TPHL plus TPLH average means TPHL plus TPLH by 2. So, we say an on and average a signal will pass one bit of signal can pass in a delay time which we called propagation coin Tp which is nothing but average of TPHL and TPLH. So, if we reduce both TPHL and TPLH obviously my Tp will decrease and therefore the circuit will become faster. Now, how to compute capacitances here is something interesting things I have shown you Cgd1 is 2 Cgd0 Cd0 essentially stand for capacitances per unit length. So, if we multiply it by width then it becomes Cgd1 if I multiply by p channel transistor width then it becomes Cgd2 then these are the junction capacitances this is junction constant as I derived in my last slide A is the area P is the perimeter of this transistor area I mean on the surface and one can then evaluate both junction capacitances Cd1 and Cdb2. If you want to know what is the capacitance at the input Cg3 and Cg4 essentially it is oxide capacitance net oxide capacitances. So, C ox is capacitance of oxide per unit area multiplied by area which is Wn into ln by same argument for a P channel it is C ox Wp into Lp and of course, wiring capacitance decided by the technology is used and the length of the wire you are using. So, you need to extract from the circuit layout what is the Cw value and finally, the C l the net capacitance is sum of all of these now here another issue in the transient one looks for. So, one can let me go back again slightly. So, if you see this capacitance once again so obviously, if I reduce the capacitance in RC time constant then the speed will improve. So, to improve speed one must look into you know the area term the width area essentially come from Wn. So, essentially the dimension of the transistor W and L they actually decide what is the kind of speed the circuit is going to have and apriori do we start with the minimum area transistor W equal to L equal to the feature size or do we start with some numbers which is more closer to the expect value of Tp and therefore, can make the guess where to start the our today's effort is to show you how to guess these initial values of W and L. Now, another issue which many of us are worried about in the case of CMOS circuit is what we call as switching thresholds. Now, why are we worried about switching threshold is the following and typical inverter character output characteristics or transfer characteristics is shown here input against output for different value of beta and beta p and beta. Beta of course, as I say in my calculations if I not shown you somewhere I may repeat in my all of my calculations beta is mu C ox W by L. Obviously, if it is N channel I will call beta n is mu n C ox W by L beta p is mu p C ox W by L of p and W by L. Obviously, if I define my beta ratio as beta n by beta p from these two expressions one can see that if C ox is same and the mobility ratio of N channel to p channel and the surface mobility ratio is 2 typically to make beta n is equal to beta p the size of p channel must be double that of size of N channel and that is very important. This is called beta r of 1 means beta r of 1 means beta n is beta p assuming mu n is 2 mu p we say W by L of p is twice that of W by L of n. So, one can see from here that the if I change a beta ratio I am now seeing the transfer characteristics is moving from one end to the other end and what is the importance of this transfer characteristic one can see from here the point this characteristic starts falling at this point when beta r is 0.1 this characteristics is say beta r is 0.5. So, what we see beta as I increase beta r the transfer characteristics starts moving now what is the importance of this region the where it falls from high to low this is called a point at which transistor goes from high to low and is the most important characteristics of any inverter this is called the point at which it actually falls down is essentially called inverter threshold. Now, one can see inverter threshold is say for one it is somewhere here closer to 50 percent of V d d whereas, if I reduce beta ratio further I mean beta r ratio higher which is beta p but this is beta r ratio of 10 and this is beta r ratio of 0.5 or this. So, one can see if I increase the n channel device width through length ratio compared to p channel larger my threshold point moves towards left and if it I increase the p channel device larger compared to n channel width wise then I move towards my right essentially the threshold points keep moving away from it is origin let us say at beta r equal to 1 that is n channel equal to p channel beta you are here and then you move either this side or you move on this side. One can see if beta r is 10 or something or higher larger n channel size means strong n mass smaller p channel size means weak p mass by same argument if I have beta r ratio is 0.1 or lower then we say your weak n mass and strong p mass. So, depending on the what kind of sizing you do this inverter threshold actually changes what is the important inverter threshold one can see from here in the inverter threshold typically for a C mass show very interesting value it shows V inverter is equal to V d d plus or rather beta r ratio. V T n minus V T p divided by 1 plus root beta r where beta r is this V T n is n channel threshold and V T p is p channel which is negative. However, let us take an example V d d is 2 volt V T n is 0.6 volt V T p is also minus V T p divided by 1 plus root beta r where minus 0.6 volt and let us say initially beta r is 1 case 1 then I get V inverter is equal to 2 minus 0.6 plus 0.6 minus 0.6 divided by 2 or 1 which is essentially V d d by 2. So, if you have a ratio of beta r equal to 1 and V T's are same magnitude wise then you get 50 percent point as inverter threshold and that essentially means you have a good switch this is your V 0, this is your V in, this is your V d d by 2 and this is your V d d. So, obviously 50 percent of input side you have high and 50 percent is low it looks more like an ideal switch and that is what switch circuits are expecting. So, beta r equal to 1 is very good if switching inverter threshold is 50 percent. However, many time this sizes will be decided by the speed since we already said the speed decide the capacitance is decided capacitance. The optimum value of beta r will never come good for 1 equal to 1 in case of speed requirements. However, for a good inverter threshold to get you expect beta r to be 1 and therefore, there is a design issue which we have to worry about because in whenever your inverter threshold moves from left to right or right to left obviously the noise margin are comparatively different for rising and discharge transients and because of that you may have a noise problem at the end of the day. So, if I go ahead this is what I think I already said. So, maybe I repeat again just because the figure is here is taken from Rebe's book when the input goes from initially input was high and suddenly went to 0 and channel device turns off. So, you say this switch is opened then the p channel is fully on initially in saturation and then in r p is varying, but initially r p is larger and then becomes smaller as you enter from saturation to non saturation and the current starts moving from V d d towards capacitance net capacitance. So, it starts charging. So, input is from low to high as output is from low to high initially it was discharged now it is charging towards the high. So, it is called charging transient in the case of discharge transient the input goes from high to low suddenly. So, one can see initially this was fully charged to V d d and now sorry low to high and therefore, as n channel it fully turns on p channel switches off. Now, this capacitor will be fully charged to V d d voltage actually discharges through this and depend on this value of V out or V c the status of transistor changes initially transistor in saturation higher resistance. So, initial transient is slower, but as the voltage falls transistor enters non saturation R n becomes smaller and the capacitor then discharges faster. Now, to get a equal kind of charging and discharging one can expect r p c l must be equal to r n c l net r p s these are not constant, but equivalently saying r p c l must be equal to r n c l and if we can achieve this delay equal to each other then you say propagation is universal or symmetric. So, if I want to design a propagation delay which is average of lies time and fault time I mean T P L H and T P H L one has to keep c l small which of course, is the ideal if I reduce the speed if I want to improve the speed I must reduce the capacitance, but that is not in our hand too much. However, some parasitics can be minimized by layouts and we must decrease the resistances R n R n and R p s and to do this we must increase the size of transistor W by L. This is a very simple first order calculations one shows that all that I have to do is to increase the size of n channel P channel. However, to maintain a good inverter threshold I may have to adjust the ratio of P to R as well and because to get a good noise margin. So, there is a tradeoff between noise margin and the speed to some extent. So, before I move further let me give you what we have learned. So far we are not entered the area of logical effort before we start the logical effort part I just want to recapitulate whatever we did earlier or we know about in the case of dynamic response. Four terms we keep talking about one is switching speed which is limited by time taken to charge and discharge C l. Then we say rise time a wave form to rise from 10 percent to output at the output please remember output wave form to rise from 10 percent to 90 percent of a steady state value is called rise time and wave form to fall from 90 percent to 10 percent of steady state value we call it a fall time and then we say delay time t d time difference between input transition and output transition is t d average delay and we define therefore, that average delay as a propagation delay which is sum of average of T P L H plus T P H L and the maximum in frequency which is allowed typically by any inverter for propagation to occur is one upon propagation delay. Essentially one many times a designer does not use one upon tau p as the maximum speed he assumes that in his calculation of T P L H and T P H L which are directly functions of capacitance he has underestimated the value of capacitances and the worst case all the parasitics and underestimation may add to let us say the maximum value may be 4 times the capacitance which was actually there, but I and estimated only one kind one type and therefore, the worst frequency which an inverter is can always work is one we say one upon 4 tau and that is the safest system speed you can work on. But in when we are scaling down the circuits now the dimensions of the every transistor actually we are reducing the sizes so much that the propagation delay should become higher I mean smaller and smaller. So, if we start taking now this one upon 4 tau as our universal this will be this will be beating the something which we are trying otherwise we are trying to improve tau p itself without actually going for C, but now you say I think that we have not done well and make it 4 times tau which is not fair and therefore, evaluation of tau p now is becoming very very crucial and essentially therefore, it is become very important to know what is the capacitance value one has to drive and what is the current each in charge and discharge time I can provide so that I can minimize tau p L H tau p H L with the available capacitances which I may get and therefore, what speed a particular circuit can attain. If I do this analysis which a transition analysis I said typically I can derive this expressions T P L H is C L net capacitance K P essentially is half you know K P by 2 is beta P, but right now we assume that 2 has been taken care beta by 2 is K beta is mu C of W by L. So, we this is spice version they say instead of beta P by 2 or beta n by 2 they write K P and K n. So, you can see from here this is beta P by 2 in case and this is beta n by 2 C L upon this which is P channel threshold this is P channel threshold divided by this part of the charging transient low to high you can see from here if you see these many term this essentially is looking a linear kind of thing or due to the larger resistance provided in the saturation. Whereas, if you see the second part which shows log term one can see from here why this log term is appearing. Log term is appearing simply because in the case of non saturation we have seen the current which I may repeat I may show you again in the case of saturation this is like a square law whereas, in the case of non saturation there is this nonlinearity or some kind of a transcendental system is appearing V d s here and V d s square some quadratic terms appear in calculation of V d s. So, therefore, if you solve this using these current values you will essentially get into a logarithmic solution or exponential e to the power t by tau kind of this and therefore, this will give you a log term. So, the log term appears when the transistor is in non saturation and linear terms occur when there is devices in saturation. So, the first part of the T P L H and T P H L both are essentially to saturation transistor mode and the second part that is C L K and V d d this into this is essentially to non non saturated N channel this into this multiplied is essentially be charging due to these non saturated P channel and one can see from here this value is smaller than this. So, discharge transient once you reach some value of V o lower than V d d device will enters non saturation and it will discharge faster by same logic initially it will take time to charge, but then will charge fast using exponential functions. Again looking at the expressions of T P L H is one best method of reducing the T P which is average of the two is to reduce C L. You can always say if you reduce V d d increase V d d, but if you increase V d d the power is going to be larger and the whole effort in V L S I is to reduce power and increase speed together. So, I cannot play and for a given node V d d also will be given by T R S. So, it may be 2.1, 1.5, 1.2, 1 volt, 0.8 volt, 0.6 volt. So, this is not so much in my hand also. V t's of course, are also technology dependent depending on the node I use V d d I have V t's fixed. So, if you look at very carefully for a given load C L cannot be say minimized. The only thing I can improve the speed is this K p and K n which is essentially mu C ox W by L half of course, but essentially mu C ox C ox is fixed for a technology mobility of N channel or P channel is also fixed for a technology. All that I can change to improve the speed is the size of the transistor W by L. Now, therefore, the question rises how do I optimize the delay and that is very important because at the end of the delay the delay essentially means the time taken for input signal to go to the output is the is the delay propagation delay. So, I want to know how do I optimize this? Now obviously, I have different way of two methods of doing that. I can have different gates in the circuit or chain of gates. So, I must do properly what I say gate size selection which kind of gates I should use and what sizing I should do for them. That is the how much current they should be able to drive. Gate size essentially is proportional to current required and corresponding the current will provide from the transistors N channel or P channel for charging discharge. So, I must size the transistors. Please remember if you decide a size for your current requirements you must believe that since W and also are directly connected to capacitances it looks sometime very funny that you improve in a R C time constant by scaling you may reduce capacitance, but proportionally you may increase the resistance. So, R C should remain constant, but that is not so. So, if that means at given technology no better speed can be attained. So, to beat that system I must now somehow find how to reduce the delay for a given logic to implement. Now in real circuit these days for example, most of the circuit designs are done through IPs available IPs which earlier ways to call standard cell design approach in which you have a library that offers multiple dry strength of cells that is it can drive 1 milliamp current, 2 milliamp current, 10 milliamp current or half a milliamp current. These are pre designed, prefabricated, pre tested and their schematics are provided with this data. Of course, they do not tell you what is the technology in and what is the value, but they will give what is the kind of schematic value I mean at the end the what is the performance values and current synthesis tools do a very great job for gate size selection. So, that is not a big issue. The second part is the sizing of the transfer itself. Now it is done in a custom design in which you size individual transistors during the design process to optimize delay. Now how does it depend on the quality depends on individual designer some synthesis may help or that is available to you synthesizing tools are very greatly available these days. And you keep iterating you keep simulating with iteration a tempting option, but can be time. For example, I can have million I am not million say at hundreds of W by R ratios and values which I can keep substituting in a circuit and keep simulating. Of course, as the word go there is no zero probability system. So, someday you are going to attain a speed or times you are looking for and you say you have achieved W by R for that speed, but doing so the window for marketing the product would have been already have lost or may be you are two years behind. So, no one is going to buy your system anyway and because of that the speed is cracks where to start simulation therefore, is most crucial in starting the design. There are many algorithms for gate size selection already exist. So, that is not a big issue, but and one such approach is very famous is called Tilos algorithm. What I am going to talk about is Tilos algorithm in nutshell can compute the delay along a path of gates have multiple gate sizes to choose from these are two assumptions. I can define I can get any size of that is any driving capabilities 1 x 2 x 4 x 1 milli amp 4 milli amp 2 milli I can choose the size of the gate which can allow me that currents and I can decide the connection. So, that the path delay can be minimized and this we will choose that two of these. So, that you get the best delay here is a very simple algorithm which I am going to show you which is essentially Tilos algorithm. Why I am showing all this precursor to my logical effort because after all this have been already done and logical efforts actually summarizes in a best way all those theorems methods algorithms which we know into a nutshell which gives you a faster design. So, at the end I am looking for a faster high speed design. So, here is a step one the kind of circuit you are shown here is you have a chain of inverters each has a gate size such that is called minimum gate size which can be minimum driving possibility 1 x 1 x 1 x 1 x. Now, I give an input and I am measure or monitor when the V 0 receives the input and the delay I calculate and that delay I call last delay. That means all of them are 1 x last this is my the this gate I solve the final gate we say is current gate and this earlier gate which is driving this gate is called driving gate. Now, this driving gate and this current gate and these are right now fixed. So, input starts has come here and from here to here for this load of CL I evaluate the time. The time from here to here is fixed for anything any size here as well, but time from here to here will change depending on what what are the gate sizes on this. Then I take another way I say double the size of current gate which means it has the twice the current driving capability this gate can now provide double the current compared to this and it is still driven by the same size old one which is 1 x. Obviously, if I have larger gate sizes larger currents larger currents if this has to prove a larger double the current the size of this transistors here or gates should be sufficiently large enough at least double of that. So, that they can prove you double the current if the sizes on this increases obviously, the capacitance will increase which is the output of this has to now drive larger capacitance. So, then it will get delayed here. So, we calculate we calculate the delay from gate g 3 to g 4 in the 2 a step with 1 x as the driving gate and 2 x as the driven gate or current gate. Now, I repeat the same experiment, but now I say my driving gate is doubled 2 x capacity of driving, but my load current gate which is my final gate to drive the load is has the old value. And I again please remember these are not been changed. So, delay from input coming from anywhere input till this time is same for either case. Now, you have 2 x here and 1 x here in the earlier case 2 a case 1 x here and 2 x here. So, I again monitor the delay coming from here to here in both cases. The first I case gate a case a this one I call 2 x x 1 k I call case b. Then I compare the delays between case a and case b and compare my these new delays 1 x 2 x and 2 x 1 x with all 1 x 1 x 1 x case which is called the last delay. Now, let us say the 1 x 1 x case has certain delay and by making 1 x 2 x I get a delay which is larger than the last delay or lower than last delay. And by same argument if I make 2 x 1 x this kind of 2 statement I also have a gate delay which I will figure out whether it is more or less than last delay. So, whichever circuit a or b gives me lower delay than the last delay I would say I have improved. And this algorithm then tells instead of putting let us say this is better b and I say at least last 2 stages are fixed you make 2 x 1 x as calculations. Now, call this as 1 current gate using this current as a gate I actually now work with this as a driving gate and sorry. So, I say now this becomes current gate and this become driving gate and I repeat this performance once again with these 2. Then next time I figure out now I have standardized this this this for the minimum delay. Then I use this as my current gate and this as my driving gate and keep doing. But I do not tweak with the first gate because this is essentially coming from the first which is a fixed side input buffer. So, which is fixed. So, based on the first one I now know the size of this because of these and these 2 I know the size of this because of this I know the size of this. So, I have now made all possible gate sizing for the minimum delay. To say execution time many times you can have you figure out this is 1 x 2 x this is called window round. So, you have 1 sized gate you now very well know such circuits will give maximum minimum delay here. So, you fix this and never use it never redesign it again. Now, one rule of thumb for delay essentially is the larger output capacitance will be decided by how many fan outs the output has. Typically, it is suggested that at no time the output should drive more than 5 preferably the highest fan out normally can be used is 4 and therefore, it is called a case of f o 4 fan out 4. So, all circuits are actually for a given standard load which is called f o 4. So, the maximum fan out be restricted to 4 and no more less than 5 I would say 4. Then also since the input capacitance changes with the fan ins. So, also you must say number of fan ins should be lower and even in for more sub microns kind of technologies it should be less than 3. Then along a critical path the minimum delay is achieved in each stage by delay is about equal keep rise fall time about equal and then before I quit today for the day I may say before I decide how to go for transistor sizing get sizing I did, but the next part I say is transistor sizing I would like to do it will be great or it will be nice if I do some back of envelope calculations. Now, if I can do transistor sizing and get sizing by very simple calculations which will give faster response to me then I would say I will be saving my effort and we say Sutherland Spal Harris who actually first time talk about the new simple technique based on whatever we are asking in our earlier part that was called as logical effort or logic effort and they wrote such a book which is logic effort designing fast CMOS circuit which introduces this method of logical effort. We will attempt to apply this method during this course to circuits that we look into and we look at static CMOS applications first. Thank you for the day and we will come back tomorrow and continue with this actual working on logical effort. Thanks for the day.