 Welcome to the lecture series on advanced VLSI design, I am covering portion on VLSI testing and today we will cover design for test techniques. In last lecture we discussed about various difficulties in sequential test generation and we discussed that you need to unroll your circuit multiple time frames to generate a test sequence and these. So, now if you look at the source of these difficulties, these difficulties are arising due to poor initializability of the circuit. So, that means here it takes couple of cycles to initialize all the flip loss to some specific state. It has poor controllability and observability of the state variable. So, that means here you cannot directly assign any value to any of the flip loss or you cannot read directly it again take couple of cycles to take out the value from state variable to the primary output. And then as the design is growing the number of gates are increasing, number of flip loss are increasing hence the sequential depth of the circuit is increasing and hence you need to unroll it multiple times, time frames and your test generation would be more and more complex. And if you look at the complexity of the test generation problem in that case you will find that most of the time cycles are main responsible to unroll circuit, multiple time frames hence your circuit would be much more complex than your combination circuit and hence it would be difficult to generate test vectors. If you look at the how difficult these things are like here these are the four different SCAS-89 circuits. So, 1196 has 14 primary inputs, 14 primary output and 18 flip loss and about 529 gates. As 1494 is almost similar kind of circuit which has 8 input, 8 primary input, 19 primary output and only 6 flip flop and about 600 gates. But this is cyclic circuit, this is a cyclic circuit. If you look at the test generation now you can achieve 100 percent fault efficiency for this a cyclic circuit and fault coverage is 99.8. So, that means your remaining faults are redundant faults or identified as redundant fault and it generates 313 test vectors in 10 seconds whereas this circuit has lesser number of flip loss, but this is cyclic and you need about. So, it generates about 559 test vectors and the test generation time is something about 20,000 seconds and still you are not able to achieve 100 percent fault efficiency here it is 93. So, now you can see the huge difference or mastery order of magnitude difference between the test generation time for a cyclic sequential circuit and cyclic sequential circuit. This can give you the fair understanding that if your circuit is cyclic then test generation time is would be huge and this is for the circuit which has only 6 flip flop. In practice we have millions of flip flop you can imagine how much time it will take to generate test. Then here now the question is if it grows like this what is the alternate? How we can this may not be practical if we go for millions of flip flops then what to do with this? And one so now here look at the problems. Problems are due to the poor controllability and poor observability. So, that means here if we can enhance the controllability and observability of the circuit we can make it better testable and hence we can reduce the test generation time and this is coming. So, now here if you look at a sequential circuit if you can look at a sequential circuit it has a combination logic a couple of flip flops. So, now it has some primary input some primary outputs and then here the input which is coming from the flip flop is known as pseudo primary input and input which is going to the flip flop is referred as pseudo primary outputs. Now, if I say that if I can assign any random value in these flip flops in that case my test generation complexity would be almost similar to the this test generation complexity of a combination logic. So, if I can assign any value and if I can read any value from here again here. So, now when you can write any value here you can read any value from these flip flops at any point in time in that case here test generation is as simple as test generation for combination logic. Now, so the question is how I can do that is there any way. So, one of the ways that we can use would be say if I I place one multiplexer here and one extra primary input. So, this primary input say I 1. So, now here whenever I want to I want to load anything here I can control this multiplexer and now using this control I can assign any value here. So, this gives me enhance controllability I can control any value here in flip flop this is. So, that means here I need two additional input, but now here the controllability is not enough I have to enhance the observability as well right. So, now here how I can enhance the observability so, in order to enhance the observability what I need to do is I have to take the output to the primary output. So, now here I need to have additional primary output this is for one flip flop now here for another flip flop I need to have another multiplexer and then one more test control. So, this is I 2 and then again I have to observe this O 2. So, now here what I need is I need three additional primary input output per flip flop. Now, the question is it means is it a practical thing. So, if you have say million flip flops you need to have three million additional primary input output that is impractical. So, now here what is the solution, but we want this kind of functionalities that we can load any flip flop by any random value at any point in time and then we can observe any value which is stored in the flip flop. So, now what is the solution one thing that we can immediately look at is that here when I want to load in one flip flop I can simultaneously load in this another second flip flop hence your test control input here we can share among the flip flop. So, that means here same test control can be used to control all these multiplexers. Now, here I reduce this n number of control signal into single signal, but now here still I need at least two n where n is the number of flip flop in the design to n number of primary input outputs. How I can reduce that number to a reasonable number and one of the simplest approach that we can make use is that we can connect the output of one flip flop as input to the another flip flop in other word what I can say is that here we can change this flip flop like this. If you change the this sorry this is here from here not from here. So, now here I can change this. So, that means here what it will give me it will make a shift register like flip flop two and then flip flop one. So, now if I want to load say value one zero in that case here first I load in the first cycle I load value one that would be storing in flip flop two and then in the next cycle here that value would be transferred here and then the another value I can load here in is one. So, now I can load any arbitrary value one zero and so now this is a shift register. So, whatever value it has that can be scanned out. This approach was first proposed by people from NEC in early 60s and that was published only in Japanese literature. So, it was unknown to rest of the world until late 60s or 70s when IBM came up with the alternate scan architecture. So, and this design is known as scan design. So, now here this gives you flexibility or a way to load any arbitrary value in all the flip flops. So, now here I can change any arbitrary value I can read any value from these flip flops hence here. So, but here what I need at least one additional test control input that is the input that can control all these multiplexers and now here you have to replace all these flip flops by scan flip flop in scan flip flop I mean a flip flop with a multiplexer and now here we make the input output as a scan shift register. So, now when you can arbitrarily load any value and read any value from the flip flop now here you when you need to generate a test vector you need to consider only combinational logic not a sequential logic. Now the test generation problem or in other word the sequential test generation problem is reduced to the combinational test generation problem. So, this is the design of a scan flip flop wherein we use a master slave D flip flop and a multiplexer before that. So, you have the test control input scan data input this D input from the circuit and then this is your clock. So, now here as I said that we need 3 additional signals one is the scan in one is a scan out and another is the test control or a test clock whatever we say. So, now here this signal controls all the multiplexers associated with these flip flops and then this provide you the scan in and scan out provide you the shift path. So, now you can load any value and when you generate the test you need to generate test for the combinational logic. So, now here how you will how you apply test first look at the simple combinational logic how we apply test to a combinational logic. You have a combinational logic you apply a some input and then here you need to apply the value from the state variable. So, that means, here pseudo primary input and then primary input and then every cycle you are getting output then your output may be at the primary output or that may go to the pseudo primary output and you are reading that. So, this way we apply if it happens to be a plain combinational logic, but now it is not a plain combinational logic it has memory elements or pseudo primary inputs and means loading value to pseudo primary inputs takes some time because it is a shift register. So, now here in place of having this vertical S to S 1 now you need to make it horizontal. So, that means, here in couple of cycles you need to scan in the test vector in the flip flops and then in one cycle you apply input from the primary input capture the response and then here you read the test response directly from the primary output of the circuit and then the response stored in the flip flops would be shifted out while you are shifting in the next vector. So, now here you have to shift out the response at the same time you can shift in the next test vector. So, this way you can apply the test. So, now here the question is how many cycles it will take. So, again if I look at this problem say here if your scan chain length is n. So, you need n cycle to load test vectors then in one cycle you have to go in the functional mode that means, you have to change your test control signal from say 1 to 0 0 to 1 and then you capture the test response and you scan out the test response this is for the first vector. For the second vector you have to again is load the test vector go to the functional mode apply primary input and capture the test response and then the captured test response from the flip flops you have to scan out if this way you keep on doing. Now, because this is shift register in that case here you can do this operation in parallel. So, when you are scanning out the test response you have to scan in the test vector for the next test vector. So, now here if there are k vectors you want to scan in, scan in, scan out in that case here how many cycles it will take. It will take the means for all vectors it will take n plus 1 cycle. So, n plus 1 cycle multiplied by k and then here after application of the last vector you have to scan out the response of the last vector. So, this would be n. So, now here your total test time you need is k plus 1 into n where n is the number of flip flops and k is the number of test vectors. So, now here if you look in this expression in that case here this is n combinational logic. So, that means the number of test vectors plus 1 into number of flip flops plus and the number of test vectors this many cycles it will take. So, it will elongate the test time the elongation of test time directly result in to increase in the test cost, but it greatly reduce the test generation effort and that is why though this scan design was proposed in way back in 60s till date it is surviving. So, almost all the industries are using the the full scan design wherein all the flip flops are converted into scan flip flop and then you apply test by loading that the test pattern in sequential fashion. So, now here the other thing that we have to take into account this way if you generate test for the combinational logic you can detect all the faults in the combinational logic, but what if the flip flop itself is a faulty circuit. So, if it is itself is a faulty circuit you have to test that as well. Now, since flip flop is a memory element it does a limited function hence in place of having fault model like stuck at kind of fault model we can use the functional fault model for this and functional fault model is like it should either restore 0 or restore 1. So, that means here we have to check whether it stores 0 or restores 1 or whether it provide you transition from 0 to 1 or 1 to 0. So, if I scan a sequence of 0 0 1 1 0 0 1 1 all through all the flip flops in that case here I can say that here means if I get out the same sequence from the scan chain I can say that it stores 0 it stores 1 and it also allows transition from 0 to 1 and 1 to 0. Otherwise if assume 1 flip flop is cannot store 1 that stores permanently 0 in that case after a while all the bit will be 1 because here the entire bit is stream is going through that particular flip flop and after a while you will get all bit as 0. So, that means here that scan chain itself is faulty. So, in order to make sure you have to scan through a bit stream of 0 0 1 1 and it will take the number of flip flop plus 4 number of cycles. So, first you have to scan through a bit sequence of 0 0 1 1 that is also known as the sanity check of scan chain. Once it is done you can apply your test vector. So, now here the number of scan chain plus 4 number of test vector you are applying from here and then as we discussed earlier that in order to apply the test vector you need these many cycles. So, now here the total number of cycles it needs is the total number of test vectors plus 2 into multiplied by the number of flip flops plus test vector plus 4. So, these are the total number of clock periods you need. So, like here for example, if you have a scan chain of 2000 flip flop and you want to apply 500 combinational vectors if it happens to be only combinational logic you need 500 cycles. If it is a sequential circuit and you generate test using the sequential logic and assume that say every vector may need a sequence of 4 every fault may need a sequence of 4 vectors may be you may need 500 2000 vectors and then it may need 2000 cycles. Whereas, if it is a scan design in that case you can put this value 2500 in this formula you will get roughly about a million cycles. So, you can see the impact in terms of test time. So, this will increase the test time, but it helps you greatly in reducing the test generation effort otherwise test generation may not be possible for a fairly large industrial design or if it is possible it may take enormously long time that may not be affordable. Now, the question is so, if you look at the various overheads then it comes with following overheads like you need a multiplexer with a single every flip flop. So, that result into additional area you need to have a test control signal routed all through the chip. So, that routing area overhead is also there then because you are placing a multiplexer in the functional path. Hence, it will result into additional delay hence your circuit may operate slow. So, it has performance penalty then it should have three additional pins one is a scan in scan out and test control. And fourth is and now here because of the sequential loading of a scan pattern it takes longer time. Now as I said that here for a small circuit which has about 2000 flip flop and 500 test vectors it take about a million cycle. Now what are the ways to reduce this time because this directly result into additional test cost. So, one of the way that we can think of is you have very long scan chain I can break that scan chain in multiple scan chains. So, like here say these 2000 flip flop in one scan chain I can chop off in say 10 scan chains and every scan chain will have now 200 flip flop and I can load these 10 scan chains in parallel. So, but for that I need 10 additional primary inputs and 10 additional primary outputs. So, that means here in all I may need 21 additional input output pins that we may not have. So, what then what is the solution? One of the solution could be because when we are loading the scan pattern in the scan chain we are not using primary input and primary output. So, what we can do is we can you multiplex these scan input and primary input and we can reduce this requirement. So, that means here by multiplexing we really need one additional pin and that is your test control that can control all these multiplexers associated with the flip flops. So, now here whenever you are in the test mode it would not take input from the combinational logic or from the primary input and when it is in the functional mode it would not shift the value from one flip flop to another flip flop. So, now here that can solve our problem up to certain extent we can reduce. Then here the question is how many scan chain I can afford to and the answer of that is max of number of inputs and number of outputs because here for every scan chain I need to have one input and one output. So, say your circuit may have 10 input and 8 output in that case here maximum I can have 8 parallel scan chains. So, that and that directly reduces test time by 8 times. So, if you look at the effort in that case here say you have circuit which has number of gates about 3000 and number of flip flop about 179 and so if you use the sequential test generation in that case you may achieve something like 70 percent fault efficiency in about 5000 and 100 seconds. Whereas, if you cannot or flip flop into scan flip flop in that case here you need to generate test for combinational logic and it will take it can achieve 100 percent fault efficiency in 5 seconds. But now if you look at the test application here if you generate this test vector by using the sequential ATPG in that case you may generate say 400 fault in test vectors and in order to apply this you need 400 fault in cycles only. Whereas, here you generate 585 test vectors and in order to apply that you need about one like cycles and so now you can see the overhead in terms of time and this is recurring cost. But as I mentioned you earlier that this can greatly help you the test generation. Here again we cannot directly compare the this time this is almost 3 order of magnitude higher than this time, but if you look at the fault efficiency here we achieved 100 percent efficiency here the fault efficiency is 70 percent only. If you go to 200 percent in that case here this time will exponentially grow and then this may go unreasonably large number or impractical. So, now in general the scan design flow is more or less automated today. So, when you start your design flow from RTL you synthesize your circuit to gate level net list. Once you have gate level net list in that case here there are two things you have to do. One thing is because you have gate level net list you have combinational logic in this you start to generate the test vector from the combinational logic. At the same time here you can insert the scan chain. So, insert scan chain mean here you have to convert all flip flop into scan flip flop and then you have to stitch these scan flip flop in a shift register. So, now here once you have shift register in that case here you know the layout of the chip and you know that how these flip flops are connected. Based on that here you have to generate the test sequence. So, the test sequence is generated and now here the mask and the test program you have to send to the FAP wherein they apply that. So, now when you have the gate level net list it has to follow certain rule in order to insert the scan cell in the circuit. So, what are those rules and which this need to follow? So, some of the rules are like here we have to use only clocked D type flip flop. We discourage to use any other type of the flip flop like SR flip flop, JK flip flop, T flip flop. So, now practically all the circuits are built or designed using clocked D type flip flop. At least you should have one primary input pin available for the test that is the test control pin which is used to control the multiplexers associated with these D flip flops. And third thing is that all clock must be controlled from the primary input. So, that means here the clock should not be gated clock should come from or are controlled by primary inputs only and clock must not feed data input to the flip flops. So, these are some of the design rules you have to follow if you want to insert scan. So, that means here once it is followed you can directly replace the flip flop by scan flip flop that means here flip flop with a multiplexer. So, like here for example, if this is the circuit wherein you have one flip flop and then the clock is gated. So, and sometimes it is very easy to design this kind of gated clock circuit. So, now here clock will depend on the clock and the D input. So, that means here whenever the input is high and clock is high it allows the value to change in this flip flop. Now, when I do not want this or we do not allow gated clock what we need to do we have to convert this gated clock input into non-gated clock input. So, now here the same functionality we can achieve by this circuit. So, you have to convert if your circuit is designed by like this you have to transform your circuit into convert your circuit into this design wherein the clock is clean that is controlled by primary input that is not controlled by the data input. Sometimes though here this is means it is discouraged to use the gated clock, but sometimes in order to optimize your circuit you feel it is better to do the clock gating rather than doing any other optimizing using any other way. So, one must be careful means while you are designing if you want to go for this scan design. Now, here as I said that scan design comes with some of the things that you can do the overhead those are like here additional area, additional performance penalty, then additional pins, but it reduces test generation time and test generation effort significantly. So, this was wonderful technique which was ever proposed in VLSI test and that is why it is surviving for last 5 decades. So, but there is a famous caught by George Bernard So, which says that science is always wrong it never solves a problem without creating 10 more and scan design is not an exception to this. This solves a very important problem of sequence test generation, but it creates some additional problems and then we have to solve those problems. In some sense it is it gives you some additional problems to solve. So, now here what are those additional problems we may have? So, one of the problem that I mentioned you earlier is that here your test application time will significantly increase and it will directly translate to the test cost. Another problem is test data volume. What does this mean? Like here if you apply sequential test in that case here you need to store only a few vectors and then you have to apply those from the primary input and number of primary inputs are pretty small. So, say you have 10 inputs and there are 100 test vector you want to apply. So, in that case here you may need to store only 100 bits. Now, assume that you have 10 inputs and you have 1000 scan sets and you may want to apply 100 inputs. So, now here how many bits you want to store you may need to or you must store 1000 plus 10 input per vector. So, that means here it is the number of bits that you may need to store would be 100 multiplied by 1000 plus 10. So, you may need to store now here almost 1000 times additional test vectors that needs the memory on the tester. In the same way you also need the golden response. From the primary output as well as the values in the flip-flops. So, now here your test data as well as golden response will also increase several order of magnitude and assume you have a circuit with millions of flip-flops and millions of several millions of test vector you need enormous use memory. So, that means the storage of that test data is also a problem. So, that is additional problem that we have. The very important problem nowadays is the test power which was not there earlier. Though here the test data volume was also not very big problem initially because at the time the circuit complexity was not that much nor the circuit was too small. Now, here what is the source of test power? So, say you may need easily you may generate a test vector wherein you may need to load a test data like here 101010 sequence because this sequence you are generating from the combination logic. Now, when you load the sequence in flip-flops what will happen? Because there are different adjacent bits. So, in every cycle when these bits will shift every flip-flop will toggle and that. So, that means here large number of switching will happen in the flip-flops and these switching will also reflect in the combinational logic and see this happens only in the test mode because here in functional mode you may not need to shift this test vector but because here in the test mode I want to load these bits in the sequential shift fashion here it creates switching in all flip-flops in all the cycles and that switching also reflects to the combinational logic. Combinational logic will also switch and now here the total power that would be dissipated during this period may go very high and practical observation says that in some of the cases peak the average power can go 3 to 4 times than the normal power and peak power may go 30 times than the normal power. What are the implications of this? If test if average power exceeds beyond a limit then your chip may burn out. So, that means here you may damage a good chip and that will result into yield loss because of your bad test methodology. If peak power exceeds beyond certain limit your circuit will start to draw large current all of sudden from your power grid. Power grid may not support that and hence there would be a drop in VDD. If there is a drop in VDD then transistors will start to switch slower. Hence your response may not be able to propagate or the effect of application of one test vector may not be able to propagate to the output within the given clock period and hence here you may classify your good chip as bad chip because you will receive a random response out. So, again here it will lead to the yield loss. So, these are the important problems that those appeared in or post 2000. So, now here there must be some solutions to these problems if you want to continue with the serial scan. These problems appear due to serial scan shift nature of the test vector. So, now here what are the solutions? I may describe couple of solutions in brief. You can look at literature there is a large body of literature available targeting these problems. So, like here the sum of the efforts which are being made like one of the effort is while you are generating the test you have to you can generate test because as we discussed earlier that one fault may have multiple tests. So, you can select a test which can dissipate less power and when you are generating test it generates large number of access. So, that means here the propagation of fault effect is not impacted by those primary inputs. So, now here you primary inputs or pseudo primary inputs. So, now you can fill these access by any value and typically people use three approaches. One is all access are filled by zeros or all access are filled by ones or all access are access are filled by looking at the adjacent specified bit. If it is 0 in that case it should be filled by 0, if it is 1 in that case it should be filled by 1 that is known as minimum transition. So, you want to reduce the transition. So, there are couple of approaches. So, now here if you want to select a test vector that can consume or dissipate lesser power in that means it has to create lesser transitions or activity in the circuit. If it creates lesser activity in that case here that may not able to detect multiple faults. Hence, you may need large number of more number of test vectors. Hence, this can solve your problem of test power, test power can be reduced, but here test length will increase. Other thing possibility is you when you are scanning in you can reduce the test clock. So, that means here you can operate your circuit slower. Hence, you can reduce the average power. In practice scan shift operation happens almost 5 times slower than the rated clock frequency. So, now here you can reduce the test power, but now when you reduce the clock frequency in that case your test application time will increase. Hence, your test cost will increase. The other way is like here you can reorder the scan chain and reordering mean here say if you want to scan in the pattern 101010 and so now here you have to have you have 1 in flip flop 1, 0 in flip flop 2, 1 in flip flop 3, 0 in flip flop 4, 1 in 5, 0 in 6. If I can stitch this can chain in different way like here 1, 3, 5, 2, 4, 6 in that case here how I need to scan in I need to scan in 11000 and hence I can reduce the number of transitions because now in every cycle there would be only one transition here. So, this can reduce the test power and test time, but here now you need to modify the scan is teaching and that is needs some design effort and hence design time will increase. Then in order to reduce the test time or test data size here you can do the compression at the primary input and at the primary output. Compaction or compression is the widely used technique, but here it again it has limited capability. So, these are some of the effort which were proposed by people to take care of the additional problems which are coming from the serial scan design. There is an alternate approach that we can get away from the serial scan and then now in place of serial scan we can have random access scan like we have random access memory. So, that means, we can load or unload any flip flop whenever we want we do not need to serial shift everything that can also help you in targeting all these three additional problems. You can look at various papers published for random access scan. So, here I complete the scan design portion. I discussed about why we need scan design and what are the advantages of scan design and what are the overheads it comes with, what benefit it gives you and what are the additional problems we are getting due to serial scan in current designs and what are the various solutions we have. So, in nutshell I can say that here if we have serial scan design we can convert every flip flop into a scan flip flop and then we can go to ATPG generate test using a combinational ATPC and then we can apply the test. But you need an expensive tester to apply these test vectors and you can test these chips just after manufacturing or in the so at the fab house or in the design house if you have expensive tester. Some of the devices are very safety critical devices and you would like to monitor the health of those devices while they are operating in the field as well. So, that cannot be done if you are testing by the chip using external very expensive testing test equipment. If it happens to be a small equipment or very inexpensive equipment you can still test it. So, now if you want to build capability of field test you have to think about some other alternate that is one of the problems. Second as I said that here it has some cost implication in terms of like you put when you put your chip on tester it cost you somewhere 5 to 10 cents per second. So, it is expensive then it was thought that can we build a test capability in chip itself. So, that means is it possible that chip can test itself that can help you in testing your chip at the speed. So, that means here you do not need to slow shift your test vector apply the test in the functional mode and scan out the response that can also give you the flexibility to diagnose your chip and so that technique is known as built in self test. It may not sound well if you say that chip test itself so that means here I need to have all these kind of test resources on chip that means here you have to have a test generator on the chip you have to have a test response collector on the chip you have to have some mechanism that can check with the golden reference the collected reference and collected response and then make a decision whether chip is good or bad. But as I said that here a field test is important for some of the devices like here nowadays when you power on your laptop it generally do some kind of self test for the memory for the sometimes for the processor as well. So, in order to monitor the health of your system whether it is good. Generally, for the diagnosis here we use the software test, but if you use the software test in that case here the hardware fault coverage is pretty low that may be something like here 20-30 percent after application of large number of hardware test vector like here you boot the operating system or you run some application on that. Diagnostic resolution is also very low it is very slow process. So, that means here if you use the hardware built-in self test in that case here you may have lower system test effort you can use that the same built-in self test after manufacturing and then in the field it can improve the system maintenance and repair it can improve the component repair and then it gives you the better diagnosability. It also alleviates some of the test problems which are coming from the expensive testers. So, some of the problems are like here in today's design the logic to pin ratio is very large. So, that means here you have large logic and then there are only few pins. So, the pins are not increasing as per Moore's law and but here logic is doubling almost every 18 months. So, now here it is very hard to observe some internal point. So, observability is very difficult then the density of the device is increasing and then here clock is becoming faster and the test application time because the number of leaf loss are increasing then the test application time is increasing the number of test vectors are increasing and like here Moore's law the test vectors are increasing every means doubling almost every 13 to 16 months and you need to expensive test vector and then here it is very hard to insert some test points in the circuit because here this may impact the timing of the circuit. Of course, here industry faces the short test of test engineer. So, that is why also we need built in self test kind of test mechanism. Other thing is like here for the design point of view it is easy to parties in the circuit and do design in parallel, but here it is very extremely difficult to parties in the circuit for the test point of view. So, these are some of the problems which are being which are elevated by built in self test. So, now here built in self test means chip is supposed to test itself. So, that means here you need to have a hardware patent generator you need to have a response analyzer or compactor that can compact collect the response compare with the golden response and say go no go and then here in order to control all these activities here you must have a test controller that can control. That means here that can excite the test pattern and generator and analyzer at different point in time and then here you need to have some methodology to test that built in self test hardware. It also comes with some pin overhead. So, that means here at least you must have one additional pin that can say you that here now it is the time for built in self test. So, now you have to run the test. So, you need additional pin for that because here we are inserting additional hardware for the test pattern generator and analyzer and then test controller in that case here some of the additional gates may be inserted in some critical path and due to that here performance may reduce. Because we are putting additional infrastructure in the circuit then the area will increase if area increases in that case here the number of force may likely to increase hence the yield may be low. And then because of the additional area the reliability of the system also reduces. So, now and then here the built in self test hardware complexity will also increase when you want to make that additional circuit as a testable. So, now here if you look at what kind of force your built in self test can detect. These are like here all single force in the single stuck at fault in the combinational or sequential circuit all the delay force single stuck at fault in the built in self test hardware or architecture. What are the benefits of this? It reduces the maintenance cost it generate the test at lower cost it reduces the storage or maintenance of test vector. It is simpler and less expensive automatic test equipment is needed because here you need to say only that here now you start the test and now you stop the test that is it. It can test as many units in as a possible in parallel because now you need a very small board that can tell it tell a chip that now you should start to test the chip and these are very inexpensive board. So, you can test large number of chips in parallel and so now here the test application time would be shorter and now here you can apply test at the circuit speeds in that case here at speed test is enabled. So, if you look at the built in self test architecture what you need? You need a hardware pattern generator you need hardware response analyzer. You need to have some place where you store or the golden reference input and then you have to compare the need to have a comparator that can compare your collected response with the golden response and it will say that chip is good or chip is bad. Now, here and this is your circuit under test. So, now where you need to apply the test? You need to apply the test at the primary input. So, that means here you have to multiplex the output of hardware pattern generator with the primary inputs and you have to take output from the primary output of the circuit and in order to do all these things you need to have a test controller that can generate the control signal for all the test pattern. So, now here this approach can test all these all the faults which are in the circuit under test all the faults which are in the built in self test structure except where the faults which are presented at the primary input of this multiplexer because here when you are testing your chip you are not exercising this path and primary output. So, now here if there is a open in that case here you may not be able to exercise that and you may not be able to test. So, these are the faults which may remain uncovered if you use built in self test. So, now describing this built in self test I stop here today we will continue with the various components of built in self test in the next lecture. Thank you very much for patience full listening good day.