 Welcome to the session on SR flip-flop in sequential logic circuit. At the end of this session students will be able to explain the operation of SR flip-flops. Let us see what is sequential logic circuit. Sequential logic circuit output depends not only on current input but also on past input values. If you need some type of memory to remember the past input values, combinational logic circuit are memory-less digital logic circuits whose output at any instant in time depends only on the combination of its inputs. This means the sequential logic circuit are able to take into account their previous input state as well as those actually present with sequential circuit. Here flip-flop is a memory device that has clock signals control the state of the device. Simple sequential logic circuit can be constructed from standard bistable circuits which themselves can be made by simply connecting together universal NAND gates or NOR gates in a particular combinational way to produce the required circuit. And the flip-flop is a memory element which is capable of storing one bit of binary information and it is used in clocked sequential circuits. It has two outputs one is normal and another is complement of the first. One bit memory cell is also called as basic bistable element. It has two cross-coupled inverters, two outputs Q and Q bar. It is called bistable as the basic bistable element circuit has two stable states. One is logic 0 and another is logic 1. Output of G1 is connected to the G2 and output of G2 is connected to the G1. In the output of G1 that is Q equals to 1, hence output of G2 that is Q complement equals to 0, this makes Q continuous to be 1. The circuit shown here the NAND gate G1 has at least one of its input at logic 0 therefore its output Q must be at logic level 1 as per NAND gate principles therefore such a flip-flop circuit is called as Z state. Similarly, if we start with Q equals to 0, G2 that is Q complement equals to 1 and this makes Q complements continuous to be 1 and Q equals to 0 therefore such flip-flop circuit is said to be reset. Here a concise memory of 1-bit memory cell, the two outputs are always complementary. The circuit has two stable states, one corresponds to Q equals to 1 and Q complements equals to 0 and it is called as Z state whereas other corresponds to Q equals to 0 and Q complements equals to 1 and it is called as reset state. The circuit can store one-bit of digital information and so it is called one-bit memory cell and the one-bit information stored in the circuit is locked. This circuit is also called latch. Here cross coupled inverter is capable of locking or latching the information but the disadvantage is that we cannot enter the desired digital data into it. This disadvantage can be overcome by modifying the circuit as the SR flip-flop is therefore a simple one-bit memory. As in SR flip-flop, the input of S equals to 0 and R equals to 1. This makes Q to be 0 therefore the flip-flop circuit is said to be reset. If the S input is taken to a logic 1 input then back to a logic 1, any further logic 0 pulses at S will have no effect on the output. And the timing of the circuit or the output changes after a change of logic state at S and R can be controlled by applying a logic 1 pulse to the clock input. So the operation of the basic flip-flop can be modified by including an additional input clock to control the behavior of the circuit. And the clock input is that the output of this flip-flop can now be synchronized with many other circuits or devices that share the same clock. In the following circuit, if Q equals to 0 and Q complement equals to 1, the output is said to be, here the choices are given, pause your video and write the answer. So your answer is B, if Q equals to 0 and Q complement equals to 1, the output is said to be reset. In clocked SR flip-flop, if input of S equals to 0 and R equals to 1, in the second stable state into table as gate G2 has one of its input at logic 0, its output Q complement must equal logic level 1 as per the NAND gate principles and the output Q complement is feedback to the input G1, therefore Q equals to 0 and the output of such a flip-flop will not change as it is in logic 0 state. If the input S is at logic level 1 and the input R is at logic level 0, the G1 has at least one of its input at logic 0, therefore its output Q must be at logic level 1 and the output of flip-flop does not change as it is already in set state. Output Q is also feedback to input G2 and so both inputs to G2 are at logic level 1 and therefore output Q complement must be at logic level 0. Now this condition showed that for input signals S equals to R equals to 0, the output state of S and R flip-flop remains the same that is Q and Q complement equals to 0. The above case has showed that for an input signal S equals to R equals to 0, the output state of S or flip-flop remains the same that is called no change state. It can be seen that when both inputs S equals to 1 and R equals to 1, the output Q and Q complement can be at either logic level 1 or 0 depending upon the state of the input S or R before this input condition existed. Therefore the condition of S equals to R equals to 1 does not change the state of the output Q and Q complement. This is an invalid state and they are supposed to be complements of each other and normally this state must be avoided. Figure shows the logic symbol of SR flip-flop. The flip-flop has three inputs S, R and C. The set S and reset R specifies the internal logic states of SR flip-flop. The outputs are denoted by Q. The SR flip-flop can also have a complementary output represented at other output terminal. They can set or reset the flip-flop regardless of the status of the clock signal. Typically they are called preset and clear. When the preset input is activated the flip-flop will be set Q equals to 1 not Q equals to 0. So regardless of any of the synchronous input or of the clock. When the clear input is activated the flip-flop will be reset regardless of any of the synchronous input or the clock. Applications of SR flip-flop. SR flip-flop is used in the digital logic circuit for the switch or the circuit breaker to hold the closed state. Even the input controller signal disappears. As a digital latching relay it can be used. As a switching mechanism for alarm circuit this is when an alarm is pressed it will not get reset until the reset button is pressed. So these are my references. Thank you.