 Hello, and welcome to this presentation of the STM32F7 analog-to-digital converter block. It will cover the main features of this block, which is used to convert the external analog voltage-like sensor outputs to digital values for further processing in the digital domain. The analog-to-digital converters inside STM32 products allow the microcontroller to accept an analog signal, like a sensor output, and convert the signal into the digital domain. There are 16 to 24 analog inputs available across the three ADCs. The ADC module itself is a 12-bit successive approximation converter. The sampling speed is two mega-samples per second. Each ADC module integrates an analog watchdog. The data can be made available either through DMA movement or interrupts. There are a number of triggering mechanisms and the data management can be configured to minimize the CPU workload. Three analog-to-digital converters are integrated inside STM32F7 products. The input channel is connected to up to 24 GPIO channels capable of converting signals in either single end or differential mode. The ADCs can convert signals in excess of five mega-samples per second. There are several functional modes, which will be explained later. There are also several different triggering methods. In order to offload the CPU, the ADC has an analog watchdog for monitoring thresholds. This slide shows the general block diagram for the three analog-to-digital converters embedded in the STM32F7. The ADC supports up to 2.4 mega-samples per second of conversion. By using triple interleaved mode, it can be extended to 7.2 mega-samples per second. The sequencer allows the user to convert up to 16 channels in any desired order. Also, each channel can have a different sampling period. The ADC offers an auto-calibration mechanism. It is recommended to run the calibration on the application if the reference voltage changes more than 10%, so this would include emerging from reset or from a low power state where the analog voltage supply has been removed and re-established. The ADC needs a minimum of 3 clock cycles for the sampling and 12 clock cycles for the conversion. With a 36 MHz ADC clock, it can achieve 2.4 mega-samples per second. For higher speed sampling, it is possible to reduce the resolution down to 6 bits, then the sampling speed can go up to 4 mega-samples per second. The sampling time can be programmed individually for each input channel of the analog to digital converters. The sampling times listed in this slide in ADC clock cycles are available. Longer sample times ensure that signals having a higher impedance are correctly converted. The ADC has 2 clock domains, one for the interface and another for the analog core. The analog clock input has a pre-scaler to select the clock speed. The ADC supports several conversion modes, single mode, which converts only one channel in single shot or continuous mode. Scan mode, which converts a complete set of predefined programmed input channels in single shot or continuous mode. And discontinuous mode converts only a single channel at each trigger signal from the list of predefined programmed channel inputs. Each ADC has an integrated analog watchdog with high and low threshold settings. The ADC conversion value is compared to this threshold window. If the result exceeds the threshold, an interrupt or external signal can be generated or a timer can be immediately stopped without CPU intervention. In normal scan conversion mode, the conversion is repeated for all channels one by one. If an injected conversion is started, the ADC stops converting the normal conversion channels and proceeds to convert the injected configured channel. At the end of all injected channel conversions, the ADC resumes the conversion from the channel where the normal conversion was stopped. When the trigger occurs, the regular conversion needs to be finished before the ADC proceeds to the injected conversion. The ADC conversion result is stored in a 16-bit data register. The system can use CPU polling, interrupts or DMA to make use of the converted data. An overrun flag can be generated if data is not read before the next converted data is ready. For injected channel conversions, four dedicated data registers are available. An injected conversion is used to interrupt the regular conversion, then insert up to four channel conversions. Once an injected conversion is finished, the regular conversion sequence can be resumed. The injected conversion result is stored in dedicated data registers. Flags and interrupts are available for the end of conversion or end of sequence. The choices for an injected channel can be reprogrammed on the fly. Even if a regular or injected conversion is in progress, you can add a different channel to the queue so that the next injected channel can be different from the previous one. Each ADC can generate four different interrupts. End of conversion, end of injected conversion, analog watchdog and data overrun. DMA requests can be generated at each end of the conversion when the ADC output data is ready. The ADCs are active in run and sleep modes. In stop mode, the ADCs are not available, but the contents of their registers are kept. In standby mode, the ADCs are powered down and must be reinitialized when returning to a higher power state. There is a deep power down mode in each ADC itself which reduces leakage by turning off an on-chip power switch. This is the recommended mode whenever an ADC is not used. The following table shows performance parameters for the ADC. The STM32F7 embeds three ADCs. ADC1, ADC2 and ADC3 can be configured to work together in dual or triple mode so that each analog to digital conversion can be synchronized between the two or three modules. These peripherals may need to be specifically configured for correct use with the ADCs. Please refer to the corresponding peripheral training modules for more information. Several application notes dedicated to analog to digital converters are available. To learn more about ADCs, you can visit a wide range of web pages discussing successive approximation analog to digital converters.