 can start after let us say 20 seconds. Hello everyone, welcome to the first lecture of unit 3. During this the next hour I will introduce the concept of synthesis I will start with the very very basic what is synthesis what does the process do, what does it need and most importantly where does the process of synthesis fits in the ASIC design code, you would also look at the design compiler family comes in office which I believe all of you would be using in your project works and assignment and further when you go into the industry and also design compiler is in fact the most popular tool of choice for synthesis. There are other tools also like hidden shuttle compiler there is magma, but we will focus are all the commands we discuss all the scripts will be focused to synopsis design compiler. However, it should not be a major problem in switching to a different tool if you want to with the need arises because the concepts remain same only few commands are different from one to other otherwise everything is remain same. So what is synthesis, synthesis by definition means combining three existing elements to form something or in other words you can also say that synthesis is nothing but conversion of an idea into implementation. We introduce one more thing called logic synthesis again logic synthesis is combining primitive logic function to form a design at least that means a function in design code. So here on the left hand side we see a jigsaw puzzle which is jumbled up each of the component is labeled as TP, TP means a technology primitive this could be there be a RTL retention there will be a BL and then we want that there will be a BL to be converted into a gate level net list which would again be sent to fabrication and this process of conversion is called synthesis. Obviously, it should meet some of the goals for example, let us say we are working on a processor from Intel. Now that processor each processor from any any company will have some frequency goal let us say the goal is it should meet 1 gigahertz so that is our goal. So whatever design we do whatever technology node we choose we have to make sure that the processor meets the criteria of 1 gigahertz frequency. So that is an example of a goal the output is net list less a lot of other files which go to physical design tools and then layout is done they are they are sent to function. The concept of automated design is theoretically it is possible to convert any digital function to a logic circuit this is what is done by the synthesis tool it automatically synthesizes circuit from function description. For example, on the left hand side you have a logic function that is equal to A or B and C or D and E. Now this is a this is this statement on the left hand side is written into a high level language it could be the end of a BLB. So the tool will read this and it will convert this to something represented by the right hand side which is a logic circuit. This is a very simple simplistic explanation of the process. Now we have we are assuming some things here one thing we are assuming is that the standard cells that is the cells the logics like in the previous example the OR gates the 2 OR gates and the 3 input language they are assuming their existence. So if primitive standard cells are previously designed we are assuming that these cells are previously designed that is we have a library which contains all these cells and we have the functional description of the cells we have the timing specifications of the cells we have the layout of the cells that means everything is already designed we could build a large number of various digital circuits using these parts. So the group of primitive cells which are used to build larger circuits is called standard cell library. Now building a standard cell library is a completely independent subject on its own it involves a lot of size analysis layout and all that. So during this course and during your project work and assignment we will be assuming that we have a library of standard cells available with us and we will simply use that library to create circuits of choice for an application. In the next lecture we will actually spend a lot of time on understanding how the standard cell library data is represented what files do we need what do those files contain. So we will see a lot of that but we will assume that everything is available for us just have to start on the design. Now synopsis has a library available for university students it is a 90 nanometer generic library which can be used for project work and assignment. Now why synthesis why can't we start with why can't we hope that is the assume you have to design a decoder that is a three to a decoder what we saw in the example of that. And now there can be two approaches first approach can be that I I know what a decoder looks like what the logic circuit looks like I can draw it on paper then I can go to the library and choose the cells the software itself hook them up from the netlist myself and then proceed through the physical design process. Second approach which is a high level approach I would what I would do I would write an HDL which is I would write an HDL and in well log let us say in well log I write something like this for the decoder. I use synthesis to convert this into a netlist into a gate lemon netlist and then again proceed for for physical design. This is possible only for very small design or very specific design or some very special circuits where you do not want the regular digital designs in the display you will find that not useful but otherwise for all the big design huge designs big chips obviously drawing circuit by hand is not at all possible plus the tools nowadays are very sophisticated in terms of that they can choose what best cell what cell would suit best for let us say different type of code or let us say you want a lower area. So, it could choose a different cell when compared to when you want a faster circuit and the complexity keeps on increasing as you go one level down. So, an HDL for a we will have let us say for a full chip an HDL will have a few hundred files with some thousands of lines of code and then when it goes through gate level it expands into a million gates which are hooked up together again and it goes to now since gate level database is not the one that is manufactured it we convert this gate level data base into a transistor there is schematic using physical design tools and then this again the each gate will have a let us say n number of cells we saw that a two input can get is comprised of four CMOS of two NMOS S2PMOS that means four transistor. So, similarly let us say you have a one million design gate gate level network it will it will translate easily into a five to six million transistor count again this transistor count is then converted into polygons which is nothing but layout. So, layout we also call them as polygons because ultimately they are just a bunch of rectangles squares different type of polygons which represent different layers of the chip. So, some polygons should represent the metal layer some will represent the poly layer and so on. So, as we go down the hierarchy as in so the number of elements increases exponentially the complexity also increases and dealing with a higher complex very complex design in the sense of let us say if you are working on gate level at least that will take more effort time and cost when compared to working on a HDL. We will see that the difference is that is there any need when we need to work on a gate level network yes there is a need when sometimes we need to work on gate level network, but most of the time for our course purpose of our course we will start with an HDL almost always we will start with a very long of VLHD and description of a design and then proceed for synthesis. I would also assume that almost all of you should be familiar with Berlop we will whatever code we see here will be Berlop because it is the most popular language of the right now and presently. There are the HDL users also but I would restrict my slides of codes to Berlop. So, if somebody is not familiar with Berlop I would suggest that the reader Berlop sort of to start with it you could start in a two or three days you could read about and start coding sort of this problem and then you come back to this lecture so that you can understand it better not this lecture are in particular, but all the coming lectures this discussion. Now logic synthesis is divided into three parts the first part is called translation second part is called mapping and the last part is called optimizing the first part the translation is the is the name given to the process of converting the HDL description into something called a GTEC netlist. So, GTEC is a term specific to synopsis GTEC means generic boolean. So, now let us say so the hardware description language the Berlop code on the different side this code here would be the pricing of a higher level language comes up if else case statements always locked and so on. So, this HDL here the art here is actually technology independent that means it does not matter what technology mode we are targeting for the RTL does not need to represent that when I talk about I mean let us say we are targeting is a 90 nanometer or 65 nanometer where the the nanometer length is the the transfer channel length. So, each technology mode mode for example, a 90 nanometer technology mode that are spawns to the manufacturing process where the channel length of NMOS and PMOS is 90 nanometer. So, when we start when we go for to decide deciding a chip deciding a then then we have to choose a technology mode, but when we write the RTL when we write a higher level description language the design is technology independent. When it goes through translation it gets converted into something called GTEC netlist the generic boolean netlist and this netlist also is technology independent that means still the process of translation still the still this this generic boolean we are not concerned about what technology we are going to get a design manufactured in. Right now we are only concerned about the logic that is it is limited by the RTL the second process the second part of the process is mapping. Mapping is the process where design compiler will map the GTEC boolean into the gates available in your library here is where the technology comes in. So, let us say I am targeting a product for a 90 nanometer technology I would have a 90 nanometer standard cell library listening. Now that standard cell library will contain lot of cells different types of hands or man or inverter purpose and so on and now the generic boolean will be mapped into this gate level netlist and the last part which is the optimization will make sure that all the goals that we have specified in terms of performance linear and power and method. Now let us say the same design I want to I have manufactured in 90 nanometer now I want to go to 65 nanometer. The first part that is foundation will remain same it will not change because the generic boolean is not changing it is same the destructive of technology it is simply a collection of gates that design compiler the gates that are available in design compiler they are not linked to any technology they are generic. So, the first process will not change the second process will change because the 65 nanometer library would be different from 90 nanometer library and because the second part is changing the mapping part is changing the optimization will also change because now although the goals might be same, but the underlying cells are different. So, the optimization of that part would be optimization carried out by design compiler on a 65 nanometer design will can be and will be different from the one in 99 nanometer. Now first we start with the functional distribution it is written in a hybrid decision language that we also call it RTL register transfer level most of the designs which will practice hands-on will be synchronous. Synchronous means there will be a clock all the handshake between different parts of the design will be based on a clock signal the very big advantage of a synchronous design is that it I will be this thing is very very important simplify time verification we will see that in further in unit 3 and unit 4 what do we mean by this it simplifies optimization algorithms again this is again a derivative of this part and simplify time timing verification optimal results it is very easy to set goals for a synchronous design as compared to an asynchronous design. A synchronous design is very very difficult to verify and to meet time. So, it is recommended that whatever design problem we have we try to solve it in the synchronous domain and so that goal setting and optimization would be easy again the way we code RTL it affects the results we will see that the coming slide how do we write better codes and how do we make sure that this one very very famous saying is that when we write RTL we should think in terms of hardware not in terms of software that is let us say we are writing a case statement we should think that what that case statement will transit into after simplify what type of hardware will it consume. So, a lot of the area of the design performance of the design a lot depends on how do we write the code. So, the process of translation now we see in detail the process of translation will cover all these things it will do sgl syntax and rule check it will optimize sgl we will see we will see few reports how does it do that it will map arithmetic functions for example, let us say you are writing a plus b you are writing c is equal to a plus b. So, that plus looks very simple in the law, but that plus translates to an adder in hardware that adder would be mapped to a g-tech adder a generic boolean adder this is what is meant by arithmetic function mapping. Sequential function mapping whenever you have always lost that represents a flip flop or a latch that particular register will be mapped to a generic flip flop or a generic latch then there will be combination function mapping that is mapping of and an ors all this mapping is done still done at generic boolean thing at a g-tech thing. The second and third parts of the process are combined together we call it mapping or optimization it maps boolean functions to technology specific primitive function it modifies mapping to meet design goals. So, this part here this part here is actually the optimization part. So, when it says it modifies mapping to the first at first path synthesis will just map the generic boolean generic boolean it will map it to a target technology and then in the next pass it will start optimizing it will start looking at your clock frequency it will start looking at the timing which is given in the library files it will start looking at the review of the design it will start optimizing the design for for all these these four parameters. So, these four parameters are the key and they are in fact, in order of priority. So, the design rules come first we look into detail what design rules mean just a hint it means that the gates the logic circuit the individual gates let us say and and all and all they are not driving any load which is beyond their capability this should be met first step. If design rules are not met the timing is not reliable. So, for timing to be reliable design rules have to be met for met first step. So, this is the highest priority this goes number one timing goes number two because if timing is not met it is not guaranteed that design will function correctly area goes number three that is the last almost the second last since we have to first make sure that the circuit is activated and is accurately time there only we should talk about area third comes area and again last comes power but power can be given high priority some people the priorities of these are dynamic, but this is the general rule design rules timing area and power the process of optimization is constraint written. So, there are few statements written here create clause set into the day set out to the last match area do not take too much about it that the first three lines represent the timing goals the last line match area 0 represents the area goal it just tells the tool that just work hardest I mean same set match area 0 will actually not result into a zero area it is just a method of telling the tool that do your best job. So, what the tool will do it will try and meet timing and for a design represented by the top three lines and for that let us say there are n number of configurations which all of let us say they are five configuration five types of different gate level networks all of them meeting the three statement among these five the tool will choose the one which has lowest gate that is meant by set match area 0. So, now we see a very nice graph here on the x axis is the delay or you could also call it the performance of the design on the y axis we have area. Now, for a if you to go from left to right that is the delay is decreasing that is the performance is going down and the area is also going down we come to the if you go you see the lower area the small area this quadrant here this is for a smaller area the delay sorry for a larger area the delay will be shorter. So, if so these two are fighting each other the area and the delay always fighting each other there is one more angle to it point power, but let us let us simplify and see area and delay points. Now, if you want to reduce area what you would do is you would add more sequential more sequencing that is let us say you have a decoder kind of example the more parallel paths you have the larger will be your area and it will be slower, but if you increase the number of stages the area will be less, but the circuit will be slower it again even if you talk about the cell design the cells which are faster and have better drive strength are always bigger in area because again the W by L ratio would be high they will probably have inbuilt inverter or buffer stages. So, these two things area and delay are always fighting each other and the optimizes the process of optimization is entirely dependent on the constraint. So, the set of four statements here these four statements are what we call constraints same function can be represented by different circuit we see that you could have a NAND or base circuit you could always have a AND or base circuit it is in a MUX based design you could actually use a simple MUX or you could implement a MUX using AND gates and OR gates. So, and different circuits will have different physical parameters the tool which choose what to take based on our constraints. So, let us say you have a function y is equal to a and b and c and d the variate one on the left hand side is a circuit where the first stage uses two input AND gates the second stage uses a three input NAND gate a three input AND gate on the right hand side you have a four input AND gate and there is one two input AND gate. The power number and the area numbers are just some random numbers here they are they do not represent actual they just tell that what is higher what is lower in power. So, obviously, these four input AND gates if you actually go and draw the CMOS circuit of a four input AND gate you will see that it is a pretty large circuit correspondingly the two input and the three input set are lower in area. So, we see that the the variant to area is higher, but power is lower or let us say comparable to variant one. So, different and again if you if you see this one more important thing is that if we see the delay from e to y in variant two the delay from e to y the delay from e to y just crosses one AND gate, but delay from assuming this is the delay from e to y here crosses two AND gates or you could also say e is here again it will be but so the delay from e to y would be different in variant one and variant two. Now the constraint with that we give on e will also determine what variant will be picked up. So, that the table here shows that it shows the representative power and area numbers for sense. Obviously, a two input AND gate will have the lowest power in the lowest area a three input will have more power and more area when compared to the two input again as we keep increasing the number of input in a in a gate the power in area keeps on increasing. It does not mean that gates which have a number of inputs higher than two or three are undesirable that will again depend on our delay requirements. So, obviously,let us say a three input AND gate the delay from a to output from input one to output from input two to output from input three to output all will be similar in this whereas, let us say if you have if you try and use always a two input AND gate or a two input gates you will see that the delay keeps on increasing since you are you will be adding more stages to your combination. So, this is where what we say that this why we say that the delay and area are always fighting each other. So, the more number of stages you have in a combination path it will be slower, but it will have lower area if you decrease number of stages and you increase the parallelism you will have more area, but faster circuit. So, the let us let us see what optimization tradeoffs are. So, the circuit as we saw the circuit design goals are the first goal is obvious that is it should be design rules then comes timing. So, we should have small delays that is our goal power we should have lower power consumption and smaller area. Now, you cannot meet all three if all three are very aggressive. So, circuit design is a tradeoff of timing area and power optimal design. When we say optimal design it means that it meets all our goals is found as a result of synthesis based on the priority set by design. So, let us say there is a CPU let us say there is an 8 bit CPU or 8 bit 8 bit 8 bit next microprocessor design of that. Now, let us say I synthesize it for a 400 megahertz starting and then again synthesize it for a 600 megahertz starting. What do you think will have more area? Obviously, the 600 megahertz will have more area because I am asking the tool to give me more performance, but there will be some cost and the cost is area and obviously, the power. So, 600 megahertz microprocessor netlist will have more area and more power when compared to a 400 megahertz design. This is what is meant by the priority set by design. For example, when the delays are small the power consumption is high and vice versa. Circuit variant is chosen on the basis of the importance of one parameter. So, in fact, the most complex part of synthesis is actually setting the goals. You have the goals in mind, but then we have to translate those goals into a number of commands given to the synthesis tool. This is the most important and most difficult part of synthesis how to make sure that whatever goals we have on paper are given correctly to the tool. So, the goals the design goals timing area power are defined by something called constraints. So, constraints are set up rules that will set limits on circuit parameter and it will set priorities. So, during synthesis process and every time there is a choice every time the tool has a choice between several perfect variants the one meeting your constraints is always chosen. So, you could say in other words that synthesis is nothing but an optimization problem. So, if you go back to most of you would have studied the course of optimization and in optimization there is a very famous when a very interesting problem called a traveling salesman problem. So, if you have not read about it please read about it it is a very interesting concept. It tells that it tries to solve a problem of a traveling salesman he has to travel let us say through 10 cities. So, now the goal is the goal can be multiple one could be a traveling cost other could be a traveling time. Now, let us say so you be assigned that ok if he goes from A to B the cost is let us say x if he goes from B to C the cost is let us say y and so on. This is the problem now there is an algorithm which tends to solve this traveling salesman problem and optimizes the total cost exactly same thing happens the constraints set a goal and the tool will try to optimize the circuit based on the constraints. So, it is nothing but an optimization problem and every optimization problem depends on the goals we give. Next we see something called environment attribute environment parameters and nets net attributes affect circuit operation. Now, we saw in synthesis we have been talking about picking up gates we are not talking about how how they are connected together that means what are the parameters of the interconnect the copper interconnect connected together. Please note the interconnect information is only estimated during synthesis it is never accurate because circuit the the accurate information interconnect information only comes after physical design after the layout is done. So, in the process of synthesis we do not have the layout information obviously. So, any interconnect information we provide is based on some estimates we will see what those estimates are. Synthesis steps need to account for such such estimates for correct results. So, we should provide this provide this data one thing which we know for sure will be environmental parameters that is we we know that our design should work at a particular voltage temperature and some process relations. The net attributes the parasitic resistance and capacitance are at this estimates at this point at the point of synthesis, but we should provide something it should not be taken as 0 it it will be inaccurate. The environment parameters here very interesting concept let us see. So, this figure here tells what goes as input to synthesis and what comes as output project synthesis tool we give it the RTL code ok let us let us go and order in which we will actually do the process. So, the first thing that we need to set up we need to decide is this what technology are we targeting and then provide that particular cell library to the second we should know what are the environment that is what are the operating conditions we are targeting. Are we targeting a 1 dot 0 mode are we targeting 1 dot 2 mode this will affect synthesis and actually this will affect this also because environment attributes that is voltage process and temperature actually also determine the cell library. Usually you have the the because the timing of the standard cell let us say timing of an AND gate will change depending on what is the voltage what process are we talking about and what is the temperature. So, by fixing the environment attribute we also could be cell library and in turn we provide the library information and the operating condition to the tool then we go on and and give the tool the RTL code and then we define the we give this and then we give the we give the constraints these are the inputs what comes out is this what comes out is a gate level net list in very long or we are let us say very long. So, the gate level net list would be in very long and then this gate level net list goes to the physical design tool the physical synthesis tool where actually the the net list the gates are laid out the wires are the actual wires are drawn routing takes place and so many things happen the as far as this course is concerned we will not be looking at this our job is to make sure that we did get a correct gate level net list from the logic synthesis tool. So, we would be looking at cell library in an exception we will go into details of how a cell library looks like what does it contain we will see how to specify environment attributes we will see examples of this course does not teach very long it assumes that you know very long, but we will go through the good practices of the log coding or particle coding what type of code results into what type of hardware we look a lot into constraints this is the most important part and we look very heavily in this very heavily into this we will see how to specify this and obviously we will see the commands related to all of these problems. Now, let us see where the design compiler fit in an ASIC design flow. So, the ASIC design flow is something like this obviously we start with an architecture the architecture will tell the scope and the problem description for example let us say we want to make we want to design an 8 bit response this is the design this is the problem statement. Now, we will go and finalize the architecture what type of registers will it contain what frequency are we targeting that will in turn decide what technology node we should choose and so on then we will start coding. So, we will start writing the the microprocessor code in where log so, which is the SGA description then now since we have let us go to back to the previous side we have this RTL code we have the cell library since we chose the technology we have a moment at the view we will go on and there is one more process which comes this is not represented here is the functional identification simulation that is we have to first make sure that whatever we have written in very long actually confirms to the functionality that we define in the in our architecture. This is again a separate very big field of which is called verification that is you make sure by using some test stimulus that the RTL code the very short code actually performs according to the functional expectations. So, once we have made sure that the RTL actually is verified 100 percent we go to synthesis you could also use synthesis for design exploration obviously you do not need it to be passing 100 percent verification you could also do that many people do that. So, we go to design compiler in design compiler there is a tools called SGL compiler which actually reads the the log and the few things it checks syntax and all then is it goes to GTEC it does timing optimization, data path optimization, power optimization. So, design compiler is nothing but a book way of tool. So, inside design compiler you have SGL compiler and you have power compiler for power optimization in area optimization then if you want to add some DFT because there is a DFT compiler and timing closure and so on. So, the loop here this loop actually shows that this process is iterated in the sense that if you do not meet your power or timing or area goals you go back you either go back to RTL or you go back to your goals you reset the you change the goals to modify them and you make sure that this whole process is passing. The input to this process is constraints this is the file format is called SBC you will see this design where library we will see what design learning, technology library, symbol library and so on do not worry too much about depth for now. So, the output is optimized netlist this optimized netlist goes to some different design tools one example is IC compiler something else it goes to place and route and now we have to also make sure that the netlist here optimized netlist here is equivalent in functionality to the RTL here. These two are equivalent you have to make sure this does not mean please note this does not mean that the tool here the synopsis design compiler tool here has some problem. It can mean that whatever RTL whatever SDN discussion we wrote is not actually good enough to produce a good netlist. There can be many many reasons why these two are not equal these two are not equal there can be many many reasons why these two are not equal, but we will see we will see in the process of synthesis that what could those reasons be, but we have to make sure that these two are equivalent the process is called formal verification formality we will look a bit into this in this course. We will see why this is called formal and what is the difference between formal and stimulus based. So, just note that you could now somebody could ask that during the verification of my RTL code I have a test I have a stimulus. Now I can use the same stimulus on a netlist and make sure that a some sanity is correct yes you can do it, but from formal verification is a much more sophisticated and much more accurate we are doing. Please hold this heart for a while now the high level we will go a bit deep into the flow chart goes a bit deep into the high level design tool. So, you have design data preparation which includes SDL coding constraint generation library development we will not be looking into library development we are assuming that library is also already provided to us. Then we go into goal specification and function simulation what I was talking about this is a tool called dp explorer which will help you in doing some design exploration we will not go into that. We have to make sure that the design needs it is within 10 percent of time imposed in arbitrary requirement then we go to design compiler. The first process what it tells here is actually the design exploration stage of it many times when you are starting a first design you are not even sure what goals you should take. So, this process actually helps us a bit it helps us in using the DC explorer DC explorer what it does is it will do a very basic program because any feedback on all the designs in books after placing out needs to have some program information. So, this design explorer will DC explorer it helps you in programming the design, but we are not going into that just make a note that the process here this the first half will help us in setting the goal. Now we have a design ready we have the goal ready now we go to design compiler and again the the flowchart tells us that if you do not meet our goals either before physical design or after physical design we have to go back after design compiler and either modify our goals or modify our design one of these. Now let us look at the design compiler family the first and foremost a tool we are looking at is DC expert. So, you do not have to actually start up different tools so when you start design compiler we call it DC shell this is not a single tool it is has a bunch of tools inside it so all commands will work there for all the tools so you do not have to worry about invoking different tools for different applications. Obviously for each tool has something a needed license for example DC expert needs the license we will see there is one more tool called DC expert. So each I will call them a feature each feature needs a separate license something also so depending on what licenses do you have available with you those features will be available in your design compiler in your DC shell. So DC expert is a basic synthesis compiler it provides authentication for a a timing power using wire load models for delay estimation wire load model estimate the inter-connect delay DC what they look like. So what capability is this tool has it provides hierarchical compile that will stop down a bottom up in detail what does that mean it gives full incremental compile techniques sequential of inter-sequential optimization for complex the problem that is we saw time borrowing so it is able to do that for large bit designs timing analysis any synthesis tool will be able to do basic timing analysis to make sure the timing is meeting we will see a lot more of that. It has a online interface and graphical user interface first up when we start any tool we are emptied by the graphical user interface but for tools like design compiler and time time you will be heavily using the interface I personally favor text based interface because it is a lot of reporting capability the graphical user interface is only useful to see the circuit but for a bigger design you actually do want to go into that until there is some very exceptional and big problem because it will contain multi-million gates and you do not know where to start. So that is why I prefer text based that is the command line interface the advanced so DC expert is the basic component tool basic synthesis feature the advanced is DC Ultra what is being used in the industry to use DC Ultra it is much more advanced version of DC expert it does apart from what DC expert does it does does an advanced automatic optimization advanced delay optimization it helps in critical processing synthesis registry timing which is a very important feature it helps in that it has advanced it has capability for advanced time analysis you will see a lot of advanced here so it is just an advanced version of DC expert it is also capable of running into a big design it supports multiple execution for faster than time which is very important for this design the rest of the things are same as dp expert but for the scope of this project dp expert should be sufficient unless and until you are going for very high speed design or something like that dp expert should be sufficient and then there is a graphical user interface for this is called design vision again it is a separate feature not a separate tool so it provides analysis viewing and analyzing designs at detail level so it provides new dialog boxes drop down menus and so on so on but I would recommend starting with and sticking with the the text phase interface that is the command line interface it will be much more intuitive than the graphical user interface as you start practicing once of this you will see that is in that there is a feature called sdl compiler sdl compiler it translates your weblog and the sdl into gtech so again you have this sdl compiler is very much like a weblog compiler what you might be using in your other course for example mc weblog this sdl compiler has a lot of those features that is what it does now your weblog code will not be same so not 100% of weblog is not in the there are constructs which do not have any hardware equations for example in the weblog many times we write we want to delay something we write hash n number let us say hash 5 hash 5 is equal to b that is b is assigning being assigned to a after service or delay now this particular delay unit that is hash 5 I have that thing equivalent to in hardware that is yes we have hardware we have the person in the what will give some amount but saying hash 5 will not result into some hardware that is this the synthesis tool will simply ignore that so this sdl compiler helps us in analyzing if our code if our RTA code is actually synthesizer it will give out warnings it will give out errors if you have cases like this so you could use the sdl compiler into correcting your design there is a family of components for design with now if you go back and remember that we call that the process of a translation converts the material into a g-tech as well into a generic Boolean network so a designer library is a collection of reusable circuit design between both which are tightly integrated into some of the synthesis environment so let us say if you have the license for the feature available and let us say you write a plus b in your RTA code now this class now assume the 8 and b amd to be let us say 8 bit what we are doing here is we are doing is 8 bit addition that adder will not be a simple adder now this designer library contains a lot of adder different adder you have carry look ahead you have carry save and so on so it implements all the all the all the adder architecture and you could use them or tell the tool by simply writing a plus b and also telling so if you write a plus b and simply synthesize if your design requirements are not to everything if you do not need a very fast adder it will pick up a ripple adder implement by itself now you could tell the tool you could tell design compiler that do not use ripple adder it is slow use some other adder architecture so it will do that so a design library is a collection of all such adder multipliers and so on there are lot of components there so it contains a lot of components which will help you in designing complex circuits and it is very tightly integrated into synthesis environment during synthesis design compiler will select the right component with the best speed and area optimization from the design program many times you do not need to specify mission in RTL code but I have seen people they are very particular that okay for example I would want that in all the cases my RTL code in multiply I multiply I use should be a boot for the class so I can actually specify in my RTL that for a multiplication operation I can say that that you that you multiply 0 1 less than the name of a designer component I could directly instantiate it in my law and DC and she also design compiler will pick it up and synthesize it so this is all in the next lecture so we what we saw let us review of it so we saw what the process of synthesis is it combines the process of synthesis and the broken into three parts translation mapping and optimization the translation is simply conversion of your RTL code into a generic Boolean at least the process of mapping and optimization actually convert that Boolean at least into a specific technology that will be met list and further optimizes based on the goal supervising we saw that we can the goal to provide our timing area and power assuming all the design rules are met in that order of priority so we will see next lecture we look into the library the standard cell library what types of standard cells are there how is timing and area information presented how to read that it is very very important then we will start we will begin with the RTL code we will see how we will see the good practices of RTL coding for synthesis we will see the process of synthesis we will spend a lot more time on writing the constraints and writing how to write how to mention the how to set timing goals how to set area goals and so on thank you