 Welcome everyone. My name is Ms. Shweta S. Patil, working as an assistant professor in Electronics and Telecommunication Engineering Department at Vulture Institute of Technology, Solapur. Today's topic for the discussion is the parity generator and checker. Learning outcomes. At the end of the session, the learners will be able to design a 3 bit event parity generator and design a 4 bit event parity checker. Contents. First is the parity bit and code. Example of event parity code. 3 bit event parity generator. 4 bit event parity checker. Application of generator and checker. Parity bit and parity code. Parity bit is either 0 or 1 depending on number of 1 contained in code group. Parity bit P is an extra bit that is attached to input code group. There are two types of parity code. One is the event parity code. Second is the odd parity code. Even parity code. If count of 1 in the code group is even, then parity bit P gets the value as 0. If it is odd, P gets the value as 1. Here in this example input code is given with the parity bit P generated at the output. In first example count of 1 is even, so P gets the value as 0. In another two examples count of 1 is odd, so P gets the value as 1. In even parity code to make total code as even parity code. If count of 1 in the input code group is odd, then parity bit P gets the value as 0. If it is even, P gets the value as 1. In first example count of 1 is even, so P gets the value as 1. To make this total code as odd parity code. In another two examples count of 1 is odd, so P gets value as 0. Example of even parity code is the two input XOR gate. This is the symbol and truth table of XOR gate. When input A and B is considered with the output, at that time in total code if count of 1 is even, then it is known as even parity code. So here for each combination there is a count of 1 is even, so two input XOR gate is the example of even parity code. This is the block diagram of three bit even parity generator. Here three bit name is given because to this block X, Y and Z three input is given and P even parity bit generated at the output. Here X is the MSB and Z is the LSB. This is the truth table for the three bit even parity generator. Here input code if count of 1 is odd, P gets the value as 1. To make total code even parity code. So in the even parity generator P gets the value 1 for the first combination, second combination, fourth combination and seventh combination. This is the K map for the three bit even parity generator. Here 0 and 1 from the truth table for the P it is entered in the K map. From that P even is equal to we get this expression. Here X bar Y bar Z minterm is written because from this K map here 1 when we are grouping it at that time X bar Y bar Z we can write as a minterm. For the second grouping of 1 we can write X bar Y Z bar. For this one grouping we can write X Y bar Z bar. And for this one we can write X dot Y dot Z. This Boolean expression is rearranged after that Z and Z bar is taken common. And we get some expression with the X or operation. And finally we get X X or Y X or Z simplified expression for the three bit even parity generator. From that simplified expression we can draw the logic gate diagram. Like this here two input X or gate is implemented for the three bit even parity generator from the simplified Boolean expression. Four bit even parity checker. This is the block diagram of four bit even parity checker. To this block X Y Z three input with the even parity generated P is given. And at the output we get the C as an parity error check bit. This is the truth table for four bit even parity checker. Four bits received at the transmitting end are here X Y Z and P. At the output parity error check denoted as C. Wherever count of one in the input code group is one there is one. P C is equal to one if error occurs in the input four bits received at the transmitting end. For that we can write the Boolean function. F of X Y Z P is equal to summation of min terms of first, second, fourth, seven, eight, eleven, thirteen and fourteen combination. From that Boolean function and this truth table we can write the Boolean expression. For first combination X bar Y bar Z bar dot P is written as a first min term. For the second min term for this combination in the truth table there written X bar Y bar Z dot P bar. After getting all expression we can simplify like this. So we get the expression for the parity error check like this. After that simplifying we get C is equal to X X or Y X or Z X or P. After that we can draw the logic gate diagram with the two input X or gate. And here three X or gate are necessary for implementing four bit even parity checker. For X X or Y and second Z X or P both are X or and given as an output C. Application of generator and checker system. This is the block diagram for odd parity generator or checker system. BCD input message is given to parity generator block. It generates the parity bit P as an output. P is given as an input to the parity checker block along with the same BCD input. The message including the parity bit is transmitted at the and then checked at the receiving end for the errors. An error is detected if checked parity does not correspond with the one transmitted. Here generated parity bit one is here same parity bit given to the parity checker block. If P is equal to one then there is an error and if this P is equal to zero then at that time error is not occurred. Conclusion. The circuit that generates the parity bit in the transmitter is called parity generator. The circuit that checks the parity in the receiver is called parity checker. A parity bit is an extra bit included with the binary message to make the number of ones or ever. A parity bit is used for the purpose of detecting errors during the transmission of binary information. These are the references. Thank you.