 Hello and welcome back. In this section we are going to start looking at the SDM32L0 architecture. If we look at the block diagram we can see that the architecture can be broken down into three main categories. System or core peripherals at the top and to the left. Standard peripherals common to most of the SDM32 families. This and low power peripherals highlighted in green unique to the SDM32L0. These three sections are all connected together by the buses. On the left hand side we have the bus masters and on the right hand side we have the slaves. The multi-layer bus matrix allows the core and DMA to access the flash, RAM and peripherals in parallel. The dual APBs allow us to have high speed peripherals and low speed peripherals on separate buses, giving you the flexibility to enter different low power modes. All the peripherals on the APBs can be clocked and reset independently of each other, giving you full flexibility for low power applications. Let's now look in detail at the system peripherals. The largest element of the system peripherals is the Cortex M0 plus core itself. All the blocks within this element have been designed by ARM and are optional. At ST we have added all the optional blocks with the exception of the micro trace buffer. As the STM32L0 is a small device the micro trace buffer will use up too many pins on the device. The Cortex M0 plus core is a von Neumann architecture with a two-stage pipeline and can handle a mix of 16 and 32-bit instructions. You may have noticed from the previous slide, the bus matrix, we have also included the low latency IO interface for directly connecting the GPIOs to the core. The instruction set for the Cortex M0 plus is the subset of the other Cortex M cores. So any code written for the Cortex M0 plus can be recompiled for use on any of the other cores at a later date if required. The two-stage pipeline on the STM32L0 has been selected to maximize the energy efficiency of the whole device and maintain a steady flow of instructions into the CPU. Comparing the two-stage pipeline to a three-stage pipeline, when a branch occurs on the three-stage pipeline, energy has already been used fetching and decoding the next two instructions that will never be used by the core at this time, whereas on the two-stage pipeline this is reduced by 50%. On the STM32L0, the debug is done via the serial wire interface. This provides up to six breakpoints with the loss of only two GPIO pins on the device. Let's now take a look at some of the peripherals within the system block. The DMA controller is the second bus master and is used to relieve the Cortex core of data movement tasks. In picture one, the core can read instructions from the flash whilst the DMA reads data from the RAM. Then in picture two, the core can access the RAM whilst the DMA transmits the data it has just read from the RAM out to the peripherals. The DMA comprises of seven configurable channels with configurable priority to do peripheral to memory, memory to peripheral, peripheral to peripheral, and memory to memory transfers. The internal memories are the largest single slave device within the STM32L0. These memories are mapped to a defined 4GB address space specified by ARM, separating flash, RAM, external memories and peripherals into different address blocks. Within the flash box we have the system memory that contains the boot loaders controlled by the Boot0 pin on the device. This allows you to program the flash via the USART or the SPI. The reset and clock control is a key system block within the STM32L0. The clock tree of the STM32L0 is like a gearbox containing six different clock sources. The multi-speed internal clock is the default clock source of the STM32L0 and is used for low to medium frequencies and has a very low power consumption. Then we have the other two internal clock sources, the HSI or high speed internal for running the device at full speed and the low speed internal for running the watchdog and the RTCs. Then we have the two external clock sources, again high speed for running the device at full speed and to generate via PLL the 48 MHz required for the USB and low speed to provide an accurate clock source for the RTC. And finally we have the HSI 48. This clock has been designed so you can run the crystal-less USB and also generate the clock source for the random number generator. Just like the clock tree, we have multiple sources for reset. There is the typical power on and power down resets and in addition to that there is the brownout reset. Then we have a programmable voltage detect peripheral. This can be configured to generate an interrupt as the power drops so you can save critical information to E2P or shut down the device safely before the power reaches the brownout or power down reset value. Other peripherals on the STM32L0 can also trigger resets like the watchdog or the firewall. Without power we would not have the ability to work. The power domain on the STM32L0 is split into three sections, analog, digital and core. Then we have two specific power functions for USB and LCD peripherals. In all devices analog and digital are very closely linked. For small pin count devices they are internally connected. The reason for external pins is to provide better decoupling to the device. The core is powered by the main voltage regulator in the digital section. For low power modes this voltage regulator can be shut down to save power. The VLCD is used if you want to provide an external source for the LCD controller rather than using the internal step up converter inside the device. The VUSB is used to power the full speed USB transceiver within the device so you have the correct signal values on the USB lines. If USB is not used then VUSB can be connected to VDD. For battery powered applications the STM32L0 can run down to 1.65 volts extending the battery life of the end product. Not all peripherals are available down to 1.65 volts, primarily the ADC, but most are. You even have the ability to reprogram the flash or DTE2Prom at this voltage. Let's now take a look at the GPIOs. The GPIOs of the STM32L0 are very similar to all other STM32s with the exception of how they are connected to the core. On the STM32L0 they are connected via the ARM IO port and not the AHB as used previously. This provides us with fast toggle on every single clock cycle. Most of the pins of the STM32L0 are 5 volt tolerant and can be programmed as alternate function or into multiple input output modes shown in the center of the slide. We also have the ability to lock or freeze the IO configuration for sensitive or critical parts of applications. The remaining system peripherals are the watchdogs. All STM32s have two watchdogs and the STM32L0 is no different. We have the window watchdog running off the same clock source as the code. This can be configurable for early and late application behavior and is capable of being stopped in certain low power modes. This is the reason we have the second watchdog, the independent watchdog, powered by the LSI clock source. This watchdog can provide longer timeouts to cover certain low power modes. Thank you for listening to this section.