 Okay, so we start with what we were talking last time continuing with some little more about DFAM. Though actually DFAM needs much more explanations. I will start working on DFAM frequency response later after this today's after the exam and that time I will show you more problems of DFAM designs. So let us start with the present a problem which is not really present in last 15 years 10 years I can say. We have been working with short channel devices and I repeat for those who have forgotten a short channel if device is defined as if the channel length of the device is comparable to the source drain junction depth or almost of equal to the depletion layer width in the gate region in the gate region. Is that clear? If they are comparables then we say device is in short channel. Essentially the way scaling goes that we scale the dimensions of the device let us say from the depletion layer width below the channel and the junction depth of source and drain. Either of them are comparable to channel length then we say device is in short channel. The problem with short channel is I will say when you scale length and width the problem is it creates lot of problems on linearity which is essentially the output currents and we like to see then what happens but please remember scaling is more relevant because we normally do what we call voltage scaling. If we do field scaling that means all voltage length everything scales then there is no problem everything is scalable but that is not possible because the power supply values are not decided by scaling people. It is decided by system people. So we started with 5 volt, 3.3 volt, 2.1 volt, 1.5 volt, 1.2 volt, 1 volt, 0.8 volt so this is not something which I can decide this is someone else is going to decide. If I scale then then the voltage to length ratio or fields will be larger because voltage will not scale as much as the lengths will scale and there is the issue where it creates problem for performance. Typically if you of course there are many short channel effects you must have done in many other courses I just list for something which you have hurt me in this course. One of the problem I see is the mobility variation due to the fields because both EXEY increase there is also a problem of VT reduction as the channel length goes down. Of course there is another issue some other device person will know that we have come very close to 90 nanometers around. There is a increase of VT this is called amounts. So there are issues there also if you are in that region you will have to take care of your VT much more. Then there is the increase of source drain resistances. The reason is as I just now say scaling things the junction depth goes down and the dimensions also X and Y goes down for source drain. So resistance actually increases. The leakage currents also increases because of variety of leakage mechanisms including diode leakage, gate induced leakage or what is called griddle, gate tunneling effects, band to band tunneling and N number of high field injection problems. So there are huge problems in leakage currents. So they normally enhance when you scale. However as I say these are not the only effects which we are worried about in digital course someone must tell you or in devices course someone must tell you much more on that. VT always reduces with channel lengths. Think of it okay. For a device way, what are we? The first and the foremost effect is absolute terms. Leakage current absolutely increases enormously. Some of the leakage currents are exponential and that is our worries. In leakage of course as I say this is not a digital course but just to give you an idea what you are saying or for all high performance circuits we are interested in what we call on to off ratio. On currents hardly increase but off currents which is the part of which is 90% leakage increases enormously. So our worries starts that once I said you also that why we allow students to continue listen because off power is larger than on power okay. So therefore it is better if you use rather than keep in standby okay. This is of course a fun part in that do not go by that. Okay so let us for us which is immediate of interest is this. As I said there is an increase of source and drain resistance. Drain resistance of course can be taken care through the load value. So you can say even if 10 ohms increase there the loads are 40 kilo ohms or 10 kilo ohms and above. So that series resistance that does not matter as much whereas in the source side if you see a resistance what is strikes immediately if there is a source resistance in a amplifier what does it do it reduces the gain drastically is that correct it is called source regeneration. So the first problem comes when the short channel device is used there is a source resistance now and it enhances as channel link goes down further and because of that there is a source degeneration effect which reduces the gain of a defam. This is an issue which otherwise in a long channel we may not worry about okay. I will not derive the expression which follows soon. We define a term current difference between this and this IOD is defined as I d s 1 minus I d s 2 which is essentially g m v I d where v g s 1 v g s 2 can be explained in this expressions and we can now see for this node v g 1 minus v g s 1 minus I d s r x is equal to v g 2 minus I d r x minus v g 2 is essentially equal because this point does not move okay. So this is an equation which now you may have to use in your evaluations is that clear and the major effect as I say is instead of doing all of it again is source resistance in an amplifier is 1 plus g m r s times the gain may go down okay that is the feedback effect in fact you will see is that okay. So this is a typical expression you can look into books of course the other we does not have some other books I do not recollect the ratio of the difference current of the two arms divided by I s s a net current which current source applies can be expressed in a Taylor series which is v I d by v o v minus 1 by 8 v I d q by v o v plus other higher terms since v I d by v o v is smaller since denominator increases in short channel case difference and apply with the r s x will show better linear characteristics that is fantastic but then it will actually if you see the terms this term will be even smaller because now so you will actually come closer to linearity so one of the advantages of having source degeneration at the cost of gain is your linearity impulse so it is something everything is not going wrong as we think so okay but if I d r s drops will also reduce g m because the available current available voltage to be smaller so essentially g m at a given current will also actually reduce however please remember what is our design parameter all through as I say though I have written expression in terms of v o v but what should be our design spec on g m by I d s so if you look at this g m by I d s term so we said last time and as I say g m by I d s is now 1 upon 1 plus g s r s 2 by v o v and not just 2 by v o v as we thought or if we calculate v o v this can be in this term so substituting this in I o d I s s expression for long and short channels I already divide 1 upon v o e is this expression or this expression is g m by 2 I d s okay so if g m by I d s is our design parameter which we are going to have why did I say that v o v is not a good parameter of design because v g s minus v t is excess voltage which can be chosen by any number or can vary any time so instead of that we prefer to have something which is more rigid which is g m by I d s ratio okay so we say all that I am trying to get the expression for 1 plus g m r s x v o v is equal to g m by 2 I d s and if I substitute this expression in the I o d expression both for long channel and short channel so if I substitute for both this 1 upon g m r s r x into this into this expression for long channel and short channel for a long channel it becomes half g m by I d s v I d minus 1 by 8 half g m by I d s v I d to the power cube and in a short channel case I o d s by I s s will now become g m by 2 I s v I d minus 1 upon 8 1 plus g m r s x v I d cube we now see since the second term has large 1 plus g m r s x divider there okay this term will be further smaller why it is called cube term is not interesting to us because it is introducing a nonlinearity in the I v characteristics essentially so to make a linearity this term should be smaller so by source resistance available the second term goes down there first remains same and therefore we can say that in a short channel device even with g m by I d s design parameter linearity will improve with short channel device so do not feel you know everyone always try to occurs short channel devices of course digital people do not curse so much because the first thing they look into or even we should not look so that way bad way because the first thing they say the electron or whole transit time from source to drain will be smaller if the channel length is smaller smaller the propagation time higher is the speed so for any high speed circuit the first criteria for me is channel link be as small as possible preferably 0 then everything what is these devices are called when it is equivalent channel links are 0 I thought maybe you are done some seminar these days or is there are devices called tunnel devices or tunnets which do this this or called also ballistic devices where typically they have no restriction of moments some other day some other time so the point I was trying to say that short channel device is better as far as linearity is concerned the only problem which it may create is the net gain may actually reduce but gain can be pushed through other means by increasing ideas but if I increase ideas power will go so there is an issue there or if I increase size the capacitance is increased so the bandwidth may go down so they are not that it is so trivial but at the same time at least swings are larger so if you are looking for a larger swings yeah this is the better device normally what did I say channel link should be as high as possible for what purpose I said you are out essentially is given by lambda dash by okay so smaller the channel link the output resistance is higher good for gain GMR okay so longer length devices always are preferred for high gains so you think of it now conditions where do are you working at what are you looking at and therefore correspondingly sizes may be chosen by is that design clear to you this is what designers do I want this so what should I do is that okay all of you okay so now we this is something which I last time should have done finish I thought I have finished once a while I thought but maybe I did not I do not as I say I am going to talk about the defam once again little latter with the bandwidth and some other issues which defam is creating why I am now worried about defam problems because defam as I keep saying is the main gain stage of an operational amplifier which is our workhorse so anything I want good from a opamp I must get first from defam itself and any problem which defam is showing will automatically a problem for opamp as well okay so at the end I am interested in an opamp design not really specifically only defams but I know if I design this properly I understand what to design and I also can design opamp as good probably will see there are other issues may come with opamp but they are different before I first I thought I should finish that and also thought I should do frequency response but I thought that frequency response can wait because we will look into that more specifically from the stability criteria so we will club everything there right now you assume the bandwidth is essentially given by 1 upon 2 pi R out into CL or CGS or C in whichever is the value given to you the other R by RC constant must be not comparable here and therefore neglect so mostly I am talking of a dominant pole which will be given by one value of the capacitance given this much you are anyway done in your second year or third year courses so that that much knowledge right now may be sufficient please take it it will have impact in our designs last time I showed you values bandwidth gives you R out by CL values CL given to you it evaluates your R out R out gives you links and ideas and therefore this ideas has another limit coming from given bandwidth okay is that clear so do not ask me that you are not taught that I have taught in an indirect way okay so here is a new chapter I switch new area we want to start because these are required in normal opium or defam designs so that I will first do that few things which are a basic blocks in any analog block analog circuit or analog IC is how to bias and one of the strongest way of biasing those circuit we suggested is to make current sources and so we like to see which are these current sources are current sinks what how do you differentiate between a source and a sink if it starts from power supply then we say it sourced if it goes to the ground it is called sink basically they are not very different but just for the sake of clarity anything which current enters the ground then it is a sink if current emulates from the power supply then it is called source they are identical in values many times the same current may go down but just to get where do I put that source current source as such may be called source or sink theoretically it does not matter but principally one should know where is the placement going on okay. So as I said in most analog ICs you need current sources the major requirement for a good current source is its output impedance okay I will enter here the first is you need allowed as large as possible preferably infinite if it is ideal source otherwise as high as possible we also should see that to keep devices in saturation the output swings are limited if you are too much output swing you may go out of saturation regions. So a current source when you design you must see that you are always in device should remain in saturation why do I say current source is a saturated device because saturated current of a transistor is beta by 2 into Vgs minus Vt or Vov square into 1 plus lambda Vds. So Vov square square means it is a square law term and therefore we say and if we lambda is very very small the current is constant okay current is constant therefore it is called current source or sink so device must remain in saturation if you want a current source so many times this swing which you are actually expecting in your defense or many other places is limited because this current source may not remain current source okay and therefore this has to be very limited of course too far away normal ranges but you must keep in mind and third and the foremost is V minimum what is this why I am worried about V minimum what does that mean normally we say that the diode for example has a cut in voltage of 0.6 so what does that mean that till that voltage is reached in part bias no current flows is that so if we mean is the drop across the current source firstly it will take Vdd minus this much available to you downwards is that clear that means it is also now consuming power okay because there is a V drop there it is consuming power so to minimize power and you want to have a ideal current source is what see if I plot ideas versus Vds I would expect ideas versus V whatever if I draw for good current source I will like something like this but in real life okay something like this happen and this value is that okay ideally what do I want like this constant current source okay so I must minimize V minimum as much as possible in reality 0 it cannot be made because device will have some drops but how much minimum we can go is the goodness of current source so how many three parameters to worry about one is the output resistance to swings available to you which makes device remain in saturation and three the smaller the V min better as the current source is that correct so these issues are clear to you so these based on this and I said you already apart from every other thing a typical current mirror satisfy many of these requirements directly sometimes indirectly okay I hope that you appreciate what we are talking about that anything you have already done but all that I am now trying to show you repeat of what you did in second year third year wherever you were is design perspective it is not that this theory was unknown to you knew it anyway as good probably or maybe better than me but now as a designer what I am looking at but to know design we must go through theory a bit again so let us have a normal current mirror which is called simple current mirror shown here which is giving to me a current source of I0 value which essentially the way I had correct is ideas to our M2's drain current there is no connection here please take it so it is VDD power supply I have a resistance R then I have a transfer M1 whose drain is connected to its gate the two gates of M1 M2 are also connected and M2 then has a current which is ideas to which I declared as my current source which is I am correct creating from mirror mirror in the sense whatever in the first M1 I am having that is mirrored to M2 that is mirrored to M2 and therefore this name was given current mirror since I am connecting gates so whatever is VGS1 is same as VGS2 if the sources are connected and gates are connected VGS for both transfer should be same is that clear and if their sizes are also same then what will be same the currents will be also same is that clear if their sizes are also same I repeat what I think VGS1 and VGS2 are equal and if the sizes are also equal by ideas equal to beta beta dash by 2W by L VGS minus VT square okay so we say if VGS is same for both and we say both both transistors are have equal currents okay so we have mirrored the current in the first to the two but will calculate they need not be equal and then sizes so we will just look into it if they are equal then of course ideas one is ideas 2 and ideas 2 is your I 0 okay so we are current source which is proportional to are exactly equal to ideas one so this is mirrored one however in case their sizes are not same which mostly will be ideas one now I can calculate the current please remember current in resistor is the same current in M1 because there is a gate which does not allow any DC current to flow so ideas one is VDD please remember this current in this arm through R is VDD this is shorted okay this VSS sometimes this VSS will be 0 other it will be minus value okay so right now the way it is it is minus of minus so it will add in fact is that clear to please put VSS either 0 if given or minus of something so typically what we do we say dual release let us say I need a total power supply of 3 volts I VDD I put 1.5 VSS I put minus 1.5 this is called symmetric rails but it is not compulsory that it should be equal to 1 also can be done 2 minus 1 or minus 2 plus 1 also can be done their advantages and very very poor thinking all four problems also may appear if we change VDD to be if this not symmetric the analysis becomes very complicated so we normally always all books all teachers will take it simple solutions and maybe ask you what happens if they are not equal so this minus this they were subtracted by one of the VGS so VDD plus VSS you can say add in numbers minus VGS 1 by R is the current flowing in this but this current in the transistor is beta dash by 2 W y L VGS minus VT square 1 plus lambda VDS 1 okay by logic of same this IDS 2 is beta dash by W 2 by L 2 VGS 2 minus VT 2 now if the transistors are not identical VT 1 VT 2 also be different so as sometimes even lambdas may be different but right now assume and lambda dash by L L is say common for both devices which is generally the train so I am not using separate lambda but otherwise you should use separate lambdas as well okay of course as I say IDS 2 is the current source which I am looking for I 0 so I have two equations IDS 1 and IDS 2 so I take a ratio of IDS 1 by IDS source or IDS 2 by IDS 1 because my IDS 2 is my outputs so I take a ratio of with reference to IDS 1 what is my I 0 I 0 is that okay I mean this is what you are done this is just to replicate what I said so if I divide the equations IDS 2 by IDS 1 is I 0 upon IDS 1 which is equal to W 2 by L 2 divided by W 1 by L 1 beta 2 dash beta 1 dash few C ox is also right now kept separate in case they are there you just cancel that they are same they can cancel that why I did this because there may be some P channel devices sometime may come somewhere so we do not want to write now write anything but generally they will be cancelled VT is a both are in channel in the same process of same channel length nodes then beta 2 dash would be equal to beta 1 dash also VT 2 will be equal to VT 1 also lambdas are same and right now assume lambda is extremely small 0.05 or 0.0 in that case everything can be cancelled out VGS 1 is anyway equal to VGS 2 by force because you are connected the drain of N 1 to the gate of M 1 and gate of M 1 is same as gate of M 2 so VGS 1 is always equal to VGS 2 if VT is are same this term cancels if lambdas are small then this term cancels and if betas are equal this term cancels all that I get is the ratio of sizes W 2 by L 1 upon W 1 by L 1 and then I substitute IDS 1 value which I derived as VDD minus VGS 1 minus VSS by R I 0 is essentially the ratio of W by L of M 2 to M 1 multiplied by this current which is VDD minus VSS minus VGS 1 by R. So if I want to design a current of value particularly what I will fix I will fix R okay I will fix R I can also fix VGS 1 through which term VGS 1 minus VT is what V O V so I can fix excess voltage a priori I say okay 200 millivolt 300 millivolt VT are given to me which I do not fix but they are given to me so I can actually know what is my VGS 1 okay supply I am going to fix anyway for the technology I am given so 2.5 minus 2.5 for a 5 micron 5 volt technology typically this will be why I am talking of 5 volt 5 micron because much of the problems which they are solved better in actual design are given in Boyce and Baker's book okay Lee Boyce and Baker they are one of the very good hardware engineering books of course they are two books the latest version of Baker is also appearing and if you see them they are given the real life values of course the only thing they did not want to show you the 0.25 or 0.18 micron results which new book of Baker has shown some of them but old ones they wanted to keep because of the problems of the security or something they are all data given is only 5 micron 5 volt process since I may solve some problem from there so I thought I will keep this value but any other value data must be given to me okay like for example of a 0.25 or 0.18 VOV is normally taken 200 millivolts but for higher it can be 0.4 so it is not that this number is big this is what you design based on your power supplies what is the criteria for that the device should remain saturation irrespective because there is sufficient headroom must be available for me to keep device so this value is also not very fixed you can actually take some value around and use that also okay is that point clear typically as I say for most analog design which we do at 0.13, 0.18, even 0.13, 0.25, 0.18 we use this value of 200 millivolts okay this is typical value please do not take it over one of my our student has taken 0.25 that 250 micro you might have chosen because he must have figured out that by doing this he has he is now going for lesser headrooms where enough does not matter but at least he is keeping device guaranteed in saturation so that may be his choice okay so if I want to calculate therefore I can if I then fix the ratio of W by L 2 to 1 1 of course I will fix what should be 1 W by L by 1 normally the minimum W by L 1 is 1 you can use you can use 5 micron by 5 microns as for the 5 micron process but this is one and this then you accordingly put 10 micron by 5 micron 20 micron by 5 micron depends on the increase you want to go beyond this typically what is an R out for this circuit the current source shunting R out is nothing but lambda I DS 2 okay which is 1 upon lambda I 0 and many a times please take it 1 upon lambda is used as early voltage VA by and by units it is correct V by R V by I is the distance so if given instead of lambda I may specify you an early voltage I am specifying you lambda exactly so if also I give you lambda dash and I am actually specifying the lengths okay so how do I design us look at the way given a value he actually have access to other parameters okay so typically you can see if this is in the order of micro amps this will be order of 50 to 100 volts you can see this will be order of mega ohms or above okay tens of mega ohms tens of mega ohms is not extraordinary large resistance compared to infinite which you would have like to okay but even then relatively much enough good enough for normal use okay is that okay so this is a good current source we thought but in reality we will say it is not that good because if we calculate the beam in for this which we do later then you will figure out that this is not that great okay is that okay last everyone okay here is some example which I am using on maps quickly VT 0.6 volt lambda 0.06 VOV 200 millivolt supply voltage is 1.5 minus 1.5 VSS IDS 1 is 10 micro amps so what is VGS 1 now I assume VOV as 0.2 volt or 200 millivolts so VGS 1 is 0.6 plus 0.2 is that okay how do I get my VGS 1 VOV plus VT okay since I am given a current in the first arm as 10 micro amps I can calculate the resistance used as VDD minus VSS minus VGS 1 by IDS 1 which is around 220 kilo ohms essentially saying if I have a 5 2.5 2.2 volt supply put 220 K as the resistor there the drain current of M1 is 10 micro amps is that clear 10 micro amps and I then calculate yeah in a technology it is normally fixed you are right your point is in our case same because VGS 1 is same okay so we assume it is VT 0 also same so V is also same if they are not equal then you can use differently but in a technology it is very difficult to change VOVs normally for keeping a transfer on saturation some value is fixed for all of them for P channel it may be different from N channel for all N channel will have same VOV if you have seen my earlier graphs it does vary but then you have to find optimum VOV there if you you have to plot it and figure out what VOV I should use if you see your earlier notes we have shown you if it varies what do we do fine figure it out see analytically if you do if you keep varying then you cannot analytically solve then you have to go numerically or plots graphic is essentially numerical solution if you do numerically you will get exactly but if I do analytically my assumption has to be something which I can evaluate okay so if I I 0 is 10 microns then beta dash by 2 W by L 2 VGS minus VT VT are equal let us say then okay then I substitute all of it here and evaluate W by L 2 which is by 50 by 11 which is around 4.54 microns is taken from that technology is 110 microns per whole square I think have I not written here okay may be this is written here the 100 and for N channel this value also will be specified for a technology you see ox will be given to you typical value for 0.25 or 0.35 is 110 microns per whole square is the beta dash values this is typical data is taken for 0.25 micron process why I am insisting on 0.25 as much because most of the analog blocks will be designed on 0.25 or 0.18 but if they are mixed signal which technology they will have to design whatever digital is asking I do not have any choice okay they say 90 nanometers they said 11 nanometers I will have to design all of it for that technology but if I am only doing an opamp for my own sake comparators I want to market on for board use then I can design on 0.25 as I say scaling has some advantages but it actually reduces the gain so we preferably to have little larger technology node but not too large because then it creates huge power losses so we are trying to manipulate that so most analog chips which are marketed will be either on 0.25 or 0.18 some may be on 130 nanometers but rarely on 90 nanometers please do not think there are some analog devices which are on 90 nanometers but in general I will say almost all opamps which you see excess areas 576 of that kind all of them are typically on 0.25 but if opamp is a part of a digital network some session then it will have to be designed at that and you will be surprised that gain of 10 to power 6 is unthinkable there so then you have to really worried about how best you can get solutions there so think of it are out if I given lambda so I get 1.66 mega ohms if I choose link 0.25 typically around 1.25 micron bits are good enough for W2 and you can evaluate you can get your source we must guarantee VDS2 should be VGS2-VT for saturation therefore VDS2 must exceed 200 millivolts okay so then only we can say it remains in saturation okay here is some interesting features how mirrors are used the mirrors are used to create currents in different arms so it need not be of the same current in different places so I may actually have this R M1 based calculation to give me IDS1 and then I can have W by L differently for M2 M3 as long as I connect their gates VGS1 is equal to VGS2 is equal to VGS3 okay and in that case the ratio of this to C is W by L ratio of this to this W by L will give you the current proportion into IDS1 so it is IDS2 by IDS1 will be 2 IDS3 by IDS will be 4 if these are the sizes so it will flow 10 micron 20 micron 40 microns currency as I say these currents are actually sinking because the currents are going towards ground okay if you want to create a source kind a P channel devices can be used is that last clear in n channel current is going to the ground if I had to take up from power supply I must create a current source which we can then use it only a P channel device sorry if I P channel device then I can have gates connected to drain of M1 as they are they were and then R is grounded and this is your VDD so current here and current here is the ratio of W by L of M2 to W by L of M1 same as n channels is that clear now I will give an example why I use this many times it is called sourcing combinations so is that clear this is source and these are sinks you need not call it that way but the current entering ground is sinks current coming from power supply is called source this is a definite nomenclature need not be very seriously worried about it okay that figure clear to you so n channel device I can create current mirrors so is so far if you want further currents elsewhere what should I do extend this gate ahead put another transistor different W by L if you need current of that proportional to this the third arm keep doing this as many as you want why we can guarantee M2 there always in saturation of this M2 because VGS1 and VGS2 are always connected gate therefore if one is in saturation the other has to be in such here is something which you should learn because this is what yes no it does not because VGS1 and VGS2 is decided by this minus this one time only this value minus this is this value is that clear so that is one time decision R will decide how much is you are actually getting that correct for a given this this minus IR plus VSS is the all that the VGS will be which is getting fixed anyway through R this another issue which many designs will require is the following is that okay this VDS2 why should it vary VDS2 will be always equal to VGS2 will prove it it is always at the edge of saturation will come and show whichever is the current there it will always be equal to VDS2 will be VGS2 just check it so that device is permanently in saturation okay here is a method of transferring currents you create a N channel current mirror which is sink kind and then you want to transfer on a P channel device as a source current okay so you have another P channel source area and please remember now I do not need R there what is that R was giving you anyway current so this current of IDS2 is acting like a source current or the bias current for this mirror okay so if you want further go down for another N channel requirements ahead you bring this instead of R now same current can go to the next N channel block and you can run through so what can I do for example this is 10 let us say this is 10 and for say reasons this is double the size this is 20 let us say this is 40 now this is 40 and if I double it this is 80 so do not jump from 10 to 80 in one go is that correct do not jump that means do not put W by L2 equal to 8 here to make it 80 mic 80 currents 8 times current why what is the problem if I make W by L 8 times what is the problem no the major worry probably is the capacitance is there is that correct capacitance is there the another problem is in layouts as we call what is layout issue layout means sizing if you do what is the aspect ratio do you know length and width length by width is called aspect ratio if something is aspect ratio is like this and some as like this then any drawing scheme will make error on one or the other is that correct so typically devices should be of same aspect ratio close aspect ratio is that point clear to you this is graphic problem not really a problem of device but graphically when I h a line which is 0.1 micron and 20 micron length I will have much more errors to maintain get to that length all about 0.1 everywhere instead if I have 1.1 1.1 and accordingly adjust then I can get more accurately the ratio which I am looking for is that clear this is called graphic problems on chip okay and therefore layouts when you draw you do not put larger device in one go parallel them if possible as many as if you wish to increase W by L is that correct this is essentially paralleling it also distributes the power so that it does not consume at one point huge powers is that clear to you so therefore P to N into P is a normal method of jumping from low currents to high currents is that clear to you please take it that if you make a spice simulation with 8 and you get and you extract and it comes back do not get satisfied because you are not done thermal analysis in actual chip that thermal part will appear anyway okay whether you like so the chip may on a circuit may work but in real life it may not or as good okay I would not say to not and therefore these issues should be thought applying so these are design issues this is nothing to do with actual mirror mirror could have been simple water ratio you want but in design one must think how many ways we should go so that it is universally acceptable values which you can get okay I agree but eight fingers still are in parallel capacitance so they are adding their power just heat problem probably is minimized but the capacitance problem is not minimized because they are at the same node all capacitance this actually distributes the capacity graphic it can solve that once you are individual that is what fingers do now that they solve the aspect ratio problem but the capacitance at that node is still some of them okay whichever you do okay is that okay is that okay now there is an issue which we must look into before we proceed further the issue comes that how much is your so-called transistor m1 m2 are identical because all the mirror was talking is W by ratio only okay or vt's were common or they so common so how much is the mismatch between the two transistors or number of transistors you are going to use will decide some way the accuracy of current mirrors so what I am saying if there is a variation and I have taken a simple case I am going to solve for a plus minus variation equal variations and figure out what is the percentage of variation at the output current if these devices change by so much let us say 5% so is the current ratio changes by 5% 3% error what is the percentage error if this inaccuracy as a designer I am now worried because I am shrinking everything and I am worried how much accurately I am doing that this is an issue which as I say now has taken into prominence because we have started worrying about inaccuracies the inaccuracies come from varieties of age which are called variability issues in process and they cannot be handled by anyone these are there for those who are devised background to some extent there is a fin fed so there is something called the thickness of the fin there is also a spacer thickness there is also the length up to which the spacer ends there are seven parameters which we govern on fin fed design now which one is dominant we do not know because all of them may vary with all processes so nowadays there is an issue which one should be controlled better than compared to all others and there is an issue which is now worrying every 90 nano 45 nanometer down people one good news always something goes bad luck favors you as you go for 16 nanometers down or 12 16 or below the scaling law has changed now it is not really scaling say for example if you see this is additional features just I will come back we were thinking that oxide thickness is scaling like this as years actually it is not now it is like this so much of my worry has actually reduced in 16 nanometers so game and I say happen people are smarter than the device but device because at then much smarter we are trying to understand the process and the circuit relationship and then the performance in system and we are trying to get some kind of what we call thumb rules what are thumb rules they are no real legal status okay so we say VT varies by delta VT by 2 beta dash varies by plus minus delta V dash by 2 lambda varies by delta lambda by 2 for M1 and M2 is that okay figure drawn I was drawn the next slide will actually explain what I meant this analysis is not new this is done many years here also it is not that I am doing only I am doing it for you right now here this is a very common analysis and this is not true only for this device this is true for everywhere whichever variation this is how one solves the sensitivities is that okay everyone okay so we write based on the analysis based on the thinking I said beta 1 dash is beta dash minus delta beta dash by 2 whereas beta 2 dash is beta say beta dash is an average value over which one is less than delta beta dash by 2 the other is plus delta beta dash this is only the variation so what is the net variation delta beta dash but half is given here and half is given there similarly for VT similarly for lambda and now I take the ratio of I0 to IDS 1 this is my beta 1 dash okay into sorry beta 2 dash into VGS minor right now I am assuming VTs of this kind sorry this kind so is that correct VT is average value plus delta VT because this is subtracted this is minus square 1 plus lambda VDS plus delta lambda by 2 VDS the IDS 1 current follows the 1 1 values beta dash minus delta beta dash by 2 VGS minus VT plus 0.5 delta D square 1 plus lambda VDS minus delta lambda by 2 VDS minus comes because this is minus I take out this big turn out I take beta dash from here I take VGS 2 times VGS minus VT outside here okay and from here I take 1 plus lambda VDS here from each of them the first two terms I take out so that becomes beta dash into 2 VGS minus VT square plus 1 plus lambda VDS now for this the term when you take beta dash out is 1 plus delta beta dash by 2 beta dash 1 minus delta VT upon 4 VGS minus VT square 1 plus delta lambda VDS upon 1 plus lambda VDS and opposite sign correspondingly is this however these two values are same okay so they can be cancelled this is taken only to remove something from denominator or numerator is that okay just each part common terms I removed so that I can remove those terms is that okay is that okay so sorry you can redo yourself wish that that the cancels term after that you get 1 plus delta beta dash by 2 VT 1 minus delta VT square plus 1 plus this divided by minus signs correspondingly opposite some that however 1 minus delta X by X to the power minus 1 if delta X is much smaller by binomial expansions it can be written roughly equal to 1 plus delta X by X okay so 1 minus delta beta the what I am doing it now so I get I 0 upon IDS 1 is 1 plus delta beta dash by 2 beta square 1 minus delta VT upon this to the power 4 into 1 plus lambda VDS 1 assumption is the delta stands are much smaller which is why they are called delta and binomial expansion is valid all higher terms are neglected then I expand square terms something square I can write a square plus p square plus 2 a b or minus 2 a b whichever is a minus b or a plus b so I expand this I expand this I expand this okay then what did I say what do what I say if delta is small all delta square term is still smaller so which holding yet is like yeah yeah right to push number simplify expression digs I say or you do yourself and verify but this whole trick I am using is to prove that if I want to calculate I should get a very simple expressions so a delta square terms delta square terms are delta square terms are neglected by me as I say this numbers should be maybe right also just check the numbers if there are two just use two if there are four use four a plus b or a minus because square square a square plus b square minus 2 a b or plus 2 a b nothing great no maps is that okay all of you so if I do that I neglect those this term I get this expression lot of game I play you look at this last before you write the first line 1 plus 2 lamb 2 delta lambda VDS by 1 plus lambda VDS I say okay lambda VDS is normally larger than 1 VDS is more so I neglect one and if I neglect one I can calculate remove VDS then I say I get 1 plus 2 delta lambda by lambda but delta lambda by lambda is very small so I neglect that also then you can keep them but this is how I quick calculations if you want to do how much you will figure it out how do I do okay so if I keep doing this analysis I expand this I multiply these two terms this I became I removed it because I say 1 plus 2 lambda by lambda is 1 so I get final expression is you can read right by then was see 1 plus delta beta dash by beta dash minus delta VT VGS minus VT minus delta beta dash by beta delta VT upon this okay if I take delta VT by VT out delta like doing this delta beta this why I write delta VT by dt delta what is that way I am telling then the percentage I can actually declare so I just do tricks on that so to say if you have function variation within plus minus 5 percent the I 0 to ideas ratio will be within 4 percent of error these are for a specific values you may get more earlier depends on VGS minus VT is used and yeah only VGS minus VT is yes dominant you do see the term minus may not it's like a little more walkily term plus a number so pass this is a brand of pass percent why I take half percent back because there is a 4 percent you got it this may be 5 percent this may be totally have 1 percent so 4 percent error you are going to get if 5 percent error you see in the VTs or in sizes or in details that okay so this is how one evaluates the errors because this is something very crucial how much accuracy I am holding when I say I am mirroring it is that clear how much accurately I am mirroring so these numbers are not really great or something just to tell you that don't believe that exactly transfers it does not okay and depends on the values it may be even more or sometimes even less is that okay so we will continue with this