 Namaste, I am Mr. S.S. Shakapure, Assistant Professor, Department of Computer Science and Engineering, Balchan Institute of Technology, Solapur. My today's topic is Programmable Interrupt Controller and the IC is 8259. So my learning outcome here at the end of this session to understand interrupts and their use in a microprocessor based system. What is Programmable Interrupt Controller? In short we call it as a PIC. The Intel 8259 is a Programmable Interrupt Controller designed for the Intel 8085 and 8086 microprocessor. So here we want to say the 8259 is very much compatible for Intel designed 8586 architectural processor and the Intel 8259 Programmable Interrupt Controller handles up to 8-vector priority interrupts for the CPU. Here the number of 8 different interrupts at a time we can ask for the request at CPU and it is a cascadeable for up to 64-vector priority interrupts without additional circuitry. That means we can handle three different kind of 8259 Programmable Interrupt Controllers in the cascadeable form and because of this the number of 64-vector priority interrupts can able to manage and the IC is 28 pin package. The 8259 is designed to minimize the software and the real-time overhead in handling multi-level priority interrupts. If you are looking 8259 pin configuration so as we discussed in our previous slide 8259 IC is of package of 28 pins and out of 28 pins we will check out one by one the functions of different pins. So here in the given table we will come to know the functionalities of different pins. The pin from D0 to D7 that is from pin number 1124 or D0 to D7 bi-directional tri-strated buffer data lines and connected to the data bus directly or through buffers. And about the CS bar that is pin number 1 CS bar is active low chip select, RD bar and WR that is pin number 2 and 3 are the active low read and write control signals respectively and the next pins that is pin number 12, 13 and 15 it is a CAS0, CAS1 and CAS2 are the very important pins and these are the cascadeable bi-directional which used in a master mode PIC place slave ID number on these lines and in slave mode the PIC reads slave ID number from master on these lines and it may be regarded as slave select. Now about the one more pin SP slash EN is very specific pin which is actually used to select either of one cascadeable line that is CS0 CS1 or CS2. So it is a slave program enable in non-buffered mode it is SP bar input and used to distinguish master slave PIC and in buffered mode it is output line used to enable buffers. Now our next pins are that is pin number 18 to pin number 25 and they are IR0 to IR7 what exactly it is these are IR synchronous interrupt request input lines and these are generated from peripherals. Now about the two control lines INT and INTA INT is a interrupt and INTA bar is interrupt acknowledgement received active low from processor. Now about the next one more important pin that is pin number 27 is A0 it is the address input line used to select control register. So like this we can see the different functions of different individual pin of A259 IC about the A259 block diagram if you are looking the A259 block diagram the internal data bus which we are looking here and the right side of this so this block diagram we divided in two parts one is the right side of this internal data bus and one is left side of this internal data bus and we can able to see here the different functional blocks and these functional blocks are different registers which helps to receive the different interrupt request arrived from the peripherals and we have a control logic which is used by the microprocessor and also we have the different buffer blocks like data bus buffer, rewrite control logic and cascaded buffer here in the block diagram now we find the different registers like IMR that is interrupt mask register and interrupt request register and service register so what exactly these are and also the left side we find data bus buffer, rewrite control logic and the purpose of these buffers are like they used to configure the internal registers of our chip. So now if we are observing our block diagram regarding the different registers like IMR, ISR, IRR about the block diagram of A259 the IRR register is used to indicate all interrupt levels requesting services so here in this particular register block we collect all the interrupt request in the priority resolver this is a block where we use to resolve the priority of this particular request and the highest priority is selected and the strobe into the corresponding bit of the ISR during INTA sequence. So in service register is used to store all interrupt levels which are currently being served and about the IMR is used to enable or mask out the individual interrupt inputs through bits M0 to M7 so 0 is used to enable and 1 is used to mask out. Now about the different interrupt request one or more of the interrupt request lines that is IR0 to IR7 are raised high setting the corresponding IRR bits they to find in evaluates these requests in the priority resolver and sends an interrupt to the CPU if appropriate. And the CPU acknowledges the INT and responds with an INTA pulse during the INTA pulse the appropriate ISR bit is set and the corresponding bit in the IRR is reset. So I have a question please think and please try to write the answer the register that stores all the interrupt request is in order to serve them one by one on a priority basis is I have the four options like interrupt request register, in service register, priority resolver and interrupt mask register. So your answer is A the interrupts at interrupt request input lines are handled by interrupt request register internally. Now about the left part of the A to find in block diagram that is if we are considering about the cascading buffer cascading buffer comparator it sends the address of the selected chip to the slave in the master mode and decodes the status indicated by the master to find own address to respond. So in the particular cascading buffer we can able to add the more number of A to find nine ICs and because of which we can try to raise the number of interrupt request to the microprocessor. About the data bus buffer this three straight bi-directional 8 bit buffer is used to interface the PIC to the system data bus control words and status information are transferred through the data bus buffer. About the rewrite control logic this function of the block is to accept output commands from the CPU it contains initialization command word register and operational command word register restores the data various control formats for device operation. About the summary part A to find nine is designed to minimize the software and real time overhead in handling multi-level priority interrupt and the Intel A to find nine programmable interrupt controller handles up to eight vector priority interrupts for the CPU and requires a single plus five volt supply. And these are what my references thank you.