 метञिक्त्रेंट, लचрезदाशाका, जीनक्रेर्स्ती, सेईन्हेंηνिस10 Ego supervised 6 मूहारिस भी साथ साथ सी उक्तिमातोर् spouse मखन में फीशन्ही भनिलिक् 쓰्मट्दार्नें Where you discuss about operating characteristics of transistors, or gates. क्नुव्ंस्म किस webinar 4 में दोबारासि जी क्चाने हमृार है। Theme should be discussed in detail. आब बंबाद आज उडिव रहे है, अरार दागर पीछ अज देवत नहीं कर दीशां इसमें पहाँट लुचिक रहाँ रहाँ, उगर टीट कर रहाँ चाो रहाँ आप बशॉत, आप नहीं पहाँट लुचिक तुछ पवाहम कर लुच्या शिर तकते है छिए जाए, तक अठ so in this lesson two to three questions were given in the session. First question was get, that if you are asked to implement a small calculator which gemultiplies, divides add sub-track operations So that the calculator, the arithmetic unit in can act so quickly to perform operations in class. So basically the answer is, that it bases in the written field which is one of the uncertainty या और गेट, या और गेट, या जो भी गेट, उस सर्ट केट में यूज हो रें, वो कितनी जल्दी सूईच करते हैं आसमें. तो अगर वो जल्दी से सूईच करेंगे, ज़ाद अप्रेशन्स होंगे. तुशा कुछन ज़े था, क्या आप एक अर्ठमाटेक यूँट, या एक खल्कौलेटर बना सकते हैं, जो बहुत खम्स्पेस अक्यपाय करें और मैं आपनी जेप में रख सकूँ, और पावर रेखवावें वी उसकी काम हों, बैट्रे से चल सके अस में. अस माल और कुऄ पावर रेखवावें जो है, पर वो आपनी और से मोस तेकनालची की लो है, तुशी मास ज़िर किष जितनाः भी हैं, बैट्रे के साध इंटेः साथ तुशी अप्रेट हो सकते हैं, लाज पावर सब्लाई नहीं जाएव। अआदे ख्बोरी l are chez सी मोस्से लगात्ठा लगात्ठा ambitions are same as ttl ज़ी ल के सी मोस्से लल्गात सावाद मनी आउज्टे Ksishaa represent it useful for अज्टे ख्बोरीね। Corona times are comparable for व में सेकिन यज्टे खवी ली सेनाई ... आप बऑइ, धिए वान क्सस्ल ज़ी सोगातawl for trading you were discussing अप थोत नाज़ात है। धूर्दे नाज़्ात चुछैई क Frequhornmeer नाज़ात नाज़ात कुछास हूँई कोन भी वी ज�ảiक। � att पुछदिव इसकी वी बाश्टर लगान शाथा। अप प्र स्उछिख में प्र इसंगन कि वीशाउगि चालगे कर पीचनि कर अपको आप को फस क्षव्चिंट शबिट से प्रवहाँट कर पहल... वह ख़ब के कोई बिगाइंद है, अन से लि कोई लिएंखवाण के राठक च्टाँ की अई भी रवाचाए... आखह को बहँत ख़्देजी से आपको लिएंगवाडा स्थाचन एक। you would use ECL technology Memories, fast memories, fast data access you would be using ECL technology to implement the memory इसी तना अगर अपने data transmit करना है बोद देजी से transmit करना होस में then of course again you would use ECL technology फिर में बात की ती PMOS and ANMOS similar technologies है basically in technologies you can build complex circuits in a very small space so your microprocessors in which there are very big circuits or very complex circuits you would implement them with PMOS or ANMOS technology Memories again they occupy large rather they have very large circuits to implement them again you would use this technology their power requirement is also less the last technology we talked about was the E-square CMOS it's a combination of CMOS and ANMOS technology इस को में गया देजी लिए use करते हैं the PLD's programmable logic devices when we talk about gates in addition to its function we also need to know about its operating characteristics operating characteristics वोई वली बात है के जो आपका अपका अर्ठमातिक सरकित है वो कितनी जलती आपका results अपका जो सरकित है वो कितनी फ्रिक्वेंसी के अनपृट्स केपिवेल है प्रोस्सिंग के इसारी बातें जो है इंपोट्डनत है वैं जो दिसाँन इस सरकित इसके इस्के इजम्पल वोई गाडी वाली है अप शुव है विकार बास एक बडी गाडी होनी जाए पारोफल लंजन होना जाए तो आद माइद भी एबल तुट्ड़ावल 300 किलमेटर से तुवाबस तो इसी च्तर है वो कितनी गाडी वो कितनी बातें सरकित प्रोस्सिंग केपिवेंसी केपिवेंसी अद of the capability of the gates के किस विकार में कर रेए कितनी power dissipation है किस frequency बे काम गरते है न all that अपने different parameters कों करक्तराईष एक गीत टे विकार दे वाद आप वेद यह अप बढी होगा अप रेड नहीं करक्रिस्टिकष अफ ए कीट पला जो वो करक्रिस्टिक ता अरद्यागलाई करएट्तिद, अरद्याई बास्टिबकर्ठीद लिए तीस्यँर न्यद है, अरद्याई थी की लिए चिर्ँटीगी रब जवदती अगे बाद्ह लाई आए, यसाथ भगी जिनुष प्रश्डुपर औरद्याई की खॉप्ताआ, अर वर दिस्छीपेहत करता हैं, ever dissipate karta in the form of heat. तो हर सेर्गेट की, hr serget ki heat, रदर पावरटिस्पेशन करता है, rather power dissipation kıतनी है, different frequencies pe अपावरटिस्पेशन अपावर्टीसे लेख।, faur dissipation effect hoti hai, कि नहीं को मैही? we would be looking at that.। उभी आकिन्खचट जी स्व़र्च्च टल्गान।ographer वोल्टेकocolate йो Compare पने। there is a CMOS series which requires a DC supply voltage of 5 volts and there is another CMOS series different switching speeds and different power dissipation. In the last lecture, we looked at codes to identify different gates. For example, 74xx00 was used to identify a quad to input NAND gate. The xx part we said represented the switching speed and the power dissipation of a gate. Let us look at the TTL series which requires a plus 5 volt DC supply. The standard TTL series is represented by the code 74xx part is missing. So a NAND gate implemented the standard TTL logic would be 7400. There is another version of the TTL NAND gate known as the Schottky TTL. It is represented by the code 74xx00. S represents Schottky. Again there is another version the 74xx00. AS represents advanced Schottky. There is yet another implementation the 74xx00. So LS represents low power Schottky. A core implementation is the 74ALS00. ALS means Advanced Low Power Schottky. The standard the Schottky the Advanced Schottky the Low Power Schottky and the Advanced Low Power Schottky and there is another version the Fast TTL 74F00. These series are characterized by their switching speed and power dissipation. The standard TTL is the slowest and consumes more power and the Advanced Low Power Schottky has the fastest switching speed and low power requirements. Let us look at the CMOS series. As we had said there are two types of CMOS series. CMOS series which requires a power supply of 5 volt and CMOS series which requires the power supply of 3.3 volts. So let us first look at the 5 volt series. This may have code 3 different versions may laying 74HC00. That means it is an AND gate HC means high speed AC 74AC00 is the second version that is the Advanced CMOS or 74AHC00 that is the Advanced High Speed version. So 3 versions again they operate at different switching speeds and they have different power dissipations. Again we will look at them in detail later. There is another version 74HCT 74ACT and 74AHCT. T which represents that means it is compatible with TTL. By the way CMOS or TTL there are two different series so they do not have compatibility but you have gates which are designed to be compatible. Let us look at the 3.3 volt CMOS series. This may be three versions in different power dissipation and different switching speeds. So the first one is 74LV so LV means low voltage CMOS. The second version is 74LVC again it is a low voltage version of CMOS which requires a power supply of 3.3 volts. The last version is 74ALVC which is the Advanced Low Voltage CMOS. So Advanced Low Voltage CMOS's power dissipation is lowest in 3 of them. We have just looked at the TTL family and CMOS family of logic gates. TTL family uses 5 volts and CMOS series uses 5 volts and 3.3 volts. Let me ask you a question. Suppose I asked you to design a circuit which you can carry around in your pocket or that battery can operate correct. So which logic family would you use? Basically you would use the 3.3 volt CMOS series because its power requirement is low as compared to the 5 volt CMOS series and the 5 volt TTL series. Now let us talk about the noise margin. First of all I have repeated the noise margin. On different logic levels a digital circuit operates 5 volts or 0 volts or 3.3 volts or 0 volts. When you connect a lot of circuits or gates together then the voltage level changes. So we have to know how much change is acceptable for that circuit. So logic 1 level can be represented by 5 volts, perhaps it could be represented by 4 volts, can it be represented by 3 volts. Similarly logic 0 can be represented by up to how many volts it has. Second important point was that when external noise is generated it affects the performance of an electronic circuit. What is that electronic noise? Ok you must have seen that when you are watching TV on television, there is some electricity or you are driving a motor at home, then the interference is seen in the picture. Basically an electronic noise is generated which is being added on the TV signal and you can see that there. Now if we look at the digital logic it works with 3.3 volts, 0 volts, 5 volts or 0 volts. If you add noise to it then what will happen? Digital logic circuit will stop working. So let us look at the noise margin and what are the actual noise margins, how much noise can be tolerated. Let us have a look at TTL logic gates. The diagram shows the input voltages applied at the inputs of TTL gates and the output voltages at the output of the TTL gate. At the input of any TTL logic gate a logic high signal 1 or a logic low signal 0 is applied. The V IH which represents input high voltage is the input voltage range of logic high signal with a range of 2 to 5 volts. That means at the input of any TTL gate you can represent a logic high with a voltage ranging from 2 volts to 5 volts. The minimum voltage to represent logic high is 2 volts which is represented by V IH minimum. The V IL the input low is the input voltage range of logic low signal with a range of 0 to 0.8 volts. The maximum acceptable input range to represent logic low signal is 0.8 volts represented by V IL maximum. Similarly the output of any TTL logic gate can be at logic high 1 or logic low 0. The V OH or the voltage output high is the output voltage range of logic high signal with a range of 2.4 to 5 volts. That means any TTL gate when it gives a logic high output it is represented by voltages in the range of 2.4 to 5 volts. The minimum acceptable voltage which represents logic high at the output is represented by V OH minimum and it is of course 2.4 volts. The V OL the output low voltage is the output voltage range of low logic signals with a range from 0 to 0.4 volts. V OL maximum is the maximum acceptable output range for logic low signal which in this case is 0.4 volts. Consider that the output of an AND gate is connected to the input of an OR gate. What are the voltage ranges for the two gates? Now for both the AND gate and the OR gate the input logic high would be represented by voltages ranging from 2 volts to 5 volts. The input logic low would be represented by voltages 0 to 0.8 volts. Now the outputs of both the gates would be represented by a voltage of 2.4 volts to 5 volts for logic high. A logic low at the output would be represented by voltages ranging between 0 to 0.4 volts. Any voltage in between 0.4 volts and 2.4 volts at the output is not allowed. Similarly any voltage between 0.8 volts and 2 volts at the input of any gate is not allowed. Let us now consider the CMOS logic levels. Let us first consider the CMOS 5 volt series. At the input of any CMOS 5 volt series logic gate a logic high signal 1 or logic low signal 0 is applied. The VIH the input high is the input voltage range of logic high signal with a range varying from 3.5 volts to 5 volts. The VIH minimum is the minimum acceptable input range or voltage for a logic high signal which is 3.5 volts. The VIL is the input voltage range of logic low signal with a range varying from 0 to 1.5 volts. The VIL maximum is the maximum acceptable input range for logic low signal which is 1.5 volts. Similarly the output of any CMOS 5 volt series logic gate can be at logic high 1 or logic low 0. The VOH is the output voltage range of logic high signal with a range varying from 4.4 volts to 5 volts. The VOH minimum is the minimum acceptable output range for a logic high signal which is 4.4 volts. The VOL is the output voltage range of logic low signal with a range varying from 0 to 0.33 volts. The VOL maximum is the minimum acceptable output range for a logic low signal which is 0.33 volts. Now let us consider the CMOS 3.3 volt series. At the input of any CMOS 3.3 volt series logic gate a logic high signal 1 or logic low signal 0 is applied. The VIH is the input voltage range of logic high signal with a range of 2 to 3.3 volts. The VIH minimum is the minimum acceptable input range for a logic high signal which is 2 volts. The VIL is the input voltage range of logic low signal with a range of 0 to 0.8 volts. VIL maximum is the maximum acceptable input range for a logic low signal which is 0.8 volts. Similarly the output of any CMOS 3.3 volt series logic gate can be at logic high 1 or logic low 0. The VOH is the output voltage range of logic high signal with a range varying from 2.4 volts to 3.3 volts. VOH minimum is the minimum acceptable output range for a logic high signal which is 2.4 volts. The VOL is the output voltage range of logic low signal with a range of 0 to 0.4 volts. Finally the VOL maximum is the maximum acceptable output range for a logic low signal which is 0.4 volts. The two CMOS 5 volts and the 3.3 volt series cannot be mixed. They are treated as separate series and separate gates. Again if you have an AND gate its output is connected to an OR gate. What would be the input and output ranges? Well they would be identical. If you are using a 5 volt CMOS AND gate and an OR gate both their inputs would vary from 3.5 volts to 5 volts for logic 1. And they would be varying from 0 to 1.5 volts for logic 0. Similarly the outputs of the AND gate and the OR gate would be varying from 4.4 volts to 5 volts for logic 1. And they would be varying from 0 to 0.33 volts for logic 0. Similar is the case for the 3.3 volt CMOS series. Now let us consider the behavior of an AND gate when an external noise is added to its input signal. Consider the CMOS 5 volt series AND gate. Input A of the AND gate is permanently connected to logic high of 5 volts. Input B of the AND gate is connected to the output of some other gate. The signal at input B of the AND gate can vary between logic 0 and logic 1. Consider that the input B is at logic high state with VIH equals to 4.2 volts which is within the valid voltage range of VIH which should be between 3.5 volts and 5 volts. Consider a voltage generated due to some external noise added to the 4.2 volt signal. A sharp dip in the input voltage due to the noise brings the input voltage down to 3 volts for a very short duration as can be seen in the figure. The 3 volt input is below the minimum input voltage limit of 3.5 volts for logic high input voltage. What would be the output of the AND gate? Well, this dip in the voltage even for a very short duration will result in an unknown output. It could be logic 0 or logic 1. Therefore, due to this added noise the AND gate malfunctions. Consider another example. Consider two AND gates connected together. Both are the CMOS 5 volt series AND gates. The first AND gate has both its inputs connected to logic high. Therefore, the output of the gate is guaranteed to be logic high. The logic high voltage output of the first gate is assumed to be 4.6 volts which is well within the valid VOH range of 4.4 to 5 volts. Now, assume that the same noise signal as the signal used in the previous example is added to the output signal of the first AND gate. The sharp dip due to noise brings the VOH voltage down to 3.4 volts with reference to the VOH of 4.6 volts signal. In the previous example, the reference signal or the output signal was at 4.2 volts. In this particular case, the VOH signal is at 4.6 volts. So, the noise signal instead of dipping to 3 volts would dip to 3.4 volts. The sharp dip due to noise brings the VOH voltage down to 3.4 volts with reference to the VOH of 4.6 volts. 3.4 volts is lower than the VIH minimum of 3.5 volts required by the input of the second AND gate. Thus, the circuit will malfunction. Since VOH minimum is guaranteed to be at 4.4 volts, therefore, a noise signal being added to 4.4 volts can bring VOH voltage down to a minimum of 3.5 volts which is the acceptable minimum range of VIH. Anything below 3.5 will cause the second gate to malfunction. Now, let us describe the high noise margin and the low noise margin for the CMOS 5 volt gates. In the example discussed, you have two gates AND gates connected together. The first AND gate has a high logic output. The minimum acceptable voltage from the diagram is 4.4 volts. This output is connected to the second AND gate's input. Now, the input logic of the second AND gate has a minimum acceptable voltage of 3.5 volts. If it is lower than this, it will not be recognized as logic 1. Now, the noise margin is 4.4 volts minus 3.5 volts minus 0.9 volts. Now, let us see how the output of the first gate should be at a minimum output voltage of 4.4 volts. Let us suppose that there is a noise added to the second gate and the voltage of the second gate is at a minimum output of 4.4 volts. Now, the input voltage of the second AND gate is at a minimum output of 4.4 volts. The minimum requirement for logic 1 is 3.5 volts. So, the output voltage of the fourth gate is 4.4 volts. Now, how far can we go with the output of the fourth gate? If it is up to 3.5 volts, then the second AND gate will operate properly. If the voltage is less than 3.5 volts minus 4.4 volts, that is less than 0.9 volts, then it will not be accepted. Similarly, the noise margin is low, that is, if the logic is at a low output of the AND gate, and the second gate of the AND gate should have acceptable range on its input. It can also be calculated as VIL maximum minus VOL maximum. So, VIL input low maximum is 1.5 volts and V output low maximum is 0.33 volts. So, the noise margin is 1.17 volts. Now, if you compare the noise margins for the 3.3 volt series, the high noise margin is 2.4 volts minus 2 volts, you get 0.4 volts. The low noise margin for the 3.3 volt CMOS series is 0.8 minus 0.4, which gives you 0.4 volts. So, the high noise and low noise margins are both 0.4 volts. TTL noise margin can be calculated similarly, the high noise margin is 2.4 volts minus 2 volts, which is 0.4 volts. Similarly, the low noise margin is 0.8 volts and minus 0.4 volts, which is again 0.4 volts. We have just calculated the noise margin for CMOS 3.3 volt series, CMOS 5 volt series and TTL 5 volt series. CMOS 3.3 volt series or 5 volt series should have the noise margins high and low 0.4 volts. CMOS 5 volt series should have the low noise margin 0.9 and it is the other way around. High was 0.9 volts and the low noise margin was 1.17. Now, let me again ask you a question. If you have a logic circuit based on CMOS or TTL, if you have a noisy environment where external noise is generated, what circuit will perform better? Well, the answer is the CMOS 5 volt series version because its noise margin is more than 0.9 volts and 1.17. TTL 5 volt or other CMOS whose noise margin is 0.4 is not so reliable in this. Let us now talk about power dissipation. Power dissipation we said is that whenever you have an electronic circuit, it requires some power and that power is consumed in it. Now, how much power it consumes, that is important. Because if a circuit is dissipating more power and generates more heat, then it has to be kept in a way to dissipate the heat. If you open the computer and see, there is a fan on your microprocessor that is dissipating the heat in it. Power dissipation also increases with frequency. So, let us first look at TTL gates and their power dissipation. How do we calculate the required power? Basically, if you remember, it is voltage into current. So, these two products gives you the power required by that circuit. When you have a logic gate, any gate, its output is not constant. Sometimes it will be 1, sometimes it will be 0, sometimes it will be 1, sometimes it will be 0. So, when its output is 1, it needs more current. When its output is 0, it needs less current. So, that means current requirement of a gate varies with the output and the inputs applied. So, average power to calculate the current concept formula. Again, it is the product of voltage and current. Current is 2 types of current. When output is high, you have a high input current. When the output is low, you would have a low input current. Where is this current coming from? The power supply you have connected. So, take the average of these two. Multiply it by voltage. That would give you the power dissipation. So, this is the case for TTL circuits. CMOS circuits have different behavior. CMOS gates have a capacitor based load. If you have read your circuits, each circuit drops or requires some current which is dropping its internal resistance on it. CMOS gates have an internal load represented by a capacitor. So, if you remember the capacitor, you have to discharge it. So, when the current is discharged, the voltage drops. Now, if you increase the frequency of a CMOS and a gate, its inputs vary very fast. So, that means the internal capacitor is discharged very fast. That means the power dissipation for a CMOS gate is variable. It depends on the frequency. Let us first look at the power dissipation of a TTL AND gate. The AND gate chip is shown in the diagram. PIN 7 is connected to ground. PIN 14 is connected to VCC 5 volts. One of the AND gates has two of its inputs connected to plus 5 volts. What is the output of the AND gate? It is high. What is the current drawn by this gate? It is represented by an high current ICC H. Now, if one of the inputs of this AND gate is connected to zero, the output would be zero. It would draw out a current ICC low. So, if the output is high, it draws out a high current ICC H. If the output is low, it draws out a current ICC L, which is low. Now, let us suppose the inputs of the AND gate are continuously varied. So, they are changing from one to zero. So, that means the gate would be drawing high current and low current continuously. So, what is the total power required? You need to calculate the average. So, the formula is P which is equal to the voltage, the supply voltage into the average of high current ICC H plus the low current ICC L. Let us now consider the power dissipation of a CMOS series logic gate. As I said earlier, the power dissipation of a CMOS gate varies with frequency. So, for a typical HC MOS gate, a CMOS gate, under static conditions, it requires a power of 2.75 micro watts. But at a frequency of 100 kHz, it requires a power of 170 micro watts. So, let us see how power varies with frequency. As we said, the CMOS-based gates have an internal capacitor-based load, which is charged and discharged. The CMOS-based gate is also connected to another CMOS gate and that particular gate represents a capacitive load. So, the power requirement of a CMOS gate is represented by the equation CPD plus CL. These are the two capacitors, the internal capacitor and the load capacitor, the external capacitor multiplied by the square of the supply voltage, which is VDD and multiplied by the frequency at which the circuit is operating. Therefore, the power dissipation depends on the frequency. If the frequency increases, the power dissipation also increases. We have just looked at the power dissipation requirements of a TTL gate and a CMOS gate. CMOS gates have the advantage that when the operation is not there, or if there are very few operations, the power requirement is minimal. The more the operation increases, the more the power requirement increases. So, let us consider a laptop. Laptops operate through your batteries. When you are working, then there will be more operations and more power requirements. When you are not working, the power requirement is very low. If you compare CMOS with TTL, the power requirement of TTL is more compared to CMOS. Let us now consider another important operational characteristic, the propagation delay and the frequency response. Propagation delay, we said earlier that when you apply certain inputs to any gate, it would respond with an output. That response is not immediate on the output. It will come after some delay. You can understand it like this. Let us suppose you go to see a cricket match. There are three ticket houses there. So, there are three lines of people there. The person selling the tickets takes about one minute to get the cash and give the ticket. So, after each minute, each person is taking the ticket and going forward. The other queue, the person is a little slow. So, he takes about two minutes to take the cash and give the ticket. So, that line is going on every two minutes. And the third line, that person is working very fast. So, the given half a minute, he is giving a ticket and why is it going on. So, at the end, the consequence will be big. That is the middle one because there is more delay there. So similarly, in the case of logic circuits, the propagation delay of the AND gate would affect the entire working of the circuit. If the inputs are changing very rapidly and the gate is not capable enough of responding in that particular time, then of course, the output would be delayed. You cannot increase the frequency of the inputs. Let us have a look at the propagation delay with the help of some slides. Let us have a look at the propagation delay of an inverter. The input signal applied to the inverter is shown and the output signal of the inverter is delayed by a certain time. Now, the output varies from high to low with respect to the input. Input is changing from low to high. After some delay, output is changing from high to low. This delay is measured by TPHL, the propagation delay high to low transition. The output is going from high to low. Similarly, when the input changes from high to low, the output changes from low to high after a certain delay. This delay is measured by TPLH. P means propagation delay, LH means low to high transition. Now, for logic gates, usually these two values are the same. For some gates, they are slightly different. The propagation delay is of two values. Where is this measure going from? Basically, the 50% point of the transition is let us consider the input. Low to high. What is low? 0 volts. What is high? 5 volts. So, from where will we measure? 2.5 volts. The middle is from there. You will measure the output of 2.5 volts. Let us consider the propagation delay of an AND gate. The AND gate is shown. The input B of the AND gate is permanently connected to high. Whereas, input A varies between high and low. The output of the AND gate changes from low to high after a delay of time specified by TPLH after the input changes from low to high. The output of the AND gate changes from high to low after a delay of time specified by TPLL after the input changes from high to low. The delay time is measured at the 50% transition mark. We have looked at the two parameters which are used to measure the propagation delay on a high to low transition and the propagation delay on a low to high transition. Practically, let us suppose we have an inverter. Its propagation delay is 100 nanoseconds. That means, the input value will come after 100 nanoseconds. Let us suppose, you are continuously wearing signal applied which changes after every 25 nanoseconds. So, what would be the effect at the output? Basically, properly, it will not operate because the delay is 100 nanoseconds whereas the signal is changing at the rate of 25 nanoseconds. Propagation delays are very important. There is an important parameter through which we compare the performance of different gates. It is the product of speed and power. So, propagation delay into the power dissipation which we have done earlier will give a number of these products through which we can compare that this gate is better or the other gate is better. Now, let us consider the last and important operating characteristics the fan out. The fan out of a circuit basically means how many output gates can we connect to the input gate? Electronic circuits basically need to supply some power for another electronic circuit to work. So, let us suppose 10 gates are connected to a single gate. Would that gate be capable of supplying that much power to the remaining 10 gates? Again, I have discussed an example earlier. We have an example. You have a power line Now, in 10 gates, 10 air conditioners are starting to run. What will happen? 10 current, let us say 10 ampere 1 air conditioner is taking place. So, in 10 gates, you are taking 100 ampere. Where will the power supply come from? What will happen? The power supply generator will be loaded and the voltage will be reduced. That happens. The voltage drops. Similarly, the case with digital logic circuits. So, it is important that we know what is the fan out of a logic gate. How many gates can we connect to the output of a particular gate? If we, let us say, cannot do much, then perhaps we could not implement a certain circuit. Let us have a look at the fan out. Let us do some calculations. Let us consider the fan out for TTL loads. The fan out of a logic gate is the maximum number of inputs of the same series in an IC family that can be connected to a gate's output and still maintain the output voltage levels within the specified limits. The output current at logic high is 400 microampere. It is represented by IOH output high current. The input current at logic high is IIH input high current which is equal to 40 microampere. Thus, a gate at logic high can source or provide current to another gate connected to its output. Similarly, the output current at logic low is IOL current output low which is equal to 16 milliampere. The input current at logic low is TTL the input low current which is equal to 1.6 milli amps. Thus, a gate output at logic low can sync current from another gate connected to its output. It is not going to be sending out current but it would be receiving current from the gate connected to its output. To calculate the unit load that can be connected is based on the formula IOH divided by IIH which is equal to IOL divided by IIL 400 microampere divided by 40 microampere is the same as 16 milli amps divided by 1.6 milli amps which gives you 10. So, you can connect 10 gates to this particular gate which has the output and input current requirements of 40 microampere and 16 milli amps. Fan out for TTL loads consider the diagram shown the output current at logic high is IOH which is equal to 400 microampere the input current at logic high is 40 microampere a gates output can be connected to inputs of a maximum of 10 gates so that 400 microampere can be equally distributed amongst 10 gates the load factor is 10. Similarly, considering the second diagram the output current at logic low is IOL which is equal to 16 milli amps the input current at logic low is equal to 1.6 milli amps a gates output can be connected to inputs of a maximum of 10 gates as 1.6 milli ampere from each of the 10 gates can be sunk by the gate which has a total current capacity of 16 milli amps therefore 10 gates can be connected to the output of another gate. Let us look at the fan out requirement of a CMOS load CMOS loading is different from TTL loading as the type of transistors used in CMOS circuits present a capacitive load to the driving gate when the output of the driving gate input capacitance of the load gate is charging and when the output of the driver gate is low the load gate is discharging as can be seen in the figure when more load gates are added the input capacitance increases as input capacitances are being connected in parallel with the increase in the capacitance charging and discharging time increases reducing the maximum frequency at which the gate can operate fewer the fan out of a CMOS gate depends upon the maximum frequency of operation fewer the load gates greater the maximum frequency of operation we have looked at the fan out requirements of a TTL load and CMOS load CMOS میں ame baat ki fan out hai were dependent hai frequency pe jitna fan out kum karenge utni zyada frequency pe CMOS circuits operate kal sakne number of gates which can be connected to their outputs so now we have discussed the important parameters which specify the operation of any logic gate end bay main ek table up ko dikhana cha raha tha jist main different gates ki different series ki apas main comparison un chala am next lecture mein karenge so we will meet in the next lecture again we would start our discussion by looking at these parameters again we will just simply compare these parameters khayal lo kyi gaya apna khuda hafiz and aslam aleykum