 So, today we will look at transistor parameter extractions namely we will look at threshold voltage extraction, mobility extraction which is a very important parameter when you are talking of transport in a FET. So, in addition to that we will also look at what is called effective channel length extraction and finally, again the interface strip density extraction using a transistor structure not using a capacitance voltage technique, but using a current measurement technique. So, then let us get started with the threshold voltage extraction you know the if you recall the drain current of a field effect transistor is essentially given by this equation. So, depending on again whether you are in linear region or saturation region these currents could be approximated. For example, when you are in linear region we say that the transistor is in linear region you know when V d s is very very small compared to V g s then it is linear region of operation. In other words in linear region if you were to look at I d s versus V d s characteristics you know the current will initially increase in the linear region and hence that is for the small V d s values and hence the name linear region and eventually the current will saturate. And that is when we say we have reached the saturation region we reach a saturation region when V d s makes a transition to this value V g s minus V t at some value of V d s V d s becomes equal to the gate voltage that is applied on the transistor minus the threshold voltage at that point you know the transistor current starts saturating. And the saturation current value is essentially obtained by substituting V d s is equal to V g s minus V t in this equation and hence you know you get I d s at or saturation current value as mu n c ox w by l which is essentially a dimensional parameter and the transport parameter how good is the mobility for the transistor. And now you put V d s is equal to V g s minus V t and you have V d s square by 2 here V g s minus V t square by 2 and hence you essentially get V g s minus V t square divided by 2 that is your you know current in the saturation region. And let me rewrite that here I d s at is mu n c ox w by l V g s minus V t whole square divided by 2. Now notice that you know both in the linear region of course in the linear region one can again make an approximation you can ignore this V d s square term because V d s is so small. So, in the linear region you can also approximate your drain current as what is called I d s linear that can be approximated as you know just this first term mu n c ox w by l V g minus V t times V d s right. So, let me write it here I d s linear is mu n c ox w by l V g s minus V t times V d s I am ignoring the quadratic part of V d s because V d s is very very small. And remember the c ox here is per unit area capacitance it is not the total capacitance in this equation that is the oxide capacitance per unit area. Now notice that whether you look at the linear region current or the saturation region current there is an important parameter which is the threshold voltage here. So, you know obviously it also indicates that if you can do a I v characterization either in linear region or in saturation region from that we should be able to extract the threshold voltage. So, let us see how one can do that now let us look at the V t extraction from linear I d s versus V g s characterization. So, in this measurement technique what you do is that you put V d s as very very small voltage let us say of the order of 50 millivolt very small value on the drain voltage source is of course, grounded and you ramp V g from 0 to some large value 5 volt. What is that value depends on what is the dimension of the transistor of course, if the dimension of the transistor is in 20 30 nanometer with 1 nanometer gate oxide you obviously do not go to 5 volt because you know that operating voltage of the transistor itself is going to be 1 volt or 1.5 volt. You go from 0 volt to in general what I call V d d where V d d is the operating voltage of the transistor the threshold voltage is somewhere in between it is obviously more than 0 for a n channel transistor of course, less than the operating voltage and we need to determine what is the threshold voltage value. So, when you do this measurement what you will end up getting is a characteristics which looks like this typically this is 0 here almost 0 we know that sub threshold current is never 0 in a transistor even when V g is equal to 0 the transistor current is not 0 we have all studied that. Now, I am ramping V g from 0 to some V d d value here this is the maximum value that the transistor can sustain and accordingly you have different values of the current when I plot this in a linear scale the current here looks very very small. Now, what we also note here is that these equations that we are writing for the transistor are really valid only when the transistor is turned on not when the transistor is off only when the transistor is on we write these current voltage equation. That is when I approach the gate voltage value which is very very close to V t obviously you see start seeing departure from these equation whether it is a linear current equation or a saturation current equation when V t approaches comes very close to V g s right you start you know having departure. But if you look at the linear region current what this indicates is that current is expected to be a linear function of V g s when V g s is larger than threshold voltage value. So, then what one could do is that one could look at this ideas versus V g s value and try to extrapolate this linear region behavior this looks almost like a straight line and say that if I extrapolate it is as if that equation were to be true at this value of V g s the current would go to 0 you see and hence I would say that when I extrapolate it I get a value here and that I call as threshold voltage. So far so good, but you see in this equation even though you have this relationship I said that ideas is linear function of V g s I am making an assumption you see here of course, V g s is constant. But I am making an assumption that W L R constant which is obviously true C ox is constant which is obviously true, but more importantly I am making an assumption mobility is constant. When I am ramping this gate voltage mobility is not changing right, but in practice that is no longer the case when you actually ramp the gate voltage as you start increasing the gate voltage to larger and larger value your mobility starts degrading. We have discussed this in one of the earlier classes because mobility depends on large number of parameters scattering due to interface and so on and so forth impurity scattering for example, and it also depends on the vertical electric field if the vertical electric field which is set up by applying a gate voltage becomes larger and larger it will impart the free movement of electrons in the lateral direction right. So, mobility will not be constant. So, in other words what you will invariably see when you do this kind of an I V measurement is that you would not really get a very nice straight line like this, but instead your I V measurement will look something like this. Of course, here it is very small current and here you start having like this. Now, the question is I need to do the extrapolation correct to get the threshold voltage for when V G is greater than V T, but where do you want to do extrapolation? If I do a tangent here that will give a different intercept if I put a tangent here that could give a different intercept and so on and so forth right. So, now there is this confusion in estimation of a threshold voltage. So, a work around for this is what we define as something called peak g m V T extraction what it means is the following. Now, I have got a measurement of I DS versus V G S. Now, based on this I DS versus V G S you also generate D I DS by D V G S versus V G S curve what is D I DS over D V G S it is called a trans conductance of a transistor. You vary the input voltage and you look at the variation in the output current and the variation of the output current to the variation of the input voltage has a unit of conductance, but it is defined on two different ports output port and input port and hence it is a trans conductance. So, once I have I DS versus V G S I can very easily create D I DS versus D V G S plot and that will look something like this typically if you actually do this in the lab the trans conductance this is what we call g m or trans conductance. And what this procedure tells us is that you do a I D V G measurement and from the I D V G measurement you also create this trans conductance curve and you locate the point where trans conductance goes to a peak and go to that point on this axis on this curve rather I DS V G S curve and at this point you put a tangent I mean you put an extrapolation here and if you have this extrapolation done and that will intersect this V G S axis and this is what I call threshold voltage. In other words what this peak g m V T extraction procedure is telling you is to locate a point on I DS V G S curve to put a you know tangent there and sort of do a extrapolation to get you know threshold voltage value. So, this is what is you know very popularly used in all these you know when you do a circuit simulation for example, there is a V T H 0 parameter in circuit simulation and that V T H 0 parameter is typically obtained using so called the peak g m V T extraction. So, this is how we essentially define the threshold voltage or compute the threshold voltage from the curves here. Now, once you have the threshold voltage how do you get mobility? Mobility can be obtained from this d I DS over d V G S right I have already created d I DS over g V G S and if you go back to this equation what is your d I DS over d V G S you differentiate this. So, it is essentially this factor correct times this factor I am differentiating with respect to d V G S. So, you know this goes to unity and this is essentially a multiplication factor for this V G S minus V T H. So, as a result of that my g m that I am computing here the g m is essentially mu n C ox W by L times V DS you know what is the V DS because you are applying the drain voltage for your measurement. And you know what is your W because you printed the transistor and you know what is your L and you also know what is your oxide thickness you know you can extract oxide thickness using C V measurement as I have already told you and you also found out what is g m and from this you can extract mobility and you know you will be able to precisely estimate the mobility of the transistor. And the fact that the g m is going down here and that is essentially a reflection of the fact that mobility is actually degrading as I am increasing the gate voltage to larger and larger value. Now, this is one way of doing a V T extraction and the peak g m extrapolation technique that I mentioned and there is another way of defining V T what is called constant current definition of V T. What we mean by this is that you know rather than doing all this extrapolation we will just say that look when my transistor gives a current of let us say 100 nano ampere I call that as a threshold voltage point and that current can be chosen you know the way based on the experience. You can fix a current if you have to fix a current all you need to do is that look at that current value and you know go to the appropriate voltage value and hence you know what is the threshold voltage value. But, you see the current is also a function of W and L of the transistor right. So, what you do is the current that you choose you normalize that current by W by L ratio. In other words if your W by L of the transistor is more you also have to multiply that current with that W by L factor right only then you will be able to get the appropriate threshold voltage value using this constant current definition. In other words what you are saying is that you are saying that I define V d s as that value let me just. So, let us say I am going to define my constant current as I d s is 100 nano ampere times W by L. What it means is that if I choose a transistor of 1 micron W and 1 micron length I look at a 100 nano ampere current. But instead if I choose a transistor of 2 micron length and you know 1 micron width I would essentially be looking at a 200 nano ampere current because because W by L is large you will get larger current and that will anyway happen right. So, you need to have this factor taken into account. So, then what you do is essentially you look at your I d s versus V g s plot and you say you have chosen this current you know what is the W by L and you get the right current value and you say that look for this transistor whenever I have a value of this current whatever that current I have defined I say that this is my threshold voltage. This is another very simple way of defining a threshold voltage right where wherein you do not have to worry about extrapolation and all that. So, in literature sometimes you will see threshold voltage defined by multiple ways either using a constant current definition or using peak g m V t definition. Peak g m V t definition is the most commonly used practice of extraction of threshold voltage. There is another way of doing this threshold voltage extraction and that is if you recall when we do I d s versus V g s measurement and if you plot that I d s versus V g s with a log scale for current remember this current looks you know this is linear because below threshold current will be exponential function of gate voltage and once you reach threshold the current will be may be linear or quadratic function. If the measurement is being done in a linear region it will be a linear function of V g s if the measurement is being done with the saturation condition it is a quadratic function certainly this quadratic variation is much you know gentler variation compared to the steep variation which is an exponential variation. So, what one could say is that look there is a transition from sub threshold to linear or sub threshold to quadratic I pick that transition point and call that as a threshold voltage. So, then one can define you know then again the question is where will you put that point right. So, what one could do is that may be one could sort of you know extrapolate this and sort of extrapolate this and say that look this is the point of transition below this point it looks like a sub threshold region and above this point it looks like a above threshold region. So, this transition point is my threshold voltage of the transistor. So, this is another way of defining the threshold voltage. So, there are multiple ways one can use and define a threshold voltage and accordingly extract the value of the threshold voltage. As I said this can be done in linear region or as well as in saturation region and similarly this constant current thing can also be done in linear region or in saturation region. And similarly this extrapolation can also be done in linear region or in saturation region except that when you do this extrapolation in saturation region because the saturation current is quadratic with respect to V G S minus V T which we have written here right. So, you do not plot I D S versus V G S you plot root I D S versus V G S that is the only difference because root I D S will be a linear function of V G S because of this quadratic dependence. So, that is the only difference as far as extrapolation technique is concerned for saturation region right. So, the saturation extrapolation you look at root I D S versus V G S and you know extrapolate from that curve and you know as a result of that you get with the threshold voltage and in order to get mobility this is the technique right. You essentially obtain D I D over D V G S and from that you can extract trans conductance and from trans conductance you get the mobility right. And even to get know when we did that we said that you know I know C ox because I have computed that T ox from capacitance voltage measurement right. You need not do that on a MOS capacitor you can do that C V measurement on a transistor itself and once you do the C V measurement on transistor you can get the C ox and you can do the use that C ox in this computation and you can get the mobility fine. So, the next important thing that we need to find out is what is called L effective or effective channel length sometimes also defined as electrical channel length. Now, first of all let us understand you know why is it different from physical channel length. So, now if you look at the transistor remember that you know I have this gate and you know this is what we call gate length which is L G L G is different from L effective you see and then what you do you do the ion implantation and there is a diffusion and eventually your junctions will be found N plus and N plus correct. And what when we say L effective what we are saying is the following I have made this transistor with certain printed gate length which you can always measure if you put this transistor under a electron microscope if it is a nanometric transistor right and you can actually see how wide is the gate physically you can look at it and then you have the junctions, but eventually when you are doing the transistor action by applying the gate voltage you are only varying the conductivity in this region you see. So, this is your effective transistor length which is being modulated only the conductivity of this region is being modulated you cannot modulate the conductivity of this region not this region because it is so heavily doped this is a p region and this p region conductivity is being modulated by applying an appropriate voltage on the gate terminal. So, the question is how will you be able to measure this in other words electrically the transistor looks as if it has this gate length not this gate length because I am not able to modulate this region any way. So, you know this can be computed only if you know what is this lateral diffusion and you know fortunately for us there is a very easy technique to compute that lateral diffusion just by doing a electrical measurement. I do not have to do you cannot do it by the way using a optical or electron microscopy because you know if you are doing electron microscopy as is right this is also silicon this is also silicon there are you know the same material in how will you distinguish the two materials right unless you do some you know very rigorous post processing and try to see you know how much is the diffusion which is taking place laterally it is a very difficult thing. So, what we do here is that in order to estimate this we do the electrical measurement L effective extraction first of all we choose transistors with same W, but different transistors multiple transistors that is not one transistor different L values when I say L here this L is what is there on my mask which I used in photolithography process you know based on that mask I have printed some gate, but I do not know what is L effective, but what I will do is that I will choose this different length transistors and when we write this transistor equation as I d s is equal to mu n C ox by W by L you see in reality it is actually L effective what is the channel length electrical channel length of the transistor which is being modulated and that will essentially determine what is the current and it is this L effective that we would like to compute and as I said if you are in linear region V g s minus V t times V d s right this is a linear region current. So, what I do is that if I before we go to the measurement let us just do some algebraic adjustments here let me compute this V d s over I d s which we also call as R channel channel resistance what is it it is essentially given by L effective from this equation you know V d s divided by I d s is L effective divided by mu n C ox W V g minus V t correct. Now, we want to compute this L effective and what is this L effective by the way L effective is L minus what we call 2 delta L what is this delta L this is delta L there is a lateral diffusion from source side and the drain side these two lateral diffusion are exactly identical they would not be any different because it is all symmetric device anyway fortunately for us you see this delta L does not depend on what is the actual printed length. In other words if I have another transistor here which has not this L g value, but may be a different L g value even in this case this delta L that I have here will be same as this delta L because why is this delta L coming you have an implantation and there is a lateral diffusion right implantation is always at the edge of the gate you see and hence the lateral diffusion whether it is a 1 micron length channel or 10 micron length channel is always the same and that is what is going to help us in getting the L effective value and that is why we are going to choose transistors of different length. So, we choose transistors of different length length as defined in the mask and then on all these transistors we do I d versus V g s measurement at linear region operation meaning by very small V d s value and then we choose when we do that for example I will have curves like this I d s versus V g s for one transistor and then I d s versus V g s for a different length transistor and so on and so forth. So, in all these cases what I will do is that I will choose a particular value of V g s in all these transistors and at that value of V g s I find out what is my I d s and I also know what is my V d s and hence I am calculating R channel at you know for different transistors that I have right because I am choosing V g s minus V t I know V t I know I am choosing V g s I am doing this for the same V g s minus V t value on all transistor. So, I know this I know this anyway right and I do not know L effective I am trying to get L effective, but I am computing R channel. Now, what I am going to do is the following all I am going to do is that I am going to construct a plot of R channel as a function of L and what is this L by the way L is L on mask I know L on mask was 1 micron 2 micron 4 micron right. So, I have 1 micron here let say and for 1 micron I got some R channel value and for 2 micron transistor I got some value and so on and so forth right. I have for multiple transistor measurement I have got all these values right and then what I know I have got different values of these R channel right and then I am going to sort of connect all these and make an extrapolation. So, this extrapolation is coming by actually measuring this resistance on different length transistors. So, what is this telling you all this is telling you is that at this value your R channel goes to 0 and what is the R channel equation R channel equation is this what is this by the way L effective L effective is L minus 2 delta L correct. So, if this is going to 0 then L should be equal to 2 delta L at that point correct in other words when L is equal to 2 delta L L effective is 0 and hence R channel is 0. So, in other words by actually looking at the intercept of this straight line where R channel is 0 I know that this should corresponds to 2 delta L value. So, in other words what I have been able to do is to really get that extent of lateral diffusion in all these transistor and all these transistors the lateral diffusion is the same. Now, then if I want to get L effective for 1 micron transistor I am going to subtract 1 minus this 2 delta L value that is my L effective and L effective for this is again 2 minus this value and so on and so forth. So, that is how you compute L effective value by doing the electrical measurement and from electrical measurement getting the channel resistance and from channel resistance doing an extrapolation for 0 channel resistance and hence getting 2 delta L value. This was quite you know in older generation technology, but in new generation technology there is a problem with this technique and that problem is the following right and that is I made an approximation I am sort of I told you that I do this ideas VDS measurement and I do VDS over ideas and that gives me channel resistance. But in reality it not only gives the channel resistance, but it gives this channel resistance in series with the parasitic resistance correct. Because the way you have we have discussed this there is a parasitic resistance here there is a parasitic resistance here and eventually your drain contact is coming here this is where you are applying drain voltage and your source contact is coming here this is where you apply source voltage. When I do VDS divided by ideas I am measuring this whole resistance this whole resistance is R channel plus R SD or R parasitic any other external resistance outside this transistor. In other words this transistor in reality is an ideal transistor which is gate controlled in series with these parasitic resistance correct. So, these parasitic resistances will affect your analysis because you had earlier mentioned VDS over ideas is only channel resistance, but it is not. So, VDS over ideas is R channel plus R parasitic and that is what you are measuring correct. So, then what will you do right how will you extrapolate you know this curve and get the L effective right. So, there is a very interesting technique. So, that is now L effective measurement in presence of I will say R parasitic what I mean by R parasitic is that VDS over ideas is really what is called R total which is R channel in series with R parasitic. When I am doing VDS over ideas R total essentially I am you know measuring both R channel and R parasitic. Now, you see there is something interesting one can do and that is R parasitic is fixed given a transistor R parasitic is fixed, but R channel depends on gate voltage value. You see what has happened is that there is a new variable that has come in if I have to get rid of this new variable I need another knob to play. So, what I do is the following earlier I was constructing this graph for only one value of VG, but now I will construct this graph for multiple values of VG. The idea of doing this for multiple values of VG is that by doing. So, I am modulating R channel, but R parasitic is always the same and hence I should be able to get R parasitic and hence 2 delta L both will come out. So, the technique here is that do your R total measurement for different VG values. If you do that what you will get is something like this again I am plotting for different length transistor again I choose 4 or 5 different length transistor. Now, what I am plotting on the y axis is total measured resistance I do it at one value of the gate voltage you get a curve which looks like this. Let us say this is for you know VG equal to 4 volt I do it for another value of gate voltage that probably will look like this and let us say this is VG equal to 3 volt and you know you do it for another value of the gate voltage you will essentially get a curve which would probably look something like this. Let us say this is VG equal to 1 volt very interestingly all these curves will intersect at some point here. What are you doing here really VG equal to 4 volt your R parasitic is constant R channel has certain value when I decrease the VG value R channel increased because VG is decreasing and there are not as many electrons and I am modulating R channel, but R parasitic stays as it is. That is why the resistance increases here for a given channel length transistor right. Remember I am doing all these measurements for different values of the channel length right and there is one transistor with this channel length another transistor with this channel length. And I really constructed these transistors and I am doing these measurements on multiple transistor and from there I am extrapolating, but I am not going to look at this point, but I am going to look at this point because this is the point of interest for me. What this is going to tell you is that the fact that all of them meet here you know that is what is your parasitic resistance R parasitic resistance. Parasitic resistance constant here at this value and in fact at this value your R channel is 0 that is why all of those are giving your constant resistance you see that is all of them are really meeting at this point. If you look at this equation when R channel is 0 R total is R parasitic and R parasitic is same no matter what is the length of your transistor it is not going to change. And hence all of them start from this point beyond this you see as you start you know applying different gate voltages for the same parasitic value of the resistance R channel here is much lower for this transistor at 4 volt compared to 3 volt. And hence I get this curve at 4 volt, this curve at 3 volt, this curve at 1 volt and that is all of them meet at this value and this is R parasitic and this is 2 delta L. Now, even though the transistor has lot of parasitic resistance I can simultaneously get the value of parasitic resistance as well as the lateral diffusion that has happened. And once you get 2 delta L for all these transistors I go back and subtract this 2 delta L and get L effective. So, this is a very interesting way of getting a electrical channel length and this is important because once you make transistors in large number of chips you know it is very difficult for every transistors length to be measured optically or using electron microscopy, but electrical measurements are very fast and non-destructive. So, by doing this electrical measurement you can actually do a lot of analysis on these transistors. So, one last topic that we will look at today is to measure the D I T or interface traps from transistors that is using I V measurement you know some kind of a current voltage characteristics measurement. And in fact you know I must tell you the way this was discovered was really a serendipity I mean in fact you know people who are doing measurement on transistors for some digital application. Digital application what you do you essentially apply a pulse or a square wave kind of a voltage you know zeros and ones is what is applied to the gate voltage right. And you would typically expect that you know you apply some source voltage you apply from drain voltage you have some current going from source to drain, but during such measurement when you were applying AC waveform on the gate there was some kind of a current that was measured at the substrate terminal. And you know this was at the beginning you know very unusual it is important that you know if you are doing some experiments if you get unusual resistance sometimes it may be beneficial to really sort of do more analysis on that unusual result that may have some very interesting observation hidden there. And eventually it was discovered that the current that comes at the substrate which was unexpected is really due to the interface trap traps. And more specifically if the interface trap density was very high the current was very high and if the interface trap density was very low the current was also very low in other words the current was directly proportional to interface trap density right. So, this turned out to be a very surprising and a very useful technique. Now let us look at you know what is happening really in terms of the experimental setup it is a very simple experimental setup. So, what you do is the following I have a transistor you can ground the drain terminal you ground the source terminal. And you essentially apply an AC waveform square waveform to the gate voltage and you connect a DC ammeter to the substrate terminal. And you measure this current which is also referred to as ICP and ICP stands for what is called charge pumping current. So, what happens here there is a certain condition here V G is being grabbed you see V G as a function of time this is done over time right this V G essentially is going between V high and V low. There is a important condition to do this charge pumping measurement and that is V high should be greater than V T and V low should be less than V F B where V F B is the flat band voltage of the transistor and V T is the threshold voltage of the transistor. This is an important condition let us say we satisfy this condition then what happens let us do this analysis. If my gate voltage is at V H level because V H is greater than V T the entire transistor will be inverted correct. So, it will have large number of electrons. So, let us do that analysis here for V G is equal to V H which is greater than V T what you have here is large number of electrons these are all electrons. We will also look at the band picture in a minute why do not we just do that here. So, if you had to do the band diagram here what will happen for the band diagram if this is your oxide you applied a positive voltage to the oxide and this is how the band diagram will look lot of electrons will be there Fermi level will be very close to conduction band most of the interface traps are filled with electrons. Now, let us look at the condition V G is equal to V L is less than V F B remember V F B is a flat band voltage if you are below flat band voltage then you are in accumulation condition correct. So, then what happens if you look at the transistor this is your n plus region n plus region this is your p region n plus p region here you will have lot of holes coming in. Now, if you had to look at this band diagram this band diagram will probably look something like this accumulation condition ok, but how did I go from high to low I went from high to low with a pulse which has let say for the discussion for the time being 0 fall time fall time is 0 from high to low I have come down instantaneously when I came down instantaneously from high to low what would happen just think about it of course, holes will come and accumulate because p is a majority carrier lot of holes are available they will come and just accumulate at the interface. But what happens the interface traps remember when we were discussing about the interface traps I have been saying that interface traps have certain time constant meaning the traps which are holding the charge they cannot leave the charge instantaneously the time constant may be from for fast interface traps it could be from micro second to millisecond I am saying that I am doing this transition at instantaneously fall time is 0. In other words when I created this these interface traps eventually would like to empty out because the Fermi level position is below the interface trap levels, but it does not happen instantaneously what happens instantaneously is large accumulation of holes. Now what happens these traps which are still filled with the electron at time t equal to 0 that fall time they start coming out electrons start coming out slowly from the interface traps because the steady state condition is that all the interface traps should become empty. So, when these electrons are coming out here they see these hole C of holes you know in other words we say there is a electron hole recombination these electrons which come in here they get combined with the hole and that hole get replenished instantaneously because it is a huge majority carrier p type that I have. So, all the electrons that come out will effectively constitute a current at the substrate terminal because for each electron that is coming out you need to provide a hole to recombine and that hole is essentially provided from the substrate terminal. So, if you have large number of interface traps there are large number of electrons trapped in and hence they result in large number of electron hole recombination and hence large number of current charge pumping current. So, this charge pumping current happens at this instance as well as at the next instance you know whenever I go from low to high and high to low right in all these instance the charge pumping current is like a spike right and what I do is an integration of this you know I average it out that is why I have a d c ammeter here right I measure the total current if your frequency is f you know that sort of averages out over that frequency that you have. In other words your charge pumping current it turns out is given by q times N i t times of course the area of your transistor times frequency this frequency is essentially your a c frequency that I have. If you have larger frequency you have more current because in a in one second you have more such transitions and there are lot more times you have filled and empty electrons and holes in the traps all that averaged out and you have more current. So, now N i t is total traps because what I am doing from inversion to accumulation is I am spanning the entire trap density from flat band to 2 phi b condition in the band gap right this entire traps in this region are either filled or empty and they are responding to this fast varying. So, as a result of that if you were to compute I c p you know what is your frequency of operation and you know what is your area and you know you would be able to compute N i t and from N i t you should be able to compute D i t. And in fact if you actually do this measurement at different frequencies you will see that your I c p versus frequency will be linear and this is again a signature of the fact that this current is coming due to filling and emptying of the traps when I am going above threshold voltage and below flat band voltage right. If you do not do this above threshold and below flat band you would not be able to get this kind of a current. So, this is a very very very sensitive current sensitive technique you know it is sometimes even more sensitive than the capacitance measurement techniques. Capacitance measurement techniques have some limitations whereas the charge pumping technique is a very very sensitive technique and you know there is lot of literature available in terms of measurement using charge pumping and the variants of charge pumping current which can even give a distribution of interface traps inside the band gap. Because now what I am getting is a integrated value of interface traps between flat band to inversion condition right. What I mean by that is you see if it is silicon with certain band gap right and this is mid gap right. Flat band condition is Fermi level is here below phi b I mean phi b below mid gap when I reach inversion phi Fermi level will be phi b above mid gap. So, this is the region that I am spanning all the interface traps in this region are contributing to this current here that is the integral of d i t over this region right. So, what I am told you just now is that there are variations of charge pumping current which can even give you distribution of traps in energy in this region. But that is a final detail of charge pumping measurement we will not really discuss about that, but suffice it to say that you know by doing this very simple technique which is very accurate you should be able to measure interface trap density in transistor very accurately. So, then let me just wrap up and summarize various parameter extractions that we looked at threshold voltage as you know is a very important parameter we can extract the value of threshold voltage using the so called peak g m extrapolation technique or using constant current V t definition or using sort of sub threshold and linear transition you know as we discussed earlier. Then mobility can be extracted by looking at trans conductance. Trans conductance is essentially change in drain current for a given change in gate voltage and hence you extract mobility. L effective is a very important parameter which is an electrical equivalent channel length of a transistor and in order to extract that you choose transistors of constant W, but varying length and do some simple I V measurement and be able to extract L effective and finally, charge pumping is a very very powerful technique to extract interface trap density. So, let us stop at that.