 So, welcome to this lecture in the course digital system design with PLDs and FPGAs. The last lecture we have completed the examples on VHDL. Then we started with some issues in the finite state machine or the controller. We have looked at how to bring the state machine to a starting state using a reset very simple thing. But if you forget then it can be problematic ok. This is like you make a cable and you want to crimp a connector and normally there is an outer ring and if you have not put and you have gone ahead and crimped. Then you realize that you have not put the outer connector, outer turn or something like that then it is tough so something like that. So, you should not forget to bring the state machine to a starting state by you know putting the reset. Second thing we have looked at is what is the kind of most appropriate clock frequency for a controller for a state machine. We have looked at the maximum frequency but then that is not a good idea to run the state machine at the maximum frequency will dissipate a lot of power. Suppose the data path is running at a much lower frequency so what should be the criteria how much you can bring down the clock frequency of the state machine and what are the issues associated with it. And that is what we have seen I mean we have not completed but then we kind of set the case for minimum clock frequency and we have seen some effects. So, I will just have a quick glance at this last lecture slide I will not go back to VHDL because we have done quite a few lectures on that you must be thorough with it. So let us move to the slide we will see the state machine part as a revision then we will continue. So, let us look at the slide so this is the slide on power on reset so this is the state machine you know kind of structure you have the flip-flops which gives the present state and that combined with the input will you know give the next state using next state logic. The present state is decoded to produce the output sometime some output may be just a function of present state and some output could be a function of the present state and input. And as we continue this lecture we will have a look at what I mean what is the difference or what are the features of this Moore kind of output and Millet kind of output we will see that. So, I said suppose the flip-flop you are using in the technology suppose you are implementing the state machine in FPGA and the FPGA flip-flop has an asynchronous reset or you are making it in VLSI chip and the technology flip-flop has asynchronous reset. Then it is easy to use that asynchronous reset is very quick as soon as you assert the reset pulse with a minimum delay the present state become the zero. So naturally the starting state can be all zeros you know that is the most easiest thing to do suppose you start with the state 001 then you may have to reset some flip-flop set some flip-flop. So when it comes to the state assignment it is always easy if you can assign the starting state as all zeros okay depending on the number of flip-flops. So asynchronous reset can be used and suppose we do not have that asynchronous reset in the flip-flop then we have to look for synchronous reset the advantage is that the synchronous reset can be an input to the next state logic and the game is that if it is asserted then we say that the next state is 00 or the starting state okay. In this case you have an advantage that you need not reset to zero when you have a sync reset since it is part of the next state logic you could make it easily to any state okay. But if it is zero it is all the more convenient and we have also said in tune with the kind of synthesis we are doing at the RTL level it essentially means like given to a synthesis tool and you know that the reset as priority over all other inputs then it means that ultimately the circuit is nothing but you have a 2 to 1 multiplexer at this stage with the reset as the select line when it is 1 the 0 goes when it is 0 the normal thing happens okay that is I mean we have seen that kind of synthesis. I mean that is what even if you write equation an equivalent circuit is going to come at the output instead of a 2 to 1 max may be a simple AND gate comes and the sync reset can be if it is active high then it can be re inverted and can be given to the input of the AND gate. Suppose if the number of flip-flops are 2 then there will be 2 AND gates and the next state inputs are going to the D1 and D0 will go to one of the inputs of each AND gate the other input goes to the inverted sync reset for active high and so on okay. I suppose that is simple enough for you to work out I just gave some detail about how it is going to be implemented when it is really you know worked out the equations are worked out. So that is about the power on reset and we have looked at the clock frequency and the question was that what is the ideal clock frequency for the state machine okay. Now we know that what is the maximum okay it depends on this path and this path okay. So this path going all the way up to some register or up to here you know since we do not know where it is going we will consider up to here okay. So it means that the clock period should be greater than the Tcq because the clock comes it takes Tcq delay then the next state logic delay and that has to come here setup time before the next clock end. So the Tclock min should be greater than Tcq plus T next state logic plus T setup or it could be Tcq plus T output logic because even if it is something directly used here say like it is crazy if this path works properly but the output does not get a chance to become you know active you know before that it goes to the next state. I mean everything works internally fine but the output kind of does not have time to get decoded then it is a bad thing. So that is a maximum frequency that is what is we are putting it here. So we choose max of two paths you know Tcq plus Tnsl plus TS everything max okay and this is the Tcq plus ToL max and you should know that like even when we use the tool there are the clock period we use a maximum time delay and for the whole time violation we use a minimum delays okay because it is the whole time violation happens with the same edge. So in the tool when you simulate you have the opportunity to choose the fastest delay or the slowest delay and all that corner cases can be chosen when you do timing simulation maybe when we work with the tool I will show you how to do that. So that is the maximum clock frequency but then we said there is no kind of point in clocking at the maximum clock frequency because it dissipates a lot of power and moreover we have some data path which is being controlled by this controller all these inputs are coming from some somewhere in the data path and these outputs are going to the data path. So naturally and that data path is working at some frequency we optimise or we maximise the clock frequency in the data path to get maybe the highest throughput in some application okay. So there is no point to kind of like suppose that is working at 100 baguettes maybe it is futile and you know a lot of power wastage if you work at 1 gigahertz clock frequency okay. So the question is that what is the minimum we can do okay like given known like if the data path is given then what is the minimum clock frequency we can choose and that was a question and to illustrate we have put I have put some kind of simple picture there assume the data path outputs which is going to the input of the state machine that means again in this picture we have suppose 3 inputs in 1, in 2, in 3 coming from some part of the data path okay. So I have put that okay so and to understand the problem we have made it very kind of simple and very symmetric okay we have put square waves like clock which is not the real life at all that but we can as I said when you analyse always go for the simple case always go for the symmetric case, regular case so that once you grasp the underlying issue the basic how to solve it we can extend it extrapolate it to the real life okay. I have cited an example suppose you have working with linear algebra with matrices and you are probably working with Eigen values or linear transformation or rank of a matrix and if you work with a 5 by 5 matrix and try to get some in-duty feeling about it it may not be possible but then if you say work with a 2 by 2 matrix or a 3 by 3 matrix it is possible that you can come to a 2 dimensional or a 3 dimensional graph you can draw with the vectors and you can make out suppose you are applying some linear transformation what is happening to the vector can be easily understood then if you grasp that basic then you go to 10 by 10 matrix that at least that clarity will come into the picture you cannot draw a kind of graphical picture of the 10 dimension but if the matter is clear in 3 dimension okay I am talking about the geometry to make the life easy but need not be okay not our subject directly not related but then you know some people are comfortable to work with algebra alone that you do not use such kind of isomorphism of going from algebra to geometry and back but anyway in geometry probably you are limited with the 3 dimension and so on. But anyway coming back to our problem we put very simple symmetric case let us assume yeah I have chosen very cleverly kind of manipulated case in one is a some kind of clock kind of waveform into is half of that in 3 is half of that the clock period so the frequency is twice and this frequency is twice of that. So this is the scenario this is going to the state machine and we have put something like this okay let us assume the state machine clock is this and we have found absolutely no problem like at this positive edge the state machine is in some state it detected that in one is 0 then in one a stage in the next clock edge yes it has transited maybe we are in a state looking for this input to go from low to high absolutely no problem because if we say in a state in one bar you remain there in one you go to the next state and that will happen perfectly because at this stage it will be in that particular state. But when the next clock edge comes it finds that the in one is 1 and it will transit to the next state maybe we will make some output to respond to this event and that is how we control and here again it is 1 then it is 0 so it is able to track all the changes in in one and look at into absolutely no issue when this clock edge comes into is 1 then this comes into is 0 then into is 1 no problem. But look at in 3 and what happens you know the clock edge comes to the state machine it detects a 1 suppose there was a you know condition that as long as in 3 is 1 remain in 1 this state and if in 3 is 0 go to the next state. And you see that it has gone to 0 then it has gone to 1 but at the next edge is still 1 in between it has gone to 0 it has come to 1 next clock edge our state machine still is detecting that in 3 is 1 and will get stuck at that state it will not even proceed to the next state and it is stuck there and waiting forever for this particular input to go low. So you get the problem now so this clock is not able to detect the change in this particular input for it to be detected we know that at least 1 active clock edge should come in this period okay suppose an active clock edge has come here we should have an active clock edge somewhere here. So like you should have an active clock edge in this period and another in this period so naturally 1 clock period suppose it is good if you can have 1 edge here and 1 edge here and so on. So we should have at least 1 edge in this period that can happen only if the clock period of the state machine is at least less than this particular width. So you see this is the maximum frequency input to the state machine the clock period is from here to here okay. So you take the half the clock period so the period of the real FSM clock should be less than half the period that means the frequency of the state machine should be twice that of maximum frequency input okay that is game okay. So that is it okay now maximum clock frequency should be greater than the twice the maximum input clock frequency okay it sounds like you know in a kind of NICUS criteria because in NICUS criteria you say which definitely we are talking about the transform the frequency domain you have a signal and you want to sample it and you know the highest the clock frequency highest frequency contained the sine wave then you should sample that twice that so that you can recover it. Something similar to that happens it should not be surprising because we are sampling the input though we are talking about the digital domain where we are talking about binary signals not the analog signals and so on. This happens because we are sampling the inputs and first thing is that now let us relax our criteria earlier we said okay we assume that yes it is fine it is like a regular square wave but in real life nothing like that happens. So it is sampling the inputs input may not be very periodic waveform but you have a pulse width like you have a narrow pulse that should not be the criteria for choosing the clock frequency because it can be stretched and the game is that you know I will show a picture suppose this is a input say the pulse width is 10 nanosecond okay assume that it is 10 nanosecond. So you will have you know suppose this is the next pulse come with after 1 microsecond okay. So the clock frequency the frequency of this signal it may not be regular waveform but assume the minimum time period between them is kind of 1 microsecond then we can say the clock frequency the maximum clock frequency is kind of 1 megahertz but this is 10 nanosecond okay. Now if you choose a clock period to kind of detect the change in this input because we are this is coming to the state machine we should detect that you know it has changed the state okay. Now to detect that we need a clock period which is only less than 10 nanosecond that means this clock frequency will be 100 megahertz but the input frequency itself is only 1 megahertz okay. So but the game is that you know we can kind of stretch this pulse because the next pulse come only after 1 microsecond may be it is even possible to stretch all the way to 500 kind of nanosecond or anywhere okay. And you can use a much lower clock frequency to detect this change at the state machine. So this is possible but like it depends on the application suppose there is a requirement some event has happened and this pulse has come. But say the controller should respond to that event within say 15 nanosecond then it is you cannot arbitrarily stretch it we have to use a clock frequency which is kind of the period should be less than 15 nanosecond because like after the input changes within 15 nanosecond the state machine should respond to it then the clock frequency should be chosen according to that requirement. So that is what is written here the pulse which should not be the criteria it can be stretched how fast to respond to the event should be the criteria okay. So all these the problem is that many a times you read in the textbook you get a very simplistic kind of solution disregarding all these issues. And even in real life when you interact when you work with a specification many a times these kind of requirements are not clearly spelled even by your the customer or the user or it may not be clear you go ahead implement something then you deploy it then you realise that. So it is very important to ask to be aware of these issues ask the right question when you kind of form the specification and it is very important when you design some complex system to write these specification the requirements in as much as details as possible and there are standard format requirements specification there could be standard format. But I am not talking about the format you know these formats the standards and all helps. But even if it is not very organised very systematic writing it down writing the requirements clearly drawing some waveforms writing some tables bring clarity to the scenario of course you can use some kind of documentation standard because it helps you to use standard tools to manipulate that like in a team nowadays it is all connected environment. So if you use a tool everybody can look at the tool multiple fellows can work on the same kind of file and so on. So that is helpful but the primary thing is to be aware of these issues and bring clarity to the scenario. So let us look at this scenario particular scenario where there is a pulse and I will show you a kind of circuit how to do the stretching okay which is frankly not a very practical in the sense there are better ways to do it. So let us at the beginning just for the argument sake see a simple very simple circuit to stretch this pulse by whatever width you require as per your requirement. But I mean practically we do not use that I will show you a better circuit after that but this is to stress the point okay. So one other thing is that here we talked about a pulse being detected okay maybe and there is no timing requirement great timing requirement it has to be detected before the next pulse then you can stretch it to any limit and you will detect it whenever you want before the next pulse okay. But otherwise you say the pulse width is 10 nanosecond but it has to be detected within 500 nanosecond no issue you stretch it half way then you can detect it okay. But it may happen that you may have to kind of you have a timing pulse okay and you have to detect it with certain accuracy. So if you remember in the case study we have you know discussed with respect to the ADC controller we had just before this lecture we had a case study where we wanted to have a controller which controls an ADC to give the start of conversion to ADC and store the sample in a memory okay. There we said that the right to the FIFO should be of certain width and we have decided to put a counter outside and the counter will give a count from 0 to some particular count and we will decode that count and give back to the state machine okay. And state machine will detect that change when it reaches that count and stop that right pulse you know that was idea. So we are in a similar situation I am showing in the picture of course I am showing a kind of again and little ideal case. So let us assume this is a timing pulse we have started this pulse at this point and the state machine is looking for the end of the pulse okay. But say this is some few say 500 nanosecond but this being a timing pulse there has to be some accuracy on it. Suppose we are giving a delay like around 500 nanosecond and suppose the state machine is assembling this pulse with a clock period because this pulse is going high here going low here. Suppose we use a clock like this looks perfectly fine because this clock earlier would have detected that it is you know 0 then this clock edge it is detecting that it is going to 1 then at the next clock edge it is detecting that it is going to 0. But our aim was to somehow capture this delay with certain accuracy but what happens now what we capture is that we will check at this activate that it is 1 this activate it is 0. So what time we detect the state machine detect is this time period not this time period okay. So that is the issue and suppose you use a higher clock frequency more higher clock frequency there are positive edges here. So we are assembling at all edges so here before it was detected it is 0 at this point it detects that it is going high and you see here it is 1 here it is 0. So here if you see that real timing pulse was this and here the pulse width is this. So we are much closer here suppose the requirement is that suppose this is kind of say assume that it is 100 nanosecond and this has to be detected with a kind of accuracy of say 90% okay. So the error should be 10 nanosecond okay. So assume that means this should be detected within 10 nanosecond. So it tells that the clock period should be kind of in that order you know the clock period clock edges should come in kind of within 10 nanosecond. So that is what is I have written to detect a pulse with certain accuracy minimum clock period should be less than the error requirement okay. This is quite intuitive but when you do many complex thing you forget you can tend to forget this. It is very natural that if the counter is working with a 100 megahertz and the state machine which is controlling that counter is working with a 1 megahertz you know that there is something wrong you know the counter is changing state at 10 nanosecond and the state machine is looking at sampling at 1 microsecond is something not acceptable. So that is what is the game is. So this should be kept in mind as far as when you have a timing requirement but in any case but to make an assumption that everything should be greater than any frequency used in the data path will be over a simplification and nowadays you have lot of constraints on power the timing and all that. So it is better to choose the optimum clock frequency which minimizes the power dissipation and many other things like that. So that is about the accuracy of a timing pulse. So let us look at this scenario we have a pulse and which is actually the frequency is low but the pulse width is very narrow and if you just consider the pulse width we will end up using a clock frequency for the state machine which is very high. But if you stretch it because the frequency is very low then you are able to use a higher clock frequency sorry lower clock frequency for the state machine. So to illustrate the principle I will show a pulse stretching circuit then we will come to more practical circuit okay. So let us keep look at this pulse stretching. So what we do is that this is a pulse catching flip-flop you see this flip-flops and this is a pulse in this case a narrow pulse come this is a input and with a very low frequency the pulse come again okay. And if you kind of concentrate on this pulse width then you will choose a clock period which is less than this width and that could be very high okay. So assume that we want to stretch it, stretch it to kind of somewhere here. So what we do is that we have a clock and reset but the clock goes to this flip-flops but this catching flip-flops has a clock as this you know it takes this pulse as a clock and the d input is given to 1 okay. So what happens is that when the pulse come this s detect so I am calling this dit and this is synchronous detect, synchronous detect you see that it goes high okay. So the detect comes on the next clock edge yeah. So here it goes high and the next clock edge that is shifted here and in the next clock edge it is shifted here that is what is shown here it goes output goes high in the first clock edge it comes here in the second clock edge it comes here the moment it comes here it goes back and reset this game and this goes low okay. So this pulse is stretched by 1 clock period because it looks as if it is 2 clock period but it cannot be 2 clock period because we are not sure when the pulse pulse is asynchronous to this clock. So it can come very close to this kind of this clock can come very close to it and that is why I mentioned is not a very practical circuit I will show a practical circuit soon but this is to kind of understand the principle. So we give 2 flip-flops to get a 1 clock period stretched so that is how it is stretched. So at the beginning it is reset everything is reset and then the pulse come it is kind of stretched at least by 1 clock period you want to stretch it by 2 clock period you put 1 more flip-flop and so on okay. Not a very practical circuit because there could be timing issues at this point when the input comes here with this flip-flop maybe if you put a chain of flip-flops it gets solved we have not seen what is that timing issue but so I am not able to kind of discuss that now and it is problematic is not a very practical circuit suppose you want to stretch it to some kind of 10 times a clock period then is not a very kind of practical circuit but then you might ask I mean why to stretch it then you know you reduce a clock frequency and so on. So we will look at a more practical circuit. So that is using something called a pulse to level converter and a level to pulse converter that means the basic idea is that when we have a pulse instead of just stretching it when the first pulse come we will make an output of this some circuit to go high like that continuously high the next pulse come that high is made low okay. So there will be between the pulses you will get a kind of square wave and what we do is that at the state machine when it goes high we will convert it into a pulse in terms of the clock frequency of the state machine okay which could be decided by some other input okay we are not sure this input is very low frequency maybe there are some other input which is higher frequency than this that will decide the clock frequency of the state machine. And using that this the pulse going high that will be converted in the in the FSM to another pulse which is wide enough to be detected by the state machine okay that is a game. So what we will see first how to convert a pulse to a level so that is what is very simple. So assume that this is a pulse okay I have not shown a lot of kind of gap but assume there is a gap then the next pulse come next pulse come and this is a D flip-flop you see the pulse is given as a clock okay and at the beginning it is reset. So you have I am calling this I because it is going as input to the to the state machine that conversion logic. So the I is low but when the pulse positive edge comes you see this is inverted and given so that this is 0 at the beginning then when this pulse come it becomes 1 and it will remain there as long as the next pulse come. The next pulse come it was already output was 1 so that is inverted and the 0 comes here and goes 0. So between the pulses either it is 1 or 0 now we take it as a state machine and state machine as some clock it is enough if you get a pulse of that state machine clock frequency at this starting and this point or if it is a negative edge we can make it here it does not matter okay. So I will show that kind of circuit and so this is the input which is a level you know we have converted the pulse to a level signal or a pulse to a toggle signal that is I and this is I that we are giving it here okay. Now this is a practical circuit I am putting two synchronizing flip-flops we have not studied why the synchronizing flip-flops is required that is to basically to meet the setup time here okay. Otherwise this flip-flop can get into something called metastability we have not studied maybe towards the end of the lecture end of the course I will touch upon it I hope I will have the time to get into it but this avoids that probabilistically. Now it is not that this scenario is completely removed but with a high probability that is kind of that scenario is averted that is a basic game so do not worry about this at all. So assume that I comes here it goes through a single double stage synchronizer it does not matter as far as timing is concerned I1 is a delayed version of I, I2 is a delayed version of I you know I1. So I2 is kind of 2 clock period delayed version of the I okay that is a game. So we will see so the pulse come you know like this a toggle comes so assume at the starting point there was a pulse here and there was a pulse here we have converted to toggle. Now this is where the all transformation happens we have an input a flip-flop it is input and output is combined through a logic and assume that logic is that I2 and I3 bar okay. So you assume an AND gate here I2 goes straight to the AND gate I3 goes through a bubble or an inverter I3 is inverted see what happens. So assume that this is the clock to the state machine and which we use in the same this transformation circuit and the see the I2 goes like this okay here for analysis that is enough we do not have to analyse I and the clock comes and when the I2 comes you see the clock comes so the I3 will go high okay in the next clock edge. But you see that I3 we are looking for a scenario where I3 is low and I2 is high. So you see I2 is high here but the next clock edge only the I3 will become high. So at this point with a 1 clock period there is a condition that I2 is high and I3 is low because this clock edge only the I3 can go high because it is at the output. So I2 I3 will give a edge a pulse which is of the duration of the clock period with a slight shift and that can go to the state machine and state machine is using this clock. So naturally it will sample and detect this pulse correctly okay. So it is a very clever circuit I hope you got the picture this was I2 so I2 was 0 before and in the next clock edge here only the I3 will become 1. So before that so during this period I2 is 1, I3 is 0 so you get a pulse and that only happens for this 1 clock period it does not happen here it again happens here. Suppose you want to catch the you want a pulse at the negative edge you do the opposite that this point is low and that point is high and that happens at the negative edge you can kind of analyse it and suppose you want the pulse at both edges here and here for some application then you know that it is nothing but I2 I3 bar or I2 bar I3 which is nothing but I2 X or I3. So depending on what you put here may be an AND gate with a bubble here or an AND gate with a bubble here or an X or gate you get any of these pulses for our case we are going to use this okay. So where we have a pulse using this particular circuit you convert it into a level signal okay and this input goes through a double state synchroniser to avoid some timing issue in this flip flop and then in this flip flop we combine the input and output through a kind of this logic very simple logic then you get the correct pulse and very important the timing is correct because we are you know deriving with a delay with respect to this clock head that pulse will come with a delay. And when this pulse ultimately goes to the state machine, state machine will correctly sample it as high you know that is very so this generate the proper timing as far as a state machine is concerned because state machine is working with the same clock that is assumption. So I hope you got this picture it is a very useful kind of structure which is very much used in synchronising clock domain crossing. Only difference is that I have little bit manipulated this and when this pulse is coming from a domain with another clock then there could be a slight change in the circuit the pulse can go here in the data path but the clock of the domain comes here you know it is a very slight change it is a very useful kind of principle and put together. So I am putting this at the input and side and this is the output side and I am combining it. So this is what which does the trick or the magic you convert a pulse to a level signal and you synchronise it and you convert level to pulse which is in this clock domain properly then the timing is proper with this clock domain. So that is how the pulses are handled and so essentially we are saying that though we said the FSM clock frequency should be twice that of the maximum input clock frequency we should not be worried about the pulse width we should be worried about the frequencies. And if the pulse width if there is a pulse it can be stretched to be neatly detected by the state machine okay. And we do not like in the first circuit we have shown it is kind of stretching at integral number of the clock cycle but then this is a better scheme we are not even stretching it we are toggling it okay it is a kind of extreme case of stretching it. We are stretching all the way to the next pulse you know so it is like a extremum that pulse is stretched from the first pulse to the second pulse then it is kind of made low it is made to toggle and then at the other end we convert back into a pulse which is of correct which has a correct timing that is the most important thing. Now let us look at this Moore and Millet output so there is a confusion where the Moore output should be used where the Millet output should be used. If you read a textbook many a times it appears as if you are making a big choice at the beginning of the design saying because many a times it is called Moore machine and Millet machine and that is very confusing you know it is as if at the beginning of the design process you are assuming okay let us go ahead and design a Moore machine it is not so because there are in practical controllers there are a lot of inputs a lot of outputs some outputs are function of the present state some are function of the present state and input so it is not a question of kind of designers preference to choose Moore output and Millet output that is what I want to bring forth. There are places where the Millet output is kind of works properly and the best option then is to choose Millet output okay there are places where the Millet output cannot work okay at such places you should use the Moore output and the discussion may not be complete at this point there could be questions asked which with the present background I cannot answer everything maybe as we go ahead in the lectures maybe some issues are handled some issues are not handled but anyway we are improving our the grasp of the situation as we go along. So, let us look at our case study where we have a controller for ADC I will take a kind of simple case from there the state machine was generating a start of conversion pulse okay. So, that is scenario so let us look at that state diagram. So, this was the state diagram so let us go to the slide so if you remember I hope it was simple enough so in the power on we come to a state okay and we were waiting for the start signal from the host CPU. As long as the start was low we remain in this state and the SOC was the start of conversion pulse was 0 when the start signal came the state machine or the controller made a transition to the next state state 1 and this particular output I am only showing the kind of the concerned output or the relevant output okay. So, SOC was made 1 and it is an unconditional transition in the next clock pulse we go to S2 and make SOC 0 and we were waiting for end of conversion here okay. So, that is a clear picture and since this is an unconditional transition so upon the start like when the start is detected on the clock it comes to S1 in the next clock it goes to S2. So, you know that the pulse width of this SOC is 1 clock period because the minimum time a state machine can remain in a state is 1 clock period because everything happens in terms of the clock period in terms of the clock edge okay. So, this is a moor output. So, if you see that this SOC is a moor output which is a present state is decoded that means that like when you write the output logic we say S0 state 0 in our discussion we said it is 2 flip flops the Q1 is 0 Q0 is 0. So, we say in the output the present state is 0 0 output is 0 present state is S1 which is 0 1 the SOC is 1 present state is 1 0 SOC is 0. So, it is a moor output during the S1 the output is 1 okay. Now, I am trying to convert this particular SOC into a Millet output okay. So, how we can do that? So, what we do is that say because we have only one input the start signal what we will do is that you look at this scenario when the start is low it is machinist in this state SOC is 0 when the start is 1 transit to the next state and make SOC 1 in this state and transit to S2. So, we will do like this say we will say the machinist in S0 state as long as the start is low remain there. Now, we say instead of SOC is 0 we say SOC is 1 if the start is 1 okay. So, SOC is written as a function of start SOC is 1 if the start is 1 then we say when the start is 1 we transit straight to the next state. So, that is what I am showing here the Millet output is upon the reset comes here as long as start is low remain there and SOC is equal to start that means in this particular state as long as start is low SOC is low when the start comes high the SOC is high. That means this SOC is a Millet output which is a function of the input start signal and the present state okay. So, we are decoding the present state. So, when you write the equation when you write the table we say S0 which is nothing but 0 0 and we have an input column where we start. Start is 0 then SOC is 0 when in 0 0 start is 1 SOC is 1. So, in the equation of SOC you have Q1 bar and Q0 bar and start okay that is the equation of SOC. And now we do not need S1 as the start comes in the same state the SOC goes high and it transit to the next state and SOC is made 0 okay. So, that is the scenario that is how the Millet output is generated. Now we can see and already you get a picture what can happen and if you are clever a clever student can already make out yes there is an advantage saying that this particular state is kind of knocked off and you get one state less. And you can imagine if there are this is we are talking only about one particular output if there are 10 outputs which was all kind of more kind of output. Suppose we are able to translate you know convert all that into Millet output may be the 10 states are less and that is a great saving and 10 states are less if it is a binary encoding log 10 to the base 2 it can be you know 3 flip flops could be less you know in the game okay depending on the total state. So, there is an advantage we clearly see number of states are less but this already should give you some hint as to what can go wrong like we are waiting in this state and the start comes then the SOC is 1. So, that description itself should give you some picture of what can go wrong. So, we are coming to the end of the lecture. So, we will see that timing in the next class a little more elaborately. So, because as I said we are seeing which is the optimal scenario where we can without you know kind of any timing issue we can use Millet output and get some advantage and where we cannot use it we should be using the more output is what we are discussing. So, we have seen how to convert a more output case to a Millet output case we will look at the timing issue in the next lecture. So, we have looked at basically the minimum clock frequency and the Millet and more output in this lecture. Please revise grasp the underlying issue I wish you all the best and thank you.