 Welcome everyone from now onward we will resume we will start unit 2 which will discuss in detail various styles of constructing different kind of combination and sequence of such is out of the NMOS function and NMOS function in unit 1 we went to the basic construction on the basic operation of NMOS human function including the formula for the current consumption unit 2 we will look into detail of different styles used for construction of different gates in the first chapter of unit 2 we will discuss we will see let us see the outline of this we will see different types of we will see some examples of complex gates we have designed using static team of circuits we look at different kinds of we look at price state inverters price state buffer different kind of muxes inverting and non-inverting we will see how pass transistors and transmission gates are used we will see an example of the layout of a slightly bigger circuit and also an inverter and we I will try and point out it is just the important parts of the layout so that we understand how the how the tapestances are minimized during the layout look at there are couple of slides about big diagram big diagrams are very very useful when you want to represent a layout on a paper. So let us start with a with this NMOS gate design I would recommend during this and other unit 2 lectures to have pen and paper ready so that you all are very able to quickly draw the circuit on your paper that will be very very helpful in this kind of a design. So this is the first activity which I want you all to do take a 4 input in pass mandate this should not be very difficult considering you look back 2 and 3 input in NMOS so just to just to review that an AND gate the there will be 2 parts of the circuit we pull down will be connected to the ground which will be comprised of NMOS transistor the polar part will be connected to VDD which will be comprised of the PMOS transistor each input of any gate will be connected to 2 transistors 1 NMOS and 1 PMOS that is to the gate input of NMOS so a 4 input NAND gate will have 8 transistors that is 4 pairs of PMOS and NMOS we pull down at work that is the NMOS will represent the complement of the function at right of the NAND we pull down will become the AND and all the NMOS will be in 3 the PMOS represents the complement of NMOS so all the PMOS will be in 5 so it is try and draw this circuit on the paper correspondingly what I would do is we will see a 4 input NOR gate. So you could also say that the NAND gate will be complement of the NOR gate so let us let us discuss let us review the NOR gate also so as I said that each input let us say a for this example in this example will be connected to 2 transistors 1 PMOS and 1 NMOS it will be connected to the gate input of the board transistor the pull down network will be connected to ground the pull up network will be connected to VDD the the pull down network shall represent the complement of the function we are trying to implement. In this case the function we are trying to implement is more so the pull down network of NMOS shall represent in all logic that means all the N all the NMOS here will be in parallel which is the case here similarly the pull up network which is connected to VDD there will be the complement of the NMOS or the pull down network since all the NMOS are in parallel the PMOS shall be in series. So VDD is connected to PMOS 1 and PMOS is connected to PMOS 2 and the output for this kind of circuit is always taken from the common train or whatever train or source is the format format for it the the Y here will be connected to this gate source. So the convention says that whatever is at higher voltage shall be called the source will call this point source of this these transistors so Y is connected to the source of or it is it will also be connected to two points that is one is the source for all the NMOS other one let us say is the brain of all the PMOS. In this way you could construct simple gates as been with as many inputs as you want so let us remember two important points let us let us see on the next slide. So we call this type of circuit as static CMOS why static static because in steady state that is whenever the values on all the inputs are stable the output will be either type to 0 to the pull down network to the NMOS pull down network the output will be there 0 when whenever pull down is on and whenever pull up is on and pull down is off the output will be type to 1 to the input drive the gate inputs of the transistors please note please be very careful in moving down that the output is not directly controlled to input the output is always driven by either VDD or ground this means what this means that if let us say there is any noise on input let us say the inputs are such that the output has 3 values that is connected to the VDD and if there is a little bit of noise of the input within the noise margin we will see what noise margins are later but if the noise is within the noise margin the output will not see any noise since it is not driven by input so it is driven by the VDD or ground another thing to another thing to this let us see this put table so whenever pull down is off so this represents like whenever pull down is off and pull up is off that is this quadrant the output is Z that is it is either connected to VDD not connected to ground now this case will not happen in case of a static CMOS why because we are assuming that all the inputs are driven to some value and since CMOS and NMOS are complement to each other the case of both being on or both being off will not usually happen these two quadrants are valid cases so whenever pull up is on the output is connected to VDD whenever pull down is on also there is one thing that in the steady state that is whenever the inputs are not switching the output will draw almost negligible current that is if it is connected to VDD the the resistance the on resistance of a transverse is quite low actually so it is drawing a very very negligible amount of current from VDD similarly when it is connected to ground via NMOS it is sourcing very it is thinking very negligible amount of current or this means is that this kind of circuit is very power efficient when we see different logic style in later capital please try and differentiate between this logic style another logic type on the basis of power now NMOS and VMOS independently also are such it so they can be used to make the different type of gates one of the example this is not a very popular style we will come we will come to this why is it so in the next slide so when NMOS is on when NMOS the gate input is 1 the NMOS is on and the gate input it is 0 the VMOS is on so let us look at figure A so A is connected to B by a series of two transistors the both NMOS so whenever both G1 and G2 are 1 A will be connected to B so you could say that the function represented here being represented here is G1 and G2 so there is a simple proof table of an AND gate similarly when we look at the PMOS so PMOS would again be the complement of NMOS so whenever either of whenever both of them are 0 then only the gate will be on so this represents an AND gate here we see that the circuit of a of two NMOS transistors in parallel so when either of G1 or G2 is 1 A will be connected to B which is this case this case and this case and both have an also A will be connected to B similarly the fourth figure is nothing but the PMOS and complement of C now again the important point to note here is that G1 and G2 are the tolling signal and if the AND A is in some of the cases whenever there is a path exists from A to B A is the input which is connected to the drain and B is connected to the source so in some of the cases the path exists between A and B and considering let us say the output is B and the other way round over so the output can also be A so A and B are connected with each other in some of the cases which means that a noise signal on A was to pass on to B this is an important point to consider in this case this kind of circuit I mean building whole gates using this style is not very popular because the reason I said because the noise gets passed in B now as I discussed earlier I would like to repeat this point that a complimentary CMOS gate will always produce either 0 or 1 the root of connection to complement say is that the pull up pull up network is always the complement of pull down network what it means is that if the pull down network is is series the pull up network will be parallel and vice versa you can you can see see any of the circuits we have discussed earlier is the two input manged or two input non-grid or two input manged or two input non-grid always the pull down network is the complement of pull up network this makes a job very easy when we want to construct complexity we will see in the next slide so here is one of the compound gates very popular gate and and or inverse so the notation which is being followed in the in the in the system is a is for and O is for or I is for inverse this gate is A O I 2 2 now any compound gate any compound gate that is really inverting inverting now please remember that CMOS logic by design is an inverting logic what it means is that let us say let us go back to slide and clear two input manged so a two input manged would need for input to transistor input to co-transistor but the function of Y is A dot B and if you want an AND gate you would have to add one more stage of the inverter after why that would mean that AND gate would have a two input AND gate will need fixed on this so whenever we discuss compound gate it is easier to discuss the gates which have inverting function that if Y will be complement of some function in this case Y is complement of A dot B plus C dot B now a non-inverting function can be just by adding an inverter at the output of so most of the compound gates that we discussed that we will discuss in the in the coming will be in the form of Y is equal to complement of some function so converting a non-compliment now complementing one will be simply adding an inverter so let us look at this now A dot B plus C dot D now what we could say is that is the non-complimenting part that is A dot B plus C dot D we can easily construct the pull down circuit this with it and pull up will be simply complement of that so let us look at figure E so figure E we see that A and B are in series A dot B means A and B are in series similarly C dot D means C and D are in series a plus sign means an odd of course so here A dot B and C dot D are in parallel and this is a pull down and will be connected to Y now when we try and do the complement of this we are left with almost a similar sort of structure so A dot B in series here would mean that A and B are in parallel C dot D in series here means that Q and D are in parallel a complement a plus sign would here mean that they are the two are in series so what could help is in analyzing the circuit is writing down on paper the complement of this so now let us look also at the smaller smaller part of the circuit let us say A so A B in series let us look A B plus C D in series A B are in series C and D are in series a plus sign would mean going from A B to B we will add a plus sign that is an odd we will combine A and B and C and B to convert in an odd function then we go on to see now what is so A and B will be in parallel C and D will be in parallel when we combine them we just connect the part here we just connect the part here to the part here so what would that mean is that C is connected to A and D is connected to B now with a connecting wire where does this wire where does this wire come from it wire this this wire it is common to this point and this point so we get E this is the logic diagram of the circuit so please take a moment to review this perfect review the construction of this compound I will have one or two more examples let us move on this one more example of O3 AI what O3 AI means is that it means three inputs and the output of that will be added to one more input and invert is the default the logic function is y is equal to A plus B plus C or of all these and into D and complement of this so this is a circuit let us again review this a pull down we should look at this on complement part and implement as it is involved A, B, C being in parallel A, B, C being in parallel and the whole circuit should be in series with D whole circuit is in series with D for the pull up part A, B and C should be in series and the whole of it should be parallel to D whole of it should be parallel to D you could also see and apply inputs at each of A, B and C to see if it really satisfies the line so let us say let us see D is 1 D1 means this nMOS is function this is connected to y this part and then when either A, B, C is 1 any of these is 1 y would be connected to D1 which is in turn satisfied by this equation D being 1 and any of A, B or C is 1 y would be complement of 1 which is 0 and we should also verify correspondingly that this circuit since only one of the pull down or pull up can be operational let us also verify that if the same condition this part would be off so when D is 1 this is off and when any of A, B and C is 1 this whole part would be off so you do not get a connection from y to B which is the basic principle of this kind of static CMOS network at one given time only one of the pull down or pull up can be active and let us come to the signal strength the strength of the signal so let us say you have a network of gates each in any of the design you will have a typical VLSI chip between billions of transistor billions of transistors means millions of hundreds of thousands of ways lot of gates have are connected in their multi state network that means that there will be let us say and connected to or connected to an inverter and so on so each of those gates each of these outputs and inputs of those gates we have to see they should all be relatively strong that means to make sure that the functionality of the whole digital design itself so we have to see so each of those inputs and those outputs and we say how strong is the signal we need to check how strongly does it approximate the ideal voltage source the ideal voltage source in this case being VDD and GND rail VDD and GND rail are supposed to be strongest are sources of strongest 1 and 0 how strong what is a strong mean in quantitative term let us say in my I chip the VDD is 1.0 volts and GND is 0 volts so a strong one would be in a voltage value which is very very close to VDD that is 1.0 volts how close let us say 5 percent of let us say it should not be worse than minus 5 percent of VDD that means a strong one would be somewhere between 0.95 to 1 1.0 volts similarly a strong 0 would be between 0 and 5 millivolts we saw earlier that NMOS passes a strong 0 that is why it is used in the pull down network but it passes a degraded or weak one we also saw that NMOS while passing 1 it will the VT of the transistor will be subtracted from VDD. So, a VDD at the source or the at the drain would and the gate being also tied to VDD would mean the voltage of the output that is source is VDD minus VT similarly NMOS will pass strong 1 that is why it is used in a pull up network but degraded or V0 now with that thing in mind we have also we will review again review the pass transistor and the usage of them in switching we have we have seen this earlier but the discussion of pass transistor is important here to see how transmission gates are constructed out of that. So, again let us go to the pass transistor pass transistor what it means is that input is being applied at source and the output is being taken at drain or vice versa. So, if gate is 0 source and drain for NMOS are disconnected if gate is 1 if the input is 0 if the input at S is 0 the drain would be strong 0 if S is 1 the drain will be a degraded 1 what it means if S is VDD the drain would be VDD minus VT similarly whenever TMOS is 0 if S is 0 so the output is degraded 0 that means output will be VSS that is absolute value of VT of the TMOS transistor when it is when the input is 1 it will be a strong 1. Now what we do here is that how much the pass transistor we combine the NMOS and the TMOS is so NMOS passes a strong 0 TMOS pass passes a strong 1 we saw that static TMOS gates they utilize the functionality to make sure that output is always a strong 0 or strong 1 and how did they do that by making the pull down complement of the pull up network. Now here while construction of the transaction gate we connect to we connect a TMOS we connect a TMOS circuit here and a NMOS circuit here by there we connected connect both the source and both the drain together this was not the case in static TMOS please note here the input is not coming from the gate the input is coming from the source side and going to be V is the output. Now let us see how this function whenever now please note that that one input is connected to the gate G other is the complement of gate G D nothing but complement of G whenever G is 0 the NMOS is off GB is 1 the PMOS is off A is not connected to be whenever G is 1 and GB is 0 they both are connected what it mean if the input is 1 the PMOS here make sure that output is strong 0 although there is connection also via NMOS but the PMOS make sure that the output is strong 1 whenever A is 0 the NMOS make sure that the output is strong 0. So, we utilize the properties of both NMOS and PMOS to construct the gate a switch in fact, the simple switch which make sure that output is not triggered this is the symbol of these are the example of symbols of AMG of the transition gate. So, in transition gate we have three symbols the input A output B and the controlling gate input G but we also need the complement of G which is G let us see how the transition gate is now used now we realize that a transition gate can be a good switch let us see how do we use it to make the circuit one of the most famous circuits is a tri-state buffer now a tri-state buffer reduces. So, in fact, the switch the switch we saw here this switch is nothing but a tri-state buffer. So, a tri-state buffer has an enable pin. So, the G is now labeled as an enable and both enable and enable complement are available whenever enable is 0 whenever enable is 0 the output we saw it is not connected to input and we represent the output the logic level of output to be Z the Z is a tri-state that means it is either connected to we need it not the ground. Now, whenever enable is 1 it simply acts in the buffer a 0 on A will would mean a 0 on Y or 1 on A would be 1 on Y. Now, let us compare this to a basic static CMOS circuit. So, we we are let us compare the two difference time. Now, the basic gate the basic gate in CMOS static circuit was an inverted which had two transistors the Y was the complement of A and CMOS and NMOS are not I mean the this let us say the source of one is connected to drain of other. Now, in case of transmission gates the basic gate here is not an inverted, but a tri-state buffer and it has a one separate input called the enable pin it uses it also uses two transistors but the basic functionality is that of a buffer. However, this also needs the complement of enable pin which should also add let us say one inverter and two transistors. So, the basic gate in case of a transmission gate is a buffer the basic gate in case of a complement with CMOS is an inverter. Now, we call this kind of a transmission gate as non-disturbing why non-disturbing is that because the noise on A is passed on to Y as we discussed earlier because whenever enable is one whenever this gate is enabled since the sources are connected to a drain these both of these NMOS and NMOS are conducting a noise of the source of a transistor can transform into the noise on a gate gate of the transistor. So, any noise on A will pass on Y. So, it is known that the tri-state buffers are noise foam with such a construction ok. Now, there is one more slight modification on to this tri-state buffer and we make out a tri-state inverter out of this let us see how we how we can do that it is a very tri-state inverter is a very very popular final project to that it is used heavily in construction of multiple let us see how and plus it is also restoring that means, the noise is not passed on to the output let us see how. Now, what we do is ok in the previous slide I want to mention one thing it says that a transmission gate needs only two transistors which is not exactly true yes it needs two transistors, but but it is assuming that the not of in enable is already available ok. Now, what we do here is that we we connect the enable we make let us say this the part here this part what does it represent in isolation what it represents is the these two transistors here this PMOS and this NMOS they represent and an inverter here, but the same input is not connected here NMOS is connected to E n and PMOS is connected to E n, but just like in case of a trans transmission gate buffer. A simple single input A is connected to PMOS here and NMOS here what it means is that yeah what it means is that whenever enable is one this is turned on this is also turned on because enable is 0 here enable bar is 0 and it is a simple inverter that means A this this whole circuit this this transistor here this transistor here and this transistor here these this circuit now is just an inverter simple inverter and whenever enable is 0 this is open and y is there. So, again we notice two things here it violates conduction complement rule the pull down is not the conduction is not the complement of the pull up y because we want to read output. Second important thing is that noise on A is not noise on A is not transferred on y because A is driving the gate input of the transistor this is the symbol the logic symbol of a tri-state inverter you can you can either either represented by this or by this in the case of the first one it is implicit that a conduction a complement of E n is available in this case we are making the connection explicit ok. So, just a few important things to remember a normal CMOS inverter a transmission gate buffer and a trans and a tri-state inverter. So, we see all these three basic gates now we see how tri-state inverters are used right. Now I mentioned very I mentioned that a tri-state inverter is most popular in construction of multiple. So, this is the case let us look at a 2 is to 1 MUX let us review the MUX functionality whenever the selection is 0 no matter what happens on D 1 the D 0 will be passed on to y. So, select select a 0 y will get whatever is present on D 0 similarly when selected 1 y would get whatever is present on D 1. Now, let us say if you would want to construct this MUX out of a complementary out of a static CMOS design style. So, what we would look for is we would look for first of all the Boolean expression now y y is equal to SD 1 by D 0 now as we we notice that any function should form of a complement we could say that y is equal to we could we could add a couple of complements here the complements and we could construct we could construct a pull down network out of. So, let us let us first see how now we could for constructing the static CMOS CMOS circuit this the complement the first complement here the top top most complement would mean adding an inverter at the output stage and the remaining of the the remaining circuit here the complement of SD 1 and SD 1 this remaining here would go down as a pull up and a pull down network right. So, let us see how many transistors are there ok the answer is 20 you could go back and verify let us let us see how how 20 right. So, this would mean AND gate AND inverter and a NAND gate here we have done some bubble pushing here to convert this AND AND into a NAND adding an inverter and again adding an inverter. So, each so a 2 input NAND gate if you go back and remember the 2 input NAND gate needs 4 transistors. So, AND in turn would need just it needs 6 transistors because one more inverter is added. So, the we have just labeled the number of transistors the reach NAND requires 4 additional inverter requires 2 again a NOR requires a 4 and a 2 and an inverter 2. So, in total this marks would need 20 transistors to implement. Now, let us look at the power of transmission gate in a specifically transfer not transmission gate inside a tri-state inverter. So, or or let us let us let us first look at transmission gate. Now, a non restoring marks we label this as non restoring because again it is transmitting gate we base and noise on inputs will travel to output that is why we say it is a non restoring. So, we need only 4 transistors how come? Now, the 2 of the trans both transmission gates can be connected the outputs of both 2 transmission gates can be connected to the output can be tied to the output. However, we have to make sure that only one of the transmission gate is active at one time how do we do that? We make sure by by connecting the inputs the the enables in such a way we connected S here and we connected S here to the bubble, but here in the second case the S is connected to the non-complimentation. Similarly, S bar is connected to the bubble here and S bar is connected to the non-complimented input here. What this means is that these the enable or the S connection to the top transmission gate and to the bottom transmission gate are both complemented. What it means if S is 0 if S is 0 the PMOS here is active as bar is 1 the P the NMOS here is active. So, this part becomes 0 if S is 0, if S is 1 in that case this is switched off why because S is 1 PMOS is off S complemented with 0 NMOS is off now this part becomes enabled in the S is 1. So, a transmission gate marks needs 4 transistors if we compare apples to apples which means we have to also take care that this S here would need an inverter this S actually would need an inverter here this is this S is connected here and S will be available here. So, this inverter means 2 more transistors. So, 4 plus 2 6 and the earlier one had 20 transistors the only disadvantage in the transmission gate marks is the non-restoring power right. Now, let us see an inverting marks what inverting marks means inverting marks means nothing, but the output is why is just a complement of the earlier marks we saw. So, why would be nothing, but the complement of the regular marks. So, there is a bubble there is a bubble here if you notice there is a bubble here yeah. Now, if we use a simple AOI type of gate then we see that we need 8 transistors to implement this using the static PMOS how let us see the output. So, let us yeah. So, D 0 D let us just look at the pull down first. So, pull down so let us so you have we have to see that the first S bar and D 0 are AND together. So, D 0 here and S bar this is an AND connection similarly S and S bar is again an AND connection both of this is an OR connection. So, this is an OR this this connection is an OR connection similarly the pull up part would be a complement. We saw the construction of AOI 2 to earlier this is exactly same only the inputs are labeled differently that is the earlier the inputs are A and B now they are D 0 and D 1 or this is the first case this is the first case or what we could do is we could use a pair of tri-state inverter we saw that this is the construction of tri-state inverter again if you are if we are connecting multistage tri-state inverter to construct a MUX then we have to make sure that the connections of S and S bar are complementary to the two stages. So, S and S bar are connected differently here D 0 and D 1 are connected in the same same pattern. So, this is very very similar to the to this circuit we saw earlier and also to this circuit we see here both utilize a transistor, but now this inverter sorry this inverted MUX here is the restoring type because all the inputs are at the gates. Let us look at a still bigger multiplexer we what we saw earlier was a 2 is to 1 multiplexer now let us look at 4 is to 1 multiplexer it two is one of the four inputs and there are two select lines. So, again it is a going back to your digital design basic 4 is to 1 multiplexer can be constructed out of two 2 is to 1 multiplexer with the the LSD S 0 controlling the two MUXes here and the S 1 controlling the MUX which controls the output. Now, we could a very simple circuit of this is connecting four tri-state inverters to the output now please note that here for 2 is to 1 multiplexer this one and this one where these are two tri-state inverters connected as a output of both of them is feeding by similarly for 4 is to 1 there will be 4 tri-state inverters output each of these outputs connected to 1. However, the enable will change now. So, the lowest the MSB that is D 3 will be S 0 S 1 D D 2 will be S 1 S 0 bar again D 1 will be S 1 bar S 0 and D 0 will be S 1 and S 0 bar also note that we would need transistor we would need inverters here to get the logic level values of. So, we need S 0 and S 0 complement we need S 1 and S 1 complement. So, we will need two two inverters one for S 0 complement other for S 1 complement. So, each of the. So, in fact, these inverters are shown here. So, S 1 direct direct connection again this is the nothing, but S 0 bar ok. So, we see that a circuit which has a very big comparatively a bigger boolean expression for a 4 is to 1 more is in implementation is actually not a very big circuit is just 4 tri-state inverters all connected in series to 1. This is the power of tri-state inverter in construction of noxious. Now, let us let us review this let us see an exercise of construction of a complex gate I would again request to do this to add these slides progress to try and do this on paper yourself. Now, so this we have we are we are very popular now you must all be clear how to do this. So, the easiest way what I would suggest is to take the non complement part draw the pull down and then take the complement and draw the pull up in these slides what we are starting with the pull up part. So, we will take the complement part. So, we just do a boolean rearrangement of this and we come up with the pull up part. So, this this what this means is that A and B would be in parallel the PMOS the pull up network A and B would be in parallel and it with C or B and E let us look at the next slide. So, this is how we do that A and B are parallel C and C is again in series with B and E being in C sorry C is in parallel with B and E being in series and these two are connected like this this is a series connection that represents this ending here this is the pull up part. Again pull down part not very difficult there is the complement of this. So, pull up pull down part is nothing but the the non complement with this part non complemented part. Let us see your next slide this is a non complemented part A B plus C B plus C A B in series C plus DNA. We combine both the pull up and the pull down part and construct the the pull circuit how many transistors you do not need to look at the circuit is to calculate that we have 5 inputs that means to that means 10 transistors 5 pairs. So, I would request you all to so at the end of this this lecture give it any Boolean expression you should be able to draw a static PMOS circuit also. We also saw that not all static C not all CMOS circuits or CMOS designs are designed this way. We also use the power of transition gate and tri-state inverter to construct circuits such as mass, but still this is the most popular technique for complex logic circuit. Okay now look at let us let us look at how after for a complex we arrived at a static CMOS we saw we now with the circuit in place you know how many transistors it is going to be. Now let us see a very basic layout how how the layout is made what things are taken into consideration each layout is a technology base is that means layout is a technology specific that means a layout is by technology and the channel length that is for example if the channel length is 90 nanometer there will be some set of rules which need to be followed. These rules come from boundary for example, the ASNC is the very is the largest company in the world based in Taiwan. So they will have according to their manufacturing processes they will have a set of rules which should be adhered to when we make the layout. So layouts in fact are very very time consuming the gates have to be fit fit together nicely. It is one thing to make a complex gate out of transistors and it is another thing to lay them lay them out the actual area of the gate the actual how much space the gate occupies on solution is very much determined by how well it is laid out. So the basic methodology is that VDD and GND rails when I am an assay rail I means they are connected to the power supply and there is a copper interconnect on the layout that they are called VDD rails VDD and GND rails they should ever that means what it means what abutment means is that each first of all all these the all these cells such as muxes and or inverts and more latches with tops come my time we call them standard cells the standard cells are the basic building blocks of any different design. So usually what what happens in industry is that already the let us say design team let us say our design team is making chips for the mobile phones let us say. Now when they start making chips they already have a library of standard cells and either they have or either some team in their own company has designed all those standard cells and put them in place or they buy it from any platform but to start designing the logic they need this standard cells the library is in place we will see much more of this in synthesis. So these are the first standard cell and a combination of all these cells is called a library. Now what we VDD and GND what abutment means is that all three cells should have fixed height but they can vary in width we will see later why this is the first major rule then a different set gates should satisfy design rule that means that there should be some minimum spacing between a different gate always be the convention is that in most at bottom and bottom and P most at top so we and more the down and P most I should be connected to VDD so we need to go to the top all gates should include valence of suspect contact so in this case when see when we draw a transistor a transistor based circuit on paper we do not show the substrate and the well contact but layout needs to show that because layout is the one that goes to counting for manufacturing the circuit on paper will not go to counting it is only the layout and that too in a machine readable binary format it will go to the counting for manufacturing so all connection should be explicit in every very few how good a layout is often determines how well the circuit can be manufactured how well the design can be manufactured. So let us see an inverted layout we have already discussed this so VDD and the ground grains run parallel to each other there will be one there will be one fixed height now let us say I am designing this inverter and I also want to design an AND gate or an AND gate so I have to make sure that the all of the gates are designed I design will have same height so that an AND gate here let us say when let us say I construct a circuit now often of an AND gate so how would I do that I would I would make an AND gate here which would be connected to this inverter here. So the VDD rail if continued here should that is why I need to keep the height same so that both of these cells can be placed between VDD and GND rail. So VDD and GND rail it stays between them determines the height of all the cells right they should be same for all the cells in the system they are exceptions but only for very very complex gates it is not usual that is why we say that all standard cells should be of free mounted. Now in the in the V part here we also show the explicit substrate and well taps so the NMOS here would need a ground tap for substrate a PMOS here would need a this the shaded gray area area this this area represents the well so there is a well tap. Let us look at a slightly more complex gate this is nothing but it is NAND gate a free port NAND gate again how do we need a layout so VDD GND rails are very very clear the pull down part the gray part here is the NMOS diffusion here the so let us see now the pull down network here this pull down network a b and c these are all in series so let us let us start on ground ground connected to C now it is not not sorry not the C but the ground connected to the diffusion again so this is again diffusion diffusion connected to diffusion again diffusion connected to diffusion and again a diffusion going to 1. Correspondingly in layout we see ground rail this is a contact this is a substrate tap connected to diffusion diffusion diffusion and then this goes to 1 the blue part here corresponds to the pull down network you see the pull up network now pull up network VDD needs to be connected to 3 diffusion layers here so we see now VDD this is this gray part is the well we cannot see the gray part here because again the gray same as the diffusion gray here so it is camouflaged VDD here is connected to is connected to diffusion by a contact now see here in the in the in the pull down network we notice that the contact is needed to connect it to ground but the region here this region and this region here has no contact because none is needed but here in the pull up case the VDD is connected to contact the VDD is connected to this contact and if you notice the VDD should be connected to all 3 diffusion but what about here what about in the layout now in the layout the connection from A to B the connection from B to C actually the PMOS this particular PMOS and this particular PMOS they have both flip in the sense they both share this common VDD why is this because we want to minimize contact we want to minimize the metal and metal routing so this is the one way of doing that is that VDD is connected to A here and this now VDD is this metal is being shared between being again let us look at the inputs A B and C so inputs connect to gates now what are gates gate made up of data made up of poly silicon if we remember the unit 1 the construction of a MOS the gate is nothing but a strip of poly silicon each input each input here goes to 2 as transistors a PMOS and an NMOS so this A layout is nothing but a wire of poly silicon this is a wire of poly silicon connecting the gates of one PMOS and one NMOS so A goes here vertically again B takes a T2 this is to satisfy some design rules again C takes a T2 so A B and C are pre-input let us look at why which is the output now output is connected again output is connected to the NMOS here at the bottom and let us look of PMOS at the top so why here okay now so we see why here is connected to the top most so NMOS are stacked it is connected to the top most here so this actually this layout and the schematic do not match completely because here in the schematic B is the top most NMOS but here we see that in fact C is the top most stack so it does not matter so why is connected to this NMOS here which is C and again why now needs to be connected to all three transistors at the top so the connection to C this one is the connection to C this connection is common to both A and B so we see that very intelligently VDD connections to all three MOSes and the output connection to all three MOSes the connections for two transistors have been shared this is to make sure that the number of contacts remain in a node we will see one example later now this the height is 40 lambda we see is the feature of size to the height is 40 lambda and this this 4 lambda is nothing but a design rule which says that like the level of a design rule says that there should be a spacing of 4 lambda from the the other let us see these design rules are just examples they can be these design rules are different depending on different technology so I hope everybody now can do the basic layout and understand a basic layout or still diagrams are a very popular way to help plan layout quickly since they are abstract representation they need not be on the screen obviously to show different kind of layers different like the layer poly-silicon will have you would need color pencils or different kind of crayons to draw this layout then do one or two explain this yourself on paper to make make sure the context is clear so the A is an inverter layout and D here is a NAND gate layout different legends are shown on the right side so contacts are shown by a flag that is a five bar and division of the gray bar and so on wiring tracks so a wiring track is a space required for a wire so an example could be the design rule could be that a wire should be of 4 lambda bit and between two wire tracks there should be a spacing of at least 4 lambda so let us define a new parameter called pitch a pitch is a is a combination of this wire bit and the minimum spacing it needs so the pitch of this wire is 8 lambda that is 4 lambda is the width and 4 lambda is the minimum spacing that is required so the height and the height of the transistor can be represented in terms of wiring track so for example a design rule of this particular technology says that the diffusion should be at least 4 lambda high and again this poly-silicon wire is running between them the gate it should be at least 4 lambda so a transistor is in fact taking more than 8 lambda let us see an example of one more design rule of well so another design rule could be that well should be around the transistor by 6 lambda so what it implies is that between opposite transistor favors that should be at least 12 lambda because you would need 6 lambda down here and again 6 lambda down here so the distance between these two at least 12 lambda what it again means is that if the distance is 12 lambda you could actually draw a wire between these two connectors why because it satisfies the wire design rule how do we estimate the area of a gate after the layout when we are drawing the layout we estimate the area by counting the wire that is for example for this kind of a gate we could estimate the area by since the pitch of the wire is 8 lambda we could be multiplied by 8 to except in terms of lambda so the let us say this this is 40 lambda so this is 5 wiring tracks this bit is 32 lambda so the area of this gate is 40 lambda by 50 lambda this is an example we saw the construction of O3 AI in terms of static CMOS earlier now let us see the the this is the layout I guess this is yeah so this is the layout in terms of stick diagram so I will not go into too much detail of this I would expect all of you to first on the on the left hand side could be transistor level gate design which is called the schematic in the right hand side you study this layout is the diagram and satisfy often with this construction you would see some interesting features that is sharing of contacts so one thing is it is clear when one with observation you could do is that you see now more tabs on the NMOS than compared to TMOS so you could say that the NMOS circuit requires more parallelism compared to the NMOS network so the the since if the network is feels it would require less contact apps if the network is silent since it the parallel network needs to be connected to VEDM GND each once you get connected in the common network you will see both apps in the parallel network right so this is again estimating area this estimating area is not an and it is not very easy to do it on paper there are many tools available for layouts I am maybe yours one of the other vectors or courses have layout technique and when you use these tools you could we could actually estimate area one thing is very clear one thing is fixed let us remember that the height of the statistics so you would have to draw a layout within those restrictions it will be high fixed and varying depending on how many so let us let us review the topics we studied in this chapter we saw the construction of some complex dates using static CMOS techniques and the static CMOS techniques will be the most popular techniques for construction we saw transmission dates we saw a price set inverter both are very popular in construction of course when we saw basic layout design techniques we saw an interesting layout of the input now and then I want to request all of you to take the layout of understanding of the layout of OPAI and if you have access to some tools that you can draw layout it would be excellent. Thank you all of you in next lecture we would look into this how to estimate and calculate the delay of the surface so two parameters are very important in during gate design one is the area other is the speed or the delay of the surface third of course there is one more parameter which is power but let me look into more detail in the delay part of this thank you all.