 I am Kurula Vagis from Department of Electronic System Engineering Indian State of Science Bangalore. I am going to give this course on digital systems design with PLDs and FPGAs. As the name suggests it has something to do with the design of digital systems and we will be implementing those systems in devices like PLDs and FPGAs. So over the next 40 hours I am planning to complete this course from the basic to advanced portion. But before we start I want you to do a small exercise, I will please take a pen and paper and write what is your idea or expectation of this course okay. So basically what you think this course is about, what is it condensed and why are you learning this course. Maybe some people are taking this course to learn the basics of digital design and learn it thoroughly. Maybe somebody is trying to get a job based on this course or could be somebody else has a similar course in the curriculum and want to complete the course with some good grades. So whatever may be your purpose behind learning this course please write it down. And the last question I want to ask you is what do you think should be taught. So from the like you have some expectation of the course that is why you have come to this course. So what do you think should be the content of this course please write it down. The idea is that in the next few slides I am going to state the objective of this course what are its major contents. So that you are clear at the outset what you are going to learn by the end of the course. It is not good if I do not tell you at the beginning and you run through the course all the way till the end and realize this is not something what you wanted to learn then there could be a problem. So when you compare what is the content of the course, what is the objective of the course with your expectation or requirement. And if there is a serious mismatch you can choose not to attend the course and waste your time that is a basic idea. So let us move on and let us see what are the content of this course. So mainly the course objective is digital system design the main focus is digital system design by which I mean that somebody gives you a specifications of a system from that specification how do you go about implementing the system okay. So the system could be a small system like a counter an arithmetic logic unit or it could be a microprocessor or it could be a system on chip a complex system on chip whatever. Given the specification how do you go about implementing this having only the knowledge of the specification and the domain. How do you go about implementing it that is the first objective when it comes to the next one say very specific objective. Suppose you have an algorithm say you have a signal processing algorithm for a filter how do you design an architecture for that filter and in the parlance of digital VLSI many a times it is called front end design and front end means that you given the specification from the specification you go all the way to the logic design. That means the design in terms of gates and flip flops and similar to the front end there is a back end design which takes this gates and flip flops all the way to transistors and the mask required for the chip or the integrated circuit manufacturing okay. So in this course we are mainly concerned with the front end design not the back end design. So next step is that when you design such a complex system you have to partition the system into pieces into blocks and now you have to take each block and design the blocks in detail meeting the specification of each block and at least you have to do a timing analysis of each block to be able to work. There are many other analysis you need to do but at least at a basic level you should be able to make it work in a functional way and it should meet the basic delay requirement. The third or fourth objective is the device technology for this course we will be using two device technologies one is called the programmable logic devices or PLDs the next one is field programmable gate array or FPGA. So we will be using these devices to implement our design and fifth point is that for entering the design for designing the blocks or designing the system we will be using a hardware description language called VHDL we will see what is VHDL later. So design entry in this course will be using VHDL there is no particular reason to pick up this language you could one could use languages like Varylog but traditionally the FPGA vendors use to support VHDL more than Varylog and it is easy to move from VHDL to Varylog than from Varylog to VHDL. So I hope that once you have learnt VHDL you can easily sit over to other hardware description languages when required and I must tell that the main focus is still the digital system design not the PLDs or FPGA not the VHDL we are going to learn this but the main focus is still the digital system design not PLD, FPGA, VHDL we will learn all these thoroughly but the focus is digital system design. And in the course of the studies we are going to have some few case studies I will draw examples from communications, embedded systems, computer architecture and all that these case studies. So I hope you have some basic understanding of these topics it will help you to understand the course better and we do not have time for too many case studies. So I hope you have a background in these topics so that is the course objective and let us move on and the next question to ask is what is the prerequisite for this course and or what are the basics you should know before embarking on learning this course and I really assume that you have some background without which this course cannot be learnt. So let us see what are the backgrounds required so essentially you would have gone through some digital systems course or digital circuit course in the undergraduate program I am not going to cover that part I really assume that you are thorough with these particular topics to start with the Boolean algebra you should be thorough with the Boolean algebra some kind of minimisation algorithm at least you must have done used kind of map for minimising and you should have learnt gates. The combinational logic like the encoders, decoders, multiplexes, demultiplexes add a subtractor and things like that and the sequential circuit like flip flops, registers, counters all this should be known at the functional level and you should know the timing parameters of combinational logic and the sequential logic at least you should know what are the delay parameters associated with the gates associated with the flip flops there after we can build the complex timing parameters based on this basic timing parameter. And nowadays you know that all the digital circuit has built of CMOS technology or NMOS and PMOS transistors maybe in the undergraduate program you would have learnt about some other technologies but that is not important the currently what is used is CMOS. So if you are not thorough with CMOS circuit please take some time to learn the basic NMOS, PMOS, the CMOS circuits of various gates and so on okay. So the next background I would require is some basics of microprocessors because when we try to learn design as an example I will bring in the microprocessor as a case study. So I hope you know some microprocessors like 8085, 8086 or anything you have learnt it could be some microcontrollers like 8051 or a risk processor as part of your computer architecture it does not matter if you know how the processors are designed what are the blocks in microprocessors that should suffice. And the next background I require is some basics of computer architecture basically the arithmetic logic unit, instructions at and so on. So if you have not learnt you can refer to some good books on computer architecture and pick up the basics of the computer architecture maybe I am not sure I will if required I will draw some examples from the computer networks or the communication networks I hope you would have learnt at least one course in communication networks I will try to limit the case studies the first two but if required maybe I will cite some case studies from these communication networks too. And so these are the prerequisite if you are not thorough please take a break learn this from any textbook any good textbook and come back and learn this course. So before getting on to review the basics I want to state the contents of the course various parts of the course this is essentially five parts the main focus will be on advanced digital design I call it as advanced digital design because I assume that you have the background you know the basics of the digital design okay. In this advanced digital design part we will be mainly concentrating on the top down design or hierarchical design in particular in a serious digital design there are two parts one is data path and the other is a controller. And the data path talks about the computation the basic computation. So this is the path where or the circuit where all the computation happens and the controller is one which moves or which controls the data movement within the data path and there could be one controller or multiple controller. And definitely after this we should be concerned with the timing that means how to get to meet the timing requirements part of the specification. And there are many other things which when we go ahead with this topic we will see the next part is the programmable logic devices or PLDs these are used in a small way for glue logic in digital design. And we will see the architecture of the PLDs the evolution of this architecture the application of the PLDs how to optimally design a circuit using the PLD. The next part will be the field programmable gate arrays or FPGAs and we will see the architecture of FPGAs the application of FPGAs and how to optimally design using FPGAs and so on. And the fourth part is this particular language hardware description language VHDL the expansion is VHS IC hardware description language that means very high speed integrated circuit HDL. And I want to emphasize that we will not be learning all about VHDL our focus will be something called synthesis that means synthesis means that you write a code you describe the hardware in a language and use a tool to generate the circuit. So our focus will be to write synthesizable code that means you write some description of a hardware and give it to a tool synthesis tool it should be able to generate the circuit that you intend to generate ok that is the basic idea of synthesis. Many a times people write VHDL code which works very well in simulation but it does not properly synthesize or it makes no sense as hardware circuit. So we are not interested in that this being a hardware design course. So we will be concentrating on synthesis aspect of VHDL similarly this course contain many case studies we will start with the case studies minor one to illustrate the design methodology design steps and so on and when we come to the end of the course we will take more complex case studies. So these are the five parts of the course but I am not going to teach it sequentially from say from the top to bottom I will start with the advanced digital design proceed come to a logical end then come back to VHDL to cover the basics of VHDL then go back to this advanced digital design then maybe handle these two you know complete the remaining VHDL with case studies and ultimately tie everything together in this part ok. So that is the essential course contents by now I think you should have some clear idea what this course is going to be but definitely that is the content I cannot talk about the way in which I am going to handle this topics which could be little different which you have to wait and see my treatment of this particular subject. So next in few slides I would illustrate or I will say what I am expecting you to achieve at the end of the course so or what competence is you will be hoping to develop or I expect you to develop at the end of the course. So at a system level I expect that you will be able to design a digital system given the specification meeting the essential functional timing requirements or constraints you should be able to do that in particular if you have an algorithm you will be able to design an architecture with the data path and controller with all the issues you know related to it sorted out. So let us look at each module level so with regard to digital systems itself you will be able to design the data path and the controller using the high level combinational and sequential blocks ok. What I mean by higher level combinational and sequential blocks is that when you design in your undergraduate course is something like say a full adder you will use some gates when you design a counter you will use some flip flops and few gates and you literally you know start with the truth table work out the Boolean equation minimize it and implement it with gates and flip flops but when you design a complex system we will not be able to do it at the flip flop and gate level we are going to use the non combination blocks like encoder decoder multiplexer demultiplexer adder subtractor and sequential blocks like registers counters and so on ok. So that is what I mean by higher level combinational and sequential blocks and you will be able to solve the functional and timing problems in data path many a times with your background maybe you are able to solve some functional problem but not the timing problems. So we will concentrate in this course quite a lot on the timing aspect of the digital design basically at the end of the course I hope you will be able to think timing ok many a times people are able to think functional aspects but I want you to think the timing aspects to develop that capability and when you design a controller or finite state machine there are various issues functional and timing issues and you should be able to solve that and the last point is that when you have a digital system you may have different parts of the digital system working with different clocks. And or there may be a part of the system working with one clock and you will receive some manual input from a limit search or a keyboard to the system and unless this is handled carefully because an event happening in with regard to one clock or one manual process reaches the another part unless it is synchronized to the receiving domains clock this won't be registered properly. So that is called synchronization aspect and that as we will at least the basics of synchronization will be taught in the course I may not have time to teach the synchronization issues in very detail in this course but I will make sure that the essential synchronization will be handled in the course. So let us move on to the VHDL the VHDL part at the end of the course you will have the competency given a block given a design you will be able to write a synthesizable VHDL code to implement this block and in the reverse way suppose you have a VHDL code given to you then you should be able to infer what is the circuit that this particular code implement or given this code to a synthesis tool what probable circuit the synthesis tool will generate. Many a time this is required because you will be working in a project team you may have to handle the code written by another designer who has worked earlier on the project and unless you are able to infer the functionality of the VHDL code you will not be able to proceed. So this is a competency which is required and we will also learn how the VHDL simulator or simulation tool simulate the code why this is important is that you know that the language is a sequential language but the hardware is concurrent suppose you have say 5 outputs from some 10 inputs in a combinational circuit any one of the input changes all the 5 output can change but in a language when you write 5 outputs it has to be written one after the other but when you simulate the functionality of this 10 input 5 output system everything has to happen suppose at 100 nanosecond one of the input changes say after some time all the output should change. So we will learn how the simulation tool handle the concurrency and from a sequentially written statement it is not very complex but it is for our understanding that is not for us to break the head it is for the simulation tool to do all that what is necessary but a clarity in understanding is important and in a complex system you cannot manually verify or manually simulate and verify the circuit we have to automate it. So we will in VHDL these are called test benches that you can automate the whole verification process so we will learn how to write test benches in VHDL so this is the competency I hope you will develop at the end of the course with regard to VHDL. So let us move on to the next topic PLD so at the end of the course with regard to PLDs I hope you will be able to choose a particular PLD for a particular application this in the case of PLD it may not be very complicated but still you would not at least choose a PLD which is too small for to accommodate the design or you may not spend too much money in choosing a complex PLD very complex PLD for a smaller application and so on. And you will be able to design and code to exploit the architecture features of PLD we will learn the architecture features of PLD and we will learn how to design properly so that those features of PLDs are best used in our design so that the resources are not wasted or we get the required timing performance. So these are the competencies you will develop at the end of the course so let us move on to FPGAs with regard to FPGAs once again you will be able to choose a particular FPGA for a particular application and as in PLDs you will be able to use the architecture features of FPGA to design and fit a particular design within an FPGA and you will be able to design to meet the area and delay constraints and estimate the power consumption of your implementation within FPGA. So there are these are little more elaborate than the PLDs and these devices are complex more complex than the PLDs so these are the competencies with regard to the digital system design, VHDL, FPGAs and PLDs I hope you will be able to develop at the end of the course. So now I want to in the course of the lectures I will be suggesting some exercise for you to work of and this will cover the various aspects covered in the course and basically deal with the concept. Many a times students are little worry about the textbook kind of simple exercises but you have to trust me it is very important to do exercises which bring clarity to the concept. Many a times people are in a hurry to design the real life systems but unless the concept is clear you will not be able to sort out the problems you encounter come out with elegant design and creative designs and so on. So it is very important to work with exercises which bring clarity to the concept than some gimmick. So we can do all gimmicks you know a PLDs or bringing some LCD display with some text and all that that is basically sometime it is a gimmick or it impresses people but it may not enhance learning or enrich your understanding. So I will be giving exercises or telling you to do some exercises which bring clarity and I will suggest some mini project towards the end of the course so that you can try to apply what you have learned in the subject to sort out some issues in a small case studies and for these exercises you can use the free web editions of the PLD and FPGA tools from major FPGA and PLD vendors like Xilinx, Altera, Atmel, Lattice etc. If possible you can try to get some PLD FPGA kits which are low cost and try to implement some of the exercises we discussed on this FPGA kits. So these are the points I want to tell you about the exercise. So let us move on to the last part of the introduction these are the references. So these are some of the references but I will not be using any of these references very thoroughly I will be using my own notes, my own slides and my own way of handling the subject. But these are very good books the Walker Lay digital design it is a very good book. So even for the basics in digital design you can use the same books suppose if you are not thorough with the basic in digital design you can use this book to learn the basics in digital design. VHDL for Programmable Logic by Kevin Cahill this is a good book for VHDL for synthesis little bit old but very good book. You could use any book which handles the VHDL for synthesis then the VHDL book by Nawabi it is a kind of complete bible and then for CMOS circuit you can use Westi Harris and Banerjee's book on CMOS VLSI design there is a book by Charles Roth it is a very good book on digital design I have not listed here. And I will be referring to various literature in this field and FPGA PLD data sheets. So you can refer to them also I will say whenever I use these references. So this gives an introduction to the course basically I have told what is the focus of the course, what is the objective of the course, what is the content of the five contents of the course and the competencies I hope you will develop at the end of the course at the system level and in each part that is what I have told and the reference books. So this is the basic introduction to the course. Now we will take some time to review the basics which you have already learned which I assume you have but I will run through give an overview of the field and run through some basics not thoroughly it will be a quick maybe 1 or 2 hours of lectures on the basics then we will move on to the real digital system design. So let us look at a digital system design with PLDs and FPGAs and overview. So I want you to have some clarity about learning and design. In learning you always go bottom up that means see normally you start with transistors like CMOS, NMOS transistor, PMOS transistor, CMOS transistor and so on. Then after having learned quite a bit about transistor you learn how to build gates based on this particular transistor. Say AND gates, NAND gates, OR gates, NOR gates, inverters and so on. Then you will learn how to build combinational circuit based on this gates ok. Then build sequential circuit like the controllers or the data path or registers with combinational circuit all that you will learn. Then ultimately you will learn how to interconnect all these in a system. So when you learn you go from the smallest pieces to the complex system. But when you design it is opposite process we adopt we go top down. Suppose you want to design a microprocessor then you break the processor into pieces like ALU, registers, say program counters, stack pointer and so on ok. Then you take one of the pieces say you take ALU and break down into adder, subtractor and so on. And then you pick one of the pieces from that and the adder is converted design in terms of XOR gates, AND gates and OR gates. And ultimately these gates are converted to CMOS transistors. So the hierarchy in design is always top down. So anything complex you should try to do top down ok. Suppose you take an aircraft you cannot start with somebody designing a wing, somebody designing a fuselage and somebody designing an engine and ultimately bring it together, fit it together without any idea of the aircraft ok. So anything complex maybe it is true with the software suppose you have a complex software you cannot arbitrarily design pieces and put it together or you organise a function a conference. So you cannot you have to have a global view say somebody will handle the program, somebody will handle the stay arrangements, somebody will handle the finance, somebody will handle the travel and so on ok. So anything complex should be handled in a top down manner but learning should be always going from the basic to the complex ok. So I am going to illustrate that in picture to bring some clarity to it ok. So let us move on to this. So say at the when you learn at the basic level I call it level 0 you will learn about MOS transistor say you pick up this NMOS transistor then you know that there is a P type silicon and N type source and drain then polysilicon gate source and drain and the PMOS it is opposite you have the substrate is of N type and the source and drain is of P type. Then you know you learn the ideas, VDS characteristics what are the how the ideas change with regard to VDS and for various VDS and so on and you learn various regions. You know you have the linear region saturation region cut off and you learn sometimes some symbol. So this is the symbol for an NMOS you have a drain source and a gate and when the gate is at a higher voltage with regard to source it conducts and for the PMOS when the gate is at a higher voltage with respect to source then again it conducts normally it is opposite voltage we apply and we know that then NMOS is a good conductor of 0 and PMOS is a good conductor of 1. Having learned this MOS transistor then you move on to the gates. So take the case of an AND gate, AND gate is designed using PMOS and NMOS transistor. So if you look you have learned this part is a NAND gate and this part is an inverter. So this is a NAND gate followed with an inverter. So you can see that if A and B are 1 these two transistors will be off this will be on. So this essentially connect this point to the ground which inverts it. So if both are 1 1 you get 0. And any of the input is 0 then you can see one of the transistor will not be conducting. So this path will be off and one of these transistors will be conducting. So you will get a high here so accordingly you will get a low there. So and that is the symbol of a gate. Similarly you have like AND gate you have NAND or NOR XOR gate and the inverter. So in the level 1 having learned the transistor you learn about the gates what are the input output relation in terms of the binary values this gate implement. Now once you know the gate you are able to go to the next level level 2 say take the case of a full adder. The full adder has a 3 input AB, 2 bits and a carry input normally from a previous stage which gives a sum and the carry out which you can use it in the next stage. So this is a full adder is a modular adder slice which can be combined to form bigger adders. So this is the truth table and you know that if any one of the input is 1, sum is 1. Any 2 are 1 then the sum is 0 and the carry is 1. All the 3 are 1 then both are 1 ok. You have studied and if you work out you know minimize then you will end up with this expression. So this is the next level in the level 3 you move from the full adder to say a 4 bit ripple adder. So using 4 full adders we are building a 4 bit ripple adder this is the A0, B0 the least significant bit of the inputs A3, B3 are the most significant bits of the inputs and these are the sum this is the carry into the first stage this is the carry out of the next stage is connected as a carry input to the next stage and so on. So knowing the full adder we will be able to build a ripple adder at the next level. So we go further maybe we go to a multiplier so this is how the architecture of a multiplier looks. So if you care to look at the multiplication algorithm the paper pencil method say here we are putting a 5 bit multiplicand and a 5 bit multiplier for each bit of the multiplier you form the partial products and you know that when it comes to the second bit this is the power of you know 2 raise to 1. So the partial product is shifted if the bit is 0 the 0 is shifted so ultimately you form the 5 partial products and you add it together you get the product. But then it involves lot of adders so in a realistic design to save the area we use a single adder and form the first partial product add to the accumulator which is 0 then form the next partial product add it. So here you have an accumulator you have a multiplicand you have a multiplier ok. So look at the least significant bit of the multiplier if it is 1 the initially the accumulator is 0 you add the multiplicand to it then you instead of shifting the partial product left you shift the accumulator right and then this the least significant bit of the multiplier is gone. The next bit comes here say look at it if it is 0 you re-circulate you take this result itself put it back and shift it because it is equivalent to adding the 0 instead of adding 0 we take this and put it back and so on say do this 5 times then you will get the desired result. So which involves 3 registers and an adder and some control which is not shown here so we can say this is the data path of a multiplier which basically use our idea of the adder ok. So that is how the learning happens you started with the transistor then move on to the gate then we have moved on to the full adder then we made the ripple adder then having some idea of the flip flops you are able to build a multiplier or you are able to understand the functioning of a multiplier very thoroughly. But when you design so let us look at the design how to design this multiplier you do the offset. So knowing the algorithm of the multiplier you design an architecture for the data path of the multiplier consisting of 3 registers and an adder. Now we have to design this adder and the registers in a detailed way. So let us pick for example the adder say assume that is a 4 bit adder 4 bit multiplier then we will design this 4 bit adder with 4 full adders cascaded. So the adder is broken down into 4 full adders now you take the full adder and design using gates using XOR gates and AND and OR gates so this is a majority logic any 2 or more than 1 input is 1 then the carry out will be 1. Now the moment you do that we know all the gates and then go to transistors and ultimately the chip masks are built from the transistor layout that is not shown in the picture. So up to here from here to here to here is the front end design that from the spec the multiplier algorithm we have come to the gates and the flip flops in this case there are no flip flops shown but you know essentially a register is composed of flip flops suppose a 4 bit register is nothing but 4 flip flops in parallel. And so this is very easily designed as 4 flip flops in parallel so this is how the design proceed in a top down approach and of course you should have the domain knowledge to design you should know all the pieces it is very important that you are thorough with all the building blocks so that you will be able to design it thoroughly and you should be able to sort out the problems as you you know you encounter as you design ok. So this shows the hierarchy of learning and hierarchy of design so let us move on. So let us ask what are the major constituents of a design that means suppose somebody tells you to design a multiplier what should we focus on ok. And many a time students the smart students say it should be low power it should be low area it should work at 1 gigahertz frequency or high clock frequency and so on ok. But think for a moment you design a multiplier and you say it works at 1 gigahertz but given some input say you give to the multiplier 7 and 5 and it gives an output like 42 but you say it works at 1 gigahertz it is of no use ok or you say it works it consumes hardly any power only micro watts but the answer is wrong then it is of no use. So that tells you that the primary part which we have to focus on as a function or the logic ok. So when you design the first part or the first constituent the first focus should be on function and logic the power area timing everything comes later ok. The first will be function and logic and you are lucky in this way because you would have learnt all the building blocks in a basic course and I will list there are two parts combinational logic and the sequential logic. So the combinational logic you would have learnt all these you know you would have learnt Boolean algebra you would have learnt minimisation some algorithm like Carnot Mop and things like that you would have learnt various functions like AND, NAND or NOR, XOR, inverters the gates implementing these functions something called encoders and decoders, multiplexers and demultiplexers, parity circuit, comparators, priority encoder, open drain outputs, tri-state outputs, metricers, adder, subtractor, increment, decrement and so on. Now we are going to use all of these ok some may not be explicitly like we may not do any minimisation most of the time this is done by the tool in a higher level design but an understanding of this is very much required to grasp the concept and bring clarity into the whole game. And so all these are very important what are these composed of how these are designed and so on. So let us move on to the sequential logic when we come to the sequential circuit the basic building block is the flip flops various type of flip flops like you would have learnt D flip flop, SR flip flops, JK flip flops, T flip flops and latches and there is a difference between latch and the flip flops latches are by definition transparent when the clock is high the input output follows the input and when the clock is inactive the last input is latched on to the output. In a flip flop normally works on the clock edge when a clock active clock edge comes the input is transferred to the output provided some input meets some timing requirement we will see that. And you would have learnt some kind of counters like ripple counter, synchronous counter, ripple counter is of no great interest to us so forget about it we will be talking about synchronous counters, various registers, parallel registers, shift registers and so on. And the finite state machines I am not sure whether you have learnt this in the basic course. But we will I assume that you may not have learnt and we will put some time developing the concept and the design of finite state machine. And various memories are important various kinds of ROM, read only memories, erasable programmable read only memories or electrically erasable PROMs. Similarly static RAMs these are fast memories which is used in a computer system at the level 1 as caches and level 2 caches and all that synchronous SRAM nowadays everything is synchronous with the clock DRAMs is the secondary level of storage in a computer system. These have the large capacity but it is not as fast as SRAM and your FIFOS which is first in first out memory that means you have two ports on one port you write and one port you read many times addressing is implicit that means you do not specify the address the first data you write will go to the first location and the second you write go to the second location. And when a circuit read the output it reads starting with the first and the read pointers and write pointers are incremented depending on the read. And one has to take care that one does not overtake the other and so on ok. That there is no overflow or underflow similarly CAM normally it is defined as an opposite of a memory here you have data stored in a memory and you look for you search for some content that means you provide data it says the location where that particular data is stored. So in a normal memory you provide the address you get the data but here you give a data then you get the address which is used in the cache memories and all search algorithm lookup algorithm use CAM for it implementation. So this is the major constituent of digital design that is combinational logic and sequence circuit and if you care to look at a data sheet maybe of a gate or a PLD or a microprocessor the first thing in a data sheet stated is the function of that integrator circuit. So that shows the priority the function as over other factors. So we have little time left let us move on to the with some of the blocks we have discussed I am not going to deal with all the blocks. Let us pick up some of these combinational blocks and just revise so that it brush up your memory. So let us move on so with regard to minimization all of you must have learned Karnoff maps okay this is a very systematic method of minimizing from the min terms to minimal product terms and this is a graphical tool it is for humans to work out it is not for computer to work out. The equivalent computer algorithm is called coin maklowski as in Karnoff map it provides a minimal solution but the complexity is very high it is kind of it has exponential complexity because it is start with the min term. Suppose you have 5 variable problem like A, B, C, D, E and you already given expression to coin maklowski like A, B bar it you know that it expand in terms of the 5 variable. So already minimized expression is taken back to get the absolute minimal or optimal the product terms okay that is the idea of coin maklowski but you know that given an input that you have 2 raise to n min terms. So the complexity is exponential and it is very hard to compute using the coin maklowski. So mostly the tools use a heuristic algorithm called espresso this is based on coin maklowski but it is faster. So that means if it has a product term already which is simplified is not going to expand all the way to the min terms and start reworking back. So but since it uses some kind of heuristic method or shortcuts it is not going to produce an exact optimal or minimal solution as in coin maklowski but it will give a near minimal solution and we do not care because many a times we are not worried about the area so much nowadays like it does not matter instead of ending up with say 25 product terms you might end up with 27 or 30 product terms it should be okay in the present technology. So these tools will use espresso kind of heuristic base the tools for minimization or algorithms for minimization and the next thing you should realize a little bit about the real life is that all these applies many a times to the two level implementation that you talk about and or or and or sum of product or product of sum which have learned in your the undergraduate program or the basic course but in real life when you come choose the FPGAs or ASIC you do not stick to the two level implementation because it is not possible. So you will have to implement a particular circuit in multiple levels of logic so you will have to apply some decomposition of a Boolean expression or a circuit in multiple terms so that multiple levels can be implemented and suppose when you have a multiple output suppose you have 10 inputs and 5 outputs then you will have to for a minimal expression in terms for the multiple output you will have to find the common sub expression like maximal common sub expression of all the multiple output. So you need algorithm to find the common sub expressions across the multiple output which minimizes the area and many a time this involves the steps like the factoring, substitution, flattening etc for the multi level implementation of the digital logic. So the minimization is more complex than you have learned it uses heuristic algorithm and it concentrate on the multiple output minimization and multi level minimization and so on. So these are complex those who are interested can look at the synthesis of digital circuit these are the that is the subject which looks at this minimization algorithm. So let us move on so let us look at this part functions and gates I just want to tell you that you would have most of the time you confuse the gates with the function okay. So you take an AND gate then this AND gate you take it to implement the AND function but many a times the AND gate can implement many other function than the AND gate AND function. So let us look at the true table of an AND gate say like in an AND gate when both the inputs are 1 then output is 1 that means A and B are 1 the output is 1 in the case of AND gate. So here we are treating the inputs are active high and output is active high. So then it the AND gate implements an AND function but if you treat the AND gate inputs and outputs are active low look at the true table if A B are active low and look at the true table if any of the input is active any one of the input is active then the output is active which is nothing but an OR function. So if for the same AND gate if you treat the inputs and outputs are active low then implements an OR function so that is shown as an OR gate with showing the active levels. So AND gate can implement OR function when the inputs and outputs are active low and if for a smart student it can easily you can easily know that this is nothing but applying the De Morgan theorem. So Y is AB and if you take Y bar is nothing but AB all bar which is nothing but A bar or B bar. So I am showing bar by a slash because I can use the text for that so that is shown here. So an AND gate can implement AND function or OR function and which is basically applying the De Morgan theorem or building the De Morgan theorem into the concept okay. So in the next lecture we will continue with this so today in the second part of the course handle basically we have looked at the major constituents of a design that is function basically what all you have learned in the basic undergraduate course the combinational logic the sequential combinational logic all that is important then we have looked at the functions AND gates before that we have looked at the minimization the multi-level multi-output minimization and the algorithm used for that. So in the next lecture we will continue with this function maybe in next one or two lecture I will be able to cover the complete the basics needed run through the basics then I will also give certain the current state of the art in this particular field to give you an idea an overview thereafter we will start with the main focus the real digital design showing the example how to go about designing and the concept I hope you enjoyed this session please go back and work on the basics I have covered those have not learned the basics please go back to the reference book learn the first few chapters covering the combinational sequential logic learn bit about microprocessor learn bit about the computer architecture so that when we move ahead you are in sync I wish you all the best and thank you.