 Hello everyone. This is Vishwanath Chavan, Assistant Professor, Department of Computer Science and Engineering, Walton Institute of Technology, Sulapur. Now I am here to explain the topic A257 which is DMA Controller. At the end of this session the students will be able to describe the architecture of A257 DMA Controller. And they will be able to explain pin diagram of A257 DMA Controller. DMA strands direct memory access. It allows the device to transfer the data directly to or from memory without any interference of the CPU. Now using DMA controller the device requests the CPU to hold its data address and control buses so that the device is free to have interaction with memory to transfer the data. It is designed by Intel. Following is the sequence of operations performed by DMA when any device has to send the data between device and memory. Normally the device has to send a request which is called DMA request to DMA controller. DMA controller sends hold request to the CPU and waits for CPU to assert HLDA. Then the microprocessor enters into tri-states all the data address and control buses. The CPU leaves the control over bus and decays the hold request through HLDA signal. Now the CPU is in hold state and the DMA controller has to manage the operations over buses between CPU, memory and IO devices. Here we have a list of features of A257. It is having four channels which can be used over four IO devices. Each channel is having a 16-bit address register and 14-bit counter register and each channel is having a capacity to transfer data up to 64 kb. Each channel can be programmed independently. Then each channel can perform read transfer, write transfer and verify transfer operations. It generates mark signal to the peripheral device that 128 bytes have been transferred. It requires a single phase clock cycle. The frequency range varies from 250 Hz to 3 MHz. It operates in two modes that is master mode and slave mode. Let us see the architecture of A257. It is having four channels like CH0, 16-bit address register, 14-bit counter register. Similarly, channel 1, channel 2, channel 4. These are the four channels. Then there is one priority resolver. There is one unit called data bus buffer and read write logic. Then control logic and mode set register. These are the different components and they are connected in this way. This is the internal bus like this. Now the external IO devices they are communicating through different channels. These four different channels. Request is assigned. The priority resolver solves their request based on priority which is assigned. Then it sends the signal to the control logic and mode set register. Then it generates the appropriate signal for its respective channels, which one should be in action. Meanwhile, read write logic sends the control signals for reading and writing. And this is data bus buffer. Temporarily it is storing the data. Priority resolver solves their request based on priority which is assigned. Then it sends the signal to the control logic and mode set register. This is the IC. Now think about this question and pause the video and write down the answer. The question is DMA controller has how many channels? I hope you answer. It has four channels. The next question is DMA has how many bit address and counter register. It has 16 bit address and 14 bit counter register. This is the pin description of A257. It is for tip in IC. Like IOR bar, IOW bar, memory read write, mark, ready, old acknowledgement, ADSTB, AEN, HRQ, CS bar, clock, reset, acknowledgement, DSEK2 bar, 3 bar, DRQ3 request, then DRQ2, DRQ1, DRQ0, ground, pin number 31 VCC, data, data lines, acknowledgement line, and address line, terminal count, address line, bar, memory read write, mark, ready, old acknowledgement, ADSTB, AEN, HRQ, CS bar, clock, reset. So like this a total 40 pins. Now we'll focus about all these pins DRQ, so DMA request, DRQ0 to DRQ3, 0, 1, 2, 3. Since there are four channels, four requests through those channels are rising. Next we are having acknowledgement, their respective acknowledgement like DSEK0, DSEK1, DSEK2, DSEK3. Next data lines, D0 to DA, total it is 8 bit data line. We're having IOW read input, output read, the next pin which is IOW write input, output write, then clock, then address lines A0 to A3, CS stands chip select, selection of A2, 5, 7. Next address lines A4 to A7, then there is a ready pin which confirms whether the device is ready or not, then HRQ, hold request signal which is coming from output device, then it's acknowledgement which is HLDA, then MEMR, memory read, for reading the memory, MEMW for writing memory write operations, EDST which convert higher byte memory address to the DMA control latch, EN which is going to disable address and data bus, then MAR, it indicates 128 bytes are covered or transferred, VCC which is about power supply, this is the textbook, thank you.