 In VLSI design we normally worry about logic stages, however as technologies have been scaled down the role of interconnects has become increasingly important. In this module we shall see what is the impact of interconnects on modern VLSI design and what are the techniques that we use to mitigate the effects of large interconnect delay. To put the whole topic in perspective let us quickly revise the ideas of device scaling. To increase packing density we would like to reduce the size of transistors and passive components. In order to decrease the lateral sizes we have to reduce the vertical sizes as well. If dimensions are scaled down voltages must also be reduced to avoid breakdown. This is the usual constant field scaling. So what price do we have to pay to get denser more complex circuits? Here is a very simple first order in fact zero order model for an MOS transistor and we know that in this model for gate source voltages less than the threshold voltage the current is zero. As the gate voltage exceeds threshold voltage but before the drain source voltage becomes equal to VGS minus VT or the saturation voltage the current is given by this equation which is the linear regime and it is VGS minus VT into VDS minus half VDS squared. Once VDS exceeds this saturation voltage then it is given by K by 2 VGS minus VT whole square. In digital circuitry the on current of transistor is typically given by this equation. However whatever the regime please notice that the current is this K factor multiplied by a term which is square in voltages. The details of this may be unimportant because when we scale voltages we scale all voltages and essentially what it means is that because this has dimensions of V squared and if all voltages are scaled then this term will scale as V squared. Let us now look at the impact of what happens as we scale down all dimensions and voltages. We are going to divide all these quantities by some factor S which is the scaling factor and S is supposed to be greater than 1 that means things will become smaller. It is clear that the device area which is a product of the width and the length both the width and the length will be scaled down by the factor S bringing down the area by S squared. The term C ox which occurs in the transistor equation is actually the capacitance per unit area and it is given by epsilon ox divided by T ox which is a constant divided by S. So the overall value of C ox goes up by the factor S. The total capacitance is inclusive of the area and the area goes down by S squared as we have seen here whereas the thickness of various things thin oxide thick oxide goes down by factor S and as a result the overall value of the total capacitance goes down by the factor S. All voltages will be scaled down as we had said earlier by this factor S. So let us look at the current the drain current. Drain current is given by this expression which is mu C ox W by L and a term which is of the order of V squared. Mu is a material constant we have already seen that C ox goes up as S. W by L being a ratio remains constant with scaling and because the voltages are scaled down by S this term will scale down by S squared. Therefore overall the current will also go down by S. So therefore the voltages scale down by S and so does the current. Let us look at the slew rate slew rate is the rate of change of voltage at the output and it is given roughly by I divided by C. We have seen that I goes down by S and C also goes down by S we had seen it here. So overall the slew rate remains constant the total delay is the total amount of voltage change that we require in going from 0 to 1 or 1 to 0 divided by the slew rate. Now the total voltage is scaled down the slew rate remains the same and therefore the total delay will go down by a factor S. This is in fact good news that means not only do we get smaller transistors we get faster transistors. The static power which is the product of voltage and current goes down by the factor S squared and the dynamic power which is C times V squared times frequency notice that because the delay has gone down by S we will now operate our transistors at a frequency which is higher by S. So the total capacitance goes down by S this we had seen here V squared goes down by S squared and the frequency goes up by S because the delays have gone down by S. So we are going to operate our transistor at higher frequencies. Even at this enhanced frequency you can see that the dynamic power also scales down by S squared. Therefore total power which is the sum of these two will also scale by S squared. A measure of the goodness of a technology is the power delay product and because the delay goes down by S and power goes down by S squared it in fact improves by a very considerable factor which is S cube. We must not get carried away by the improvements in speed and power alone. We need to worry about the power density. Power density determines the overall temperature at which this device will operate and fortunately they both reduce by the same area. The power goes down by S squared so does the area and as a result the power density remains constant. So let us summarize what is the effect of all of this when we scale down the technology. The packing density improves it goes up by S squared because the area of each transistor is smaller. The speed improves because the delay goes down by S and power consumption improves because it goes down by S squared. All of these are extremely welcome changes and it is indeed the motivation for the continual scaling down of technologies that we have seen over the last so many decades. However, all these formulae were derived from the equations of active circuits coming from transistor characteristics and capacitances. What about passive components? Also we must be aware that as the voltages reduce the signal to noise ratio will also go down because the noise remains the same and the signal is proportional to the voltages that we have. Let us do a very simple order of magnitude computation for interconnect delay. What I show here is a line of length L of width W and with a metal whose thickness is T m. This metal line is running over an insulator whose thickness is T i and we assume that there is a ground plane below. The resistance of this line is the resistivity times the length divided by the area of cross section which is W multiplied by the thickness of the metal. On the other hand the capacitance is given by the parallel plate capacitance of this and that is given by the dielectric constant multiplied by the area which is W times L divided by the thickness of the insulator now which is T i. Therefore, the charge time it is not equal but roughly equal of the order of R C time constant and if we multiply these two things together what we get is rho epsilon L squared divided by T m T i. The factor W cancels that means to first order delay is in fact independent of W and that is understandable. If you increase W the resistance will go down because now you have a wider line but the capacitance will increase in the same ratio you because of the same reason that the W is larger. Unfortunately, W is the only parameter that the circuit designer could decide L is fixed by the distance between the points to be connected you cannot change that rho and epsilon are material properties and T m and T i are decided by the technology they are not in the hands of the designer. The only factor which could have been controlled by the VLSI designer is in fact how wider line you will lay out and as we see that to first order that does not matter. In fact, this is a very simple model in reality if you take the source resistances and various things into account the width does matter a little bit. So, the VLSI designer has to be aware of what width to use but by enlarge it is a low order dependence on W. On the other hand the dependence on L is square that means if you double the length of a wire the delay will not just double it becomes 4 times and that is very disappointing that means the delay of a long wire will in fact increase very fast in it. Now, let us look at the statistics of the kind of wires that we normally have on an integrated circuit this is just a notional diagram essentially you have a very large number of wire lengths which are distributed around some peak here. This is a histogram the x axis shows the normalized wire length the wire length is normalized to the diagonal of the die size. Therefore, it will essentially spread from a range which is roughly 0 to 1 we will hardly have wires which are much longer than the diagonal of the entire die. The y axis plots the number of wires which are of this length. It turns out that a very large number of wires are distributed around this somewhat small length and these represent the local interconnects. When you make flip flops when you take signals from one stage to the immediate next one this is roughly the span of lengths for which there will be wires. However, in addition to that there are these wires. These wires are the global interconnects these are the supply wires the clock distribution the buses the global signals the reset signal all such signals which have to run over the entire chip. And there are a few of these because a bus typically may be very wide it may have 8 16 32 or these days 128 wires and these buses will be of very long normalized length. While we scale the technology it turns out that these lengths will scale down if the devices are smaller the interconnects which are immediate will be smaller. On the other hand these global interconnects are scaled not by the transistor size but by the die size. So, the interconnect delay which we had derived earlier as rho epsilon divided by T m t i T i into L squared we put this as a constant as a L squared and it scales as L squared. For local interconnects as we change the technology L scales the same way as T m times T i. So, the delay is invariant if we scale down L by the factor s and scale down T m and T i by the same factor s both the numerator and the denominator will be divided by s squared. So, the delay is invariant this is not very good our active circuitry is becoming faster but our interconnects remain the same speed even as we scale the technology. However, this is still manageable what is alarming is in fact the global interconnect. In case of global interconnects L actually goes up with die size while T m and T i scale down as a result even in a modern scale down technology the global interconnect delay will show a very sharp increase and this is indeed alarming our electronics has become much faster our power has gone down but at the same time the delay in global interconnects goes up very very sharply indeed and this is one of the major problems of modern VLSI design. To summarize the global interconnect delay can be the determining factor for the speed of an integrated system the L square dependence of interconnect delay is a source of particular concern the problem can be somewhat mitigated by buffer insertion in long wires this is the technique that we will see and in order to do this what we do is that all right if the delay is increasing super linearly that means if the length becomes double the delay becomes four times then let us not have very long wires let us divide the wire into short segments and let us buffer the signal after each short segment. So, we define some critical wire length and when a wire segment exceeds this length we insert a buffer. So, here is a model of this notice that this is not multiple segments this is just one segment but we model it as a distributed RC and this entire thing is the segment length which we denote L prime here the delay of even this multi-segment length will be proportional to L prime squared and next we put a buffer here we assume that the delay of the buffer is stopped. So, notice that while we are buffering the signal we are incurring the delay introduced by this buffer. Let us assume that this segment length of the wire is L prime in that case this segment delay of this wire which is which constitutes just one segment of the wire of the long wire is a L prime squared where L prime is the length of the segment and the buffer delay is tau. So, therefore, the total delay of one stage of this will be a L prime squared plus tau and for n segments there will be n minus 1 buffers and L will be n times L prime. So, the total delay which I represent with this capital delta that is n times a L prime squared plus n minus 1 into tau. Now, n is nothing but L by L prime we have divided the length L into n segments of length L prime therefore, n can be put down in terms of L and L prime also. So, we substitute for n this L by L prime and finally, we get for delay as this a L times L prime plus L divided by L prime minus 1 into tau. Now, we want to know what is the optimum segment length to minimize this overall delay after all if we have very small segments then we will have a large number of them the total delay introduced by the buffer will then dominate the delay. On the other hand if we have segments which are too long then the L square dependence will make the wire delay too much and therefore, there is an optimization an optimal length L prime. To find this optimal length we put the derivative of this total delay term with respect to L prime 0 for optimization and when you take the derivative of this what you get is a L from the first term and minus L by L prime squared from this term times of course, tau this is a constant and will give you 0 on derivation. What this means is that a L prime squared should be equal to tau a L prime squared is in fact, just the wire delay of the segment. So, therefore, we have a very simple formula that L prime should be so, chosen that the wire segment delay is equal to the buffer delay. Now, the total delay will be proportional to n and therefore, is linear in L this segment delay is now 2 tau twice the delay suffered by the wire, but overall the total delay is linear in L. The multiplier this linear proportionality constant has doubled, but it remains linear and therefore, over longer wire lengths we will gain a lot if we use this trick. As a result buffer insertion has in fact, become the dominant technique for laying out long wires in modern technologies. These buffers are typically wide buffers. So, the tau is small and then unfortunately what it means is that they consume power and they consume silicon area. However, in current technologies that is the only way to go otherwise global delays will pull down the performance of your system by a very large amount. So, we are these are the problems with buffer insertion. Let us look at this buffer consume power and silicon area. In a typical design what we do is we do floor planning and lay out the unit cells of our design first and then put in the interconnects. Now, while putting down these interconnects we roll this wire out and when the wire length reaches L prime we need to put in a buffer. However, it is quite possible that when we reach the length L prime on this wire we find that there is active circuitry underneath on silicon and there is no room to put in a buffer. Now, what do we do? We either live with buffer insertion at non-optimal wire length that means we use an L prime which is too small or too long at this point because we cannot put on put down a buffer at this length or we insist that our interconnect will be optimal and whatever is obstructing putting a buffer here will be moved out and therefore, the existing cells must be relayed out and we must remodify the layout. This leads to a cycle. We keep on adjusting our floor plan that changes the wire delays that changes the wire lengths and finally, it becomes very difficult to get closure of our design. So, this is a big problem of modern VLSI design with global interconnects. Global interconnects often include data buses and this is yet another problem that means these data buses need to be bidirectional. Now, as long as we just had a wire there is no problem the wire can be bidirectional. However, as soon as we put in a buffer this defines a direction because the buffer has an input and an output. So, for example, suppose you have a bus connecting a processor and a cache or on chip memory. Now, the buffer insertion will fix the direction of data flow. Unfortunately, the data flow is in both direction. You need to read from the memory as well as write to it. So, what do you do? Either you have redundant buses one for reading and one for writing that means your cost both in terms of area and power and complexity goes up by a factor of 2 or you replace the buffer with bidirectional transceivers. However, this is not such an easy solution. The transceiver needs a control signal which will determine in which direction it conveys the data. And where does this control signal come from? These transceivers are all along the wire and therefore, this control signal must be run along with the bus that means now we must run more wires in the bus. Also, this control signal must not be slower than the data. In fact, it should be faster than the data so that the direction of the transceiver is set before the data arrives. That means this wire must also be buffered. If it is unidirectional, there is no problem. But if it is also bidirectional, we have major headaches here because then we need to decide how to set the direction of the buffers which convey the control signal. So, that means bidirectional buffer inserted wires are extremely complicated to design. They are expensive both in terms of area, silicon area certainly. We have not doubled the wire length by putting transceivers, but the silicon area will indeed double and we must put in additional wires which will carry the control signal for turning around the direction of these transceivers. Notice that buses can at times be very wide and that means each buffer of the control signal must drive say 16, 32, 64 or 128 line buffers in parallel and this is indeed at all order. And you pay by having a slower bus and one which consumes a lot of area as well as power. So, buffer insertion is unfortunately the only solution available, but practically it comes with lots of disadvantages. Modern VLSI design research has therefore concentrated on how to improve the performance of the interconnect and this constitutes what we call interconnect aware design. One of the solutions is in fact to change our design style and lay down the wires first. So, this is like designing the roads in a city first and then use of the area for active circuitry. The active circuitry area left must be adequate to accommodate exactly the practical silicon circuits that you will put there. If it is too large the area between the interconnects then you will waste silicon area. If it is too small you would not be able to fit in the functional circuits that you want to put in after you have laid down this wires already. See even that solution is not optimal, is not without its problems. The other solution is to come up with ways of conveying data which is different from what is used right now and we shall now look at some of these techniques. There are other problems as well which are common. There is a serious signal integrity problem because of electrostatic coupling between long wires. Inter-signal interference, capacitive coupling of signals going down one wire, coupling to a wire which is adjacent to it. They can lead to unpredictable delay variations. The delay variations are data dependent and cannot be anticipated at the time of design. To avoid this we might use grounded shielding wires between wires but then that leads to extra capacitance and CV squared F power losses not to speak of area. So there are solutions but these solutions are generally expensive. Timing closure we have already discussed that if global interconnects are placed after active circuit design then we lead to a closure problem that means you change the layout that changes wire lengths that changes delays and then you must redesign the circuits and so on round and round till you meet your timing specification. To get around this problem we come up with a new suggestion. We say why signal zeros and ones by voltages? Why should we have that a low voltage is zero and a high voltage is one? Why can't we signal a zero or one by the presence or absence of a current? The current rise time is limited by inductance rather than capacitance and typically inductive effects are much smaller than capacitive effects. Inductive effects are becoming important now with scaling down but still the inductive effects are much smaller than the capacitive effects. After all the value of epsilon is close to four for most of the materials average this is the silicon dioxide dielectric constant. So epsilon is of the order of four but practically none of the materials that we use are magnetic and therefore the value of mu is of the order of one and therefore the inductive effects tend to be somewhat smaller than the capacitive effects. Signal voltage swings are limited by scale down supply voltages. Remember we got higher performance by scaling down voltages and therefore the voltage swings are limited. On the other hand the current swings are not limited we can still drive a transistor much harder and take much larger current from it. So therefore we are not limited in the headroom for signal to noise ratio if we signal using current rather than voltage. Indeed so much so that we can use multiple current values to send more than one bit down the same wire that means the amount of current could be 0 units 1 unit 2 units or 3 and that would represent a 2 bit information being carried down the same wire. So therefore the current mode signaling appears very promising indeed and indeed this is some work that many researchers in the world have been doing and this includes our group here at IIT Bombay. So let us see how we use this current mode signaling. The suggestion is the following if you hold the voltage on the interconnect nearly constant in fact we will not be able to do it. So we will later see that we will use low swing signaling but just to argue the point let us say that the voltage on the interconnect is nearly constant that means the dynamic power will be negligible in fact if we hold it exactly constant then it then the dynamic power will be 0. Correspondingly the latency will be much lower. We also have the option of using multiple current levels to transmit multiple bits simultaneously. This can give higher throughput and lower interconnect area because there are fewer wires for carrying the same amount of information. Thus we have the possibility for improving latency throughput and power simultaneously. Normally we tend to trade off one against the other. However this is easier said than done. How are you going to change the current without changing the voltage because Ohm's law connects the two. In fact if we say that delta V tends to 0 while delta I is non-zero that means the input resistance at the receiver should approach 0 otherwise as you change the current across this input impedance a voltage will develop across this which will change in proportion to this current. Therefore in current mode what we do is to terminate the line with a low resistance rather than using the traditional high input impedance of CMOS design. So let us see what happens when we use this technique. However the digital designers who are used to doing traditional design might panic. However what we are proposing is that we will design the interconnect as a library element. It will be designed using more or less analog techniques. However the digital designers need not panic. As far as their voltage levels are concerned these voltage levels will be standard. They will swing from rail to rail and these will be digital signals. All the overhead of converting this rail to rail signals to a lower voltage and then converting it back to a rail to rail digital signal. The power as well as the delay involved in these operations will in fact be charged to the current mode transmission signal and if in spite of this overhead if it comes out better then indeed it is a very good replacement for the traditional buffer inserted drivers. So let us look at this particular idea. The main problem is how do we get a very low input termination resistance? There are many ideas for these. The simplest of these would only actually put a passive resistor at the end of the line. However there are some smart solutions which have been proposed for this and this is one of them. This is taken from a paper by Chunky Kim and other offers and it was originally designed not for interconnects but for readout circuits for low resistance infrared detectors. This paper originally appeared in 1900 and 99. The reference is given here. This configuration by the way is known as a beta multiplier. This is a slight modification of a beta multiplier. In a beta multiplier these two transistors will have different geometries and the larger of these will have a resistor in this arm. However in this case we have them matched and there is no resistor. You can think of it as a p-type current mirror driving an n-type current mirror below. The circuit above the half looks like a p-type current mirror. The circuit below the half looks like an n-type current mirror. So we connect a p-type current mirror to an n-type current mirror and they essentially sustain a value of current within each other. The reference current of this is in fact the current output of the p-type current mirror and this is echoed back by this transistor and becomes the reference current of the other. So as a result if the multiplying factor is truly 1 then this current will in fact be sustained. We can actually look at the input impedance of this arrangement. We propose to connect this point marked V to the long interconnect line and therefore the input impedance is the impedance seen here to gram. To calculate that we compute the ratio of the small signal fluctuation V here to the small signal fluctuation I. This can be easily analyzed. For example I1 is gmn1 that is the gm of this n-channel transistors times V1 where V1 is the AC or the fluctuating voltage across this transistor. Notice that this is diode connected and therefore the current is gm times V1 where V1 is the voltage at the drain as well as at the gate. But if you look at the p-channel transistor then the same current I which is in series is given by gm of this transistor gm of p1 times the difference of fluctuation at this point and this point. That is the drain that is the gate source voltage of this. So therefore this current I1 is also gm p1 times V minus V2. V is the fluctuation here, V2 is the fluctuation here and therefore this is given by this. Similarly these two transistors are in series and therefore convey the same current and this current I2 is given by gmn2 times V1. Look at the n-channel transistor, the gate fluctuation is V1. This is connected diode style here. Therefore the fluctuation here is V1 and therefore the current through this transistor the fluctuation in current through this transistor is given by I2 equal to gmn2 times V1. Remember V1 is a small signal fluctuation in voltage not the DC voltage and this is equal to minus gm p2 V2 because this is the p-channel transistor. V2 is the fluctuation here. The current here, current fluctuation here will have opposite sign to V2 here. In increasing voltage here this being a p-channel transistor will decrease the current through this. Now because this is a current mirror these two currents are equal and we can solve these equations to get eventually the input impedance of this. So by eliminating the unknown voltages here which are which is V1 here, we finally get I1 in terms of V and eliminate V1, V2 in terms of VLO. So I1 is gm p1 V plus this ratio of ratios gmn2 by gmn1 divided by gm p2 divided by gm p1 times I1. If we collect all terms in I1 then we can get the input impedance and finally the input impedance will come out as 1 minus gamma divided by gm p1. The net impact of this is that by bringing gamma very close to 1 we can bring the input impedance of this circuit very close to 0. In fact we can put the input impedance to any desired value by setting the value of gamma appropriately and gamma is nothing but gmn2 divided by gmn1. The whole thing divided by gm p2 divided by gm p1. In short it is the ratio of the mirror ratio here, mirror ratio in the n channel transistor divided by the mirror ratio of the p channel transistor. Now it turns out that this is a very robust quantity. If you derive the value of gm it is given by root 2k times id if the transistors are assumed to be saturated and when you substitute for this the value of gamma actually turns out to be this number which is dependent only on geometry. Notice that this is independent transistor parameters and therefore it will be independent of process variations. It is independent of k and mobility and therefore it will be independent of temperatures neither k nor vt nor any other transistor parameter appears in the expression for gamma. As a result it is set statically once and for all by the geometries and therefore it can be defined very very robustly. Thus we choose an input impedance that we need, set the appropriate value of gamma and now we can make a receiver which has the desired input impedance which can go all the way down to 0. And once we have a low input impedance essentially a large current fluctuation will lead to a very small voltage fluctuation on the line and then we will reap the consequent advantages. This current which then comes to the beta multiplier as we had seen can be further mirrored and then we can detect this current by converting it to voltage or by current comparators. Indeed low swing signaling can also be used for voltage mode. So, we should be careful when comparing the advantages of low swing by itself and low swing voltage versus load swing current. What is the difference? Indeed I can design buffers in which the in which this voltage swing is not rail to rail. These are like little analog circuits with gain of the order of 1 and now I can have a driver where this swing is much smaller than VDD. In that case I shall still reap the benefits of reducing the dynamic power. But what I sense at this end is then a voltage and this buffer will then need to restore this small signal voltage here to a full rail to rail signal here. In case of current mode everything is exactly the same. I drive it, I get my full swing input and I drive it by a low swing driver. I have the same passive line which is RC but I now terminated in a load resistance which is small. Because of this termination the swing at this particular point will continue to remain low but also it will bring down the RC time constant of this entire line. As a result the bandwidth of this line will be higher and I will be able to use much higher data rates on this line if I am using current mode. So it is the combination of this a low terminating resistance and low swing signaling that the current mode of signaling shows extreme promise and indeed some of the best results in terms of power and delay for standard technologies not going to optical and so on are shown by technologies which use this trick and this is an upcoming technique which is used widely to signal at low energy cost and at very high speeds. Now we have seen the basic premise of current mode signaling. We would now like to optimize it further. The current mode signaling can be modeled as a low swing driver which drives this distributed RC line and which is then terminated in a low resistance amplifier. This receiver or amplifier takes a low swing voltage at the input and converts it to a full rail to rail traditional digital signal. So notice that in this link the input is a traditional rail to rail digital signal and so is the output. Therefore if we design this link very well once and for all and put it in a library then our overall VLSI design style need not change. On the other hand if this link is faster and consumes much less power then we have an improved VLSI working with us. Actually it turns out that interconnects actually consume between half to three quarters of the total power consumed by a modern large VLSI. So if we reduce the delay and reduce the power we shall have an overall impact on the performance of this circuit. This does not mean that current mode signaling has no disadvantages at all. We must be aware of these and we must know when current mode signaling can in fact be used and this is the list of things that we have to worry about. Notice that because the current is made to flow it will consume static power and this power will be independent of the data rate. That means at low data rates this may not be such a good idea. There is a direct tradeoff between speed and static power. If we have to make this link faster then the static current which flows through this must be increased. There are two tricks which are now suggested for improving this kind of circuitry and they include inductive peaking and dynamic over driving and we shall now look at both of these in turn. Let us look at inductive peaking first and let us first understand the motivation of using inductive peaking. As we have seen on chip interconnects can be modeled as distributed RC which is essentially a low pass filter. That means the problem that we have is that the digital signal provided by our driver is passing through a low pass filter. This low pass filter then has this kind of this kind of roll off at high frequencies. If at the end apart from the terminating resistance I put a small inductor. In that case the voltage developed across this will have a high frequency behavior. Remember the voltage across this inductor the inductive impedance will be omega times l and when I pass a current through this the voltage will be i times omega times l which is linearly proportional to omega higher the frequency higher is this voltage. So essentially by suggesting that you put an inductive termination you are saying that you will counter the low pass nature of this interconnect with the high pass value of this load. So this is the basic premise on which we are making this solution. This is not a new idea and this idea has been used in RF employers RF amplifiers for a long time. The only problem is that putting inductors on chip is not practical. Inductors are large devices and they consume a lot of area and therefore a traditional inductor may not be possible. To understand the problem what we do is first find out what is the amount of inductance that we may put in a practical circuit to expect improvements in device speeds. And then find out if this much of inductance can be generated electronically that means as an active inductor rather than putting a traditional spiral inductor which in fact has a low Q. When we do a static analysis with different values of l inserted not caring how we are going to get this value of l. We notice that enhancement of about 500 megahertz in the 3 dB bandwidth is possible. I would warn you that this x axis is on a logarithmic scale and it turns out so these three curves are with 0 in between and large inductance put here and therefore the cutoff frequency is pushed out and while this looks very marginal on this scale that is because this is a long scale and indeed the 3 dB bandwidth is increased by about 500 megahertz where the actual limit is of the order of a couple of gigahertz. So, this improvement is substantial indeed. In short what this passive analysis tells us is that if we can produce of the order of tens to hundreds of nano Henry's of inductance somehow. In that case the kind of improvement in data speed that we can expect neutralizing the low pass behavior of this inductor can be substantial indeed our next endeavor then will be how to generate an artificial electronically generated inductance which is of this value and we shall look at it in the next lecture. So, just to summarize we have looked at the scaling behavior of interconnects. We notice with considerable alarm that the delay of the interconnects goes up as L square and as a result the overall delay will be dominated in fact by the delay of long interconnects. Short interconnects the delay remains more or less constant and while in the long term it may be of concern in short term perhaps we can live with it. But long wires like clock distribution like buses very long wire which carry high speed signals are a great concern. The traditional solution for that problem has been buffer insertion. We have looked at the optimization problem of that buffer insertion and we came to the conclusion that it is worthwhile to divide a long wire into short wire segments and the optimum segment length is such that the segment wire delay is equal to the buffer delay. However, this solution had lots of drawbacks and we have been looking at low swing current mode signaling as a replacement for that buffer insertion method and we have looked at one possible way in which we can counter the low pass behavior of this long interconnect wire by terminating it into a high pass termination which requires inductors of the order of 10s to 100s of nano henries. We shall see in the next lecture how we can generate these 10s to 100s of nano henries and what are the other ways of countering the low pass behavior of this wire this wire model this is where we conclude this particular lecture.