 Now, the logical effort extends to multiple networks also. Before we actually calculate the net delay, let us calculate the path, part delays. How do I calculate part delays is from this. This is a, I mean this example is not unique or something. It just to have a chain of 4 gates. Initially, the inverter is here and last is also an inverter. In between there is a XOR gate and then and 2 input like R and NAND and NOR gates. So, I now start for path from here to here. Let us say C input has a unit of 10 and C out has a unit of 20. So, I say for this first gate G 1 is inverter. So, G 1 is 1 H 1. Now, let us say this has an in size we do not know. Actually, what we are doing now? We want to find how much delay it will take for me to go from signal from this input to charge this output load and therefore, to minimize what should be the sizes of these NAND and OR gates. That is the capacitance they will give me which will optimize my delay for input to output. This is what I am looking for. So, I first find the delay itself as a function. So, I say fine G 1 is 1. The H 1 that is the output capacitance divided by input, input capacitance. Let us say it has a size of X. So, it is X by 10. Similarly, for G 2 since it is a NOR gate 2 input 5 by 3 H 2 which is Y by X because this also I do not know. So, Y by X. So, H 2 is Y by X. For this, let us say this size buffer also I do not know what it is to drive. So, I say it is a Z. It may not be minimum size. It is a buffer stage. So, I do not know what is the size here. So, I say it is Z. So, G 3 for NAND gate is 4 by 3. 2 input NAND gate is 4 by 3 and H 3 is Z by Y. And for the last this gate G 4 of course is 1 because an inverter H 4 is 20 divided by Z. Output to input, output to input ratio I had taken. So, now I say the. Excuse me. The last for the last buffer why did you keep it at Z? Why currently you have taken it as 10 as what you have taken for the input stage? I do not know because I want to minimize here. If I had to increase the size I may, I need not have essentially the same final buffer because many times this is what we are doing. The optimization of X, Y, Z sizing will give you the minimum delay. So, if I fix Z I have only 2 optimizing then. So, I will keep that as well. As far as I am concerned I can put any size now. I am at the design stage. No one is fabricating anywhere right now. So, I can keep that as a variable. As many variables you will keep that much control you have, is not it? So, that is the idea. You are right. If you reduce that fixed value then you have only value but that may not be minimum because for that value of Z you have chosen that minimal. That may save your time a bit. I am not denying but that time may not be that enough for offsetting the actual delay reduction. So, I keep it as a free flow. Yeah. So, under the same assumption that output 20 could be because the load is fixed. No, but load is fixed. Load will be given to you. Correct, correct. The load is fixed. Load cannot be changed. But again that input 10 also could have been fixed. Yeah, normally input is also fixed. What we do is input is driven from the last gate somewhere from there and you will actually buffer. Like let us say I have an input A and I want to have A and A bar which I will show you later. I may create both complements and true but that input circuit may not be able to drive the full lines. So, I may actually put a buffer stage and normally some input buffers are used for drive the longer lengths. I may start with any value whichever is given by the last circuit to me. Which right now I assume 10. 10 is not very some a sank or sank. 10 is chosen number. You can put some other number and recalculate that number. It does not matter for me. The idea is given an input output and if there is delays in between the path what sizing I should do. That is the idea. So, I say path logical effort is the product of all logical effort along the path. Multiply of all g's. So, g1, g2, g3, g4. The path electrical effort is the output C divided by input C. However, I may now give as sometimes this may work. Sometimes it does not and therefore I wrote specifically this line. Do not define h as product of h1, h2, h3, h4. In this case it may work. In this case it is working z by x, x by y. It will cancel and finally you will get only C out by C in. So, this worked very well. So, you thought h is also multiplied but in real life we will show an example which is called blanching problems. This may not be true. So, in general do not use product of h1, h2, h3, h4, hn to calculate your h. You only take the output and take the input, take the ratio of the two. In between we will see what h actually went through. Maybe it may still follow h1, h2, h3, h4 but that is logically it will automatically come. If it does not, I am not bothered then. If I define by anything like this then I will be bothered. So, normally I never define h, the total electrical effort by stage wise I say output by input in block I want to. But in this specific case if you do that nothing well will go wrong because it will find that you can see C out by z. The next is z by y. So, z cancels. Next is y by x. So, y cancels. So, x cancels. So, finally you will get C out by z. In this specific case it was true. But an example may be shown where this may not be true. So, as a general rule I will just not to put h1, h2, h3 as this as the product to get your h. However, as I say in this specific case it was okay. Then the path effort I define, path effort is from input to output. I say defined as g into h. That is what we define to start with. So, the path effort is called f, capital F which is okay. Small f is called g into h. Small f is called stage effort. Each stage has an effort which is g into h. So, you can have now g h into g h into g h, g1, h1, g2, h2, g3, h3 and one of them okay. So, we say it is product of all f's each stage effort. So, the definition is can we write therefore always f equal to g h? That is what the whole question was okay. Let us see why okay. Maybe this is not a good example. At times yes, at times no. If the parasitic delays are too small maybe this is not absurd. But if the parasitic delays are not this because each block may not have same parasitic delays in your calculation of this you actually forgot about p. So, never put always but in many cases it may okay. So, that is the as I said these are back of calculation. So, you do not think that I want 2.367 nanosecond. I am not interested. It is 2.5 nanosecond lower or more okay. So, as long as these values I get I am as I say I am going to finally do final simulations. But I want to know initial guesses which should be close to what real values will give me for the minimum delay okay. This is the trick okay. So, we can now compute the delay of multi-stage network by we say the path effort delay is sigma of f i path parasitic delays all p sum together and the path delay is df plus p now that p has to be there. Now maybe we can see if I have n stage of such blocks n of them okay. So, what is the f1 f2 will be g1 h1 g2 h2 g3 h3 g4 h4 g5 product of all of them that I call let us say I would like to get some relationship. I know h is h1 what is h1 c out by c1 at that stage h2 is correspondingly. So, if I now say I want to optimize a delay. So, what I am going to say that as long as each stage delay is equal I will get optimal delay. So, what I am really going to do is I want to find d by h1 I want to find the net delay with reference to say first electrical effort and I can also say h1 into h2 is h assuming right now no branching going on. So, any product of h1 and let us say only 2 stage things I am using. So, h1 into h2 is h. So, I can say h2 is h upon h1 okay. Then I say for first thing it is g1 h1 plus p1 or that is a same the other will be g2 h2 plus p2 with the net delay d. One question sir. Yes. So, you said that this thing if you keep that h1 more or less same throughout each of the stage. I never said h I said gh. Oh gh okay. I never said h okay that is what I want to prove this point. So, I know now this d okay I know this d h of course I know because I know c out to c in the ratio. So, h is known to me. So, I replace this h2 by g2 h upon h1 and right now for the simplicity I assume both them same p but you can always use others. This is the net delay path delay from one to the other and then I differentiate this d with reference to one stage effort electrical effort and equate it to 0 and if I equate it to 0 I then can get the value of h1 okay. That h1 if I substitute here I get the value of h2 since I know the two capacitance I know in between capacitances also by this technique but when I do this I get an assumption that g1 h1 is equal to g2 h2 and I read d by gh1 equal to 0 the condition I am getting to satisfy this is g1 h1 is g2 h2. So, each stage delay if it is identical then I will get always minimum delays okay. This assumption again is p is same if not there is another calculation but can be done okay the idea is this. If I use this kind of logic which I have not shown here then I can say for any stage f any stage delay f g into h is called one single stage delay f and since there are n stages. So, if I f is equal to gh di is a ith1 not g1 but ith1. So, for each stage we are say delay and remember f is the g1 h1 just n times that if gnh are same then gh to the power n gh is f. So, f in I must tell you what I am saying each gh is f. So, gh to the power n is actual f okay if there is a equal delay of n stages gh into gh into gh just gh to the power n is the net f or gh is f to the power 1 by n okay. So, we say upper okay. So, we say per stage delay is f to the power 1 by n if n stages are being used okay. Therefore, the net minimum delay is if there is n stages this is per stage. So, f to the power 1 by n is for one stage if there are n stages n into f to the power 1 by n is this plus the net parasitic delay which is p1 p2 p3 sum of all of them okay. This is a key result of logical effort is that clear this is the key result because what we are now said if there are n stages and as long as you maintain gh same for most of them then the delay can be minimal any number of stages okay that is exactly the trick. So, obviously if you are using NAND gate and NOR gate their Gs are different. So, their capacitance should be so adjusted such that stage delay is uniform okay that is exactly what designers do actually. Once I know c in what is h c out just now okay may be h is c out by c in okay. But I also know h 2 and h 1 are the ratio of c out by last one and next one by this. So, if I do this simple calculations or we can say gh is equal to f as we did we can say input capacitance at any node i is equal to output of that into g by f this is h gh is what we are calculated okay. So, this now we have got we know g of a gate we know stage effort for n stages we which we have calculated already from n fn to the power 1 plus p we already evaluated f for minimal delay. So, I know my f I know my gate which I am looking for if I know my capacitance at that output side I can calculate the capacitance for the other side once I get the last input I use that as an output for the next. So, you start from the output side keep going towards the input side and keep evaluating the capacitances and therefore the size capacitance means it is into proportion to w. So, as much capacitance you get proportionately w's you can assign to those gates is that clear. This is essentially what all that we do in all our calculations. Here example let us say input of an AND gate driving first stages say NAND gate to input NAND is c and let us say I am also driving at load which is c okay and many a time people say why are you driving but it is okay in the example I have in between 2 NAND gates which is this is final gate which is drive this is the circuit given arbitrarily chosen not very specific for anything. Now I want to know this I know c this output I know c but I do not know what are the sizes here. So, I want to find for the delay which is minimal for this path path is from here to here I want to see what should be the size of here and what should be size here. So, I say okay I calculate the net logical effort first for the total path okay. So, what is total gate path g is g 0 g 1 g 2. So, I multiply g 0 g 1 g 2 this is all 3 are 2 input NAND gates each has a logical effort of 4 by 3. So, 4 by 3 into 4 by 3 into 4 by 3 which is 64 by 9 or 27 which is 2.37 okay or keep it 64 by 27 it may help because you have to do one-third again. So, maybe you can use directly that okay branching effort okay there is some word which we are yet not introduced for example this input let us say this output can also be driving some other block somewhere right now this is driving only one but let us say this is driven somewhere output another one then there is a branching effort why because not only this capacitance has to be charged but the upper one also or N number of then could need to be charged. So, there is now how much is totally required and how much part of it I am actually going to give for this gate is called the branching effort right now no branching. So, b is 1 okay no path of loads and the electrical effort I repeat do not do h 1 h 2 but see h c out by same c by c which is 1. So, the minimum delay is achievable f is g b h total part delay is g into b into h b of course is 1 in our case right now till I do otherwise so I substitute g equal to 2.37 b 1 and h 1 and since there are 3 stages n is 3 this is 3-stay circuit. So, 3 stages so n is 3 so 1 by 3 into gb h to the power 1 by n f to the power 1 by n plus 3 okay I did not say you but inverter has a delay 1 input inverter has parasitic of 1 2 inputs will have 2 3 inputs have 3 whatever number of inputs of your gate those many parasitics are used okay by value of calculations as a this. So, since it is 2 input so you have 2 p inverters and since there are 3 such gates 6 of that so I get you can see why I did I say you keep it 64 by 27 then this one-third will go immediately and therefore you get total a delay minimum delay achievable for this path is 10 and multiplied by tau which is your absolute delay so now if I want to calculate the capacitances sorry here excuse me sir one doubt I am quite you know knave to chip fabrication but a question is based on here so this way what you achieve is you achieve you know different capacitances for different you know transistors so essentially what you are trying to do is maybe in the same logical path you are going to have you know transistors different widths. So, from a fabrication point of view is it difficult is it optimal not at all as far as fab is concerned they are given you design rules as long as you do not violate any one of them it does not matter fab people are only interested the constraint which they are given you as a design for layouts which they call design rules as long as you do not violate any of their design rules for a given fab whatever foundry you are using you are safe anyway designer need not worry any of course this statement should be taken little pinch of salt for say anyone designing below 32 nanometer process but as of now here I do not think anyone is looking for 32 nanometers till 6545 even rules are not well known 32 20 to 11 probably are not available so I do not know but as of now any design rule given by a fab people you should follow as that means if they say do not separate line less than that do not use any W or any which is less than the number which they specify but you need not you scale all of them correspondingly we are mostly looking for ratios so you can scale things for your ratio okay so I want to calculate now as I said seen here and seen here okay so I say fine I have f minimum which is the per stage delay gate for this dd by dh1 equal to 0 I calculate dbh to the power one third f to the power 1 by n so I calculate same 4 by 3 seen at the last gate should be equal to I just said g of that see out by cement okay so I just 4 by 3 this see whatever is given to you divided by f minimum which is 4 by 3 which turns out to be same see use this see for example this see now here and calculate by same logic in this case it will come same because you are using two input and same but if this gate is different then it may get a different value okay so you got for the middle gate also see this way you can find the input capacitance and therefore the size here another example okay now I have this is a branching over okay here is the case of branch doing big enough I have one I have a this is a 3 stage circuit okay probably you must have done in a logical algebra somewhere or logical switching theory that the number of stages and the size will decide the delay there also we talked about that you know whether you should use 4 input systems or use 2 2 input systems similar gains are actually well understood or taken care in this design okay that is the trick okay so here is a input is coming from here then it is connected to 2 2 input NANDs only one is used here for this I am calculating delay on this path red one okay whereas this node is also driving another NAND gate this node is also driving 2 other NAND gates okay for simplicity right now I mean it is not that I cannot do other things I am assuming that all loads are same for each of them I also assume all 3 NAND gates also are same size okay right now in real life this this number may not be same and this number so we may have to calculate different path lengths and different delays on that but right now for simplicity for calculation purpose I assume that so now I want to find the minimum delay on this red path and for doing this I want to find the size of this size of this which will give me minimum delay so I say okay I have calculate full logical effort for the path which is G okay 4 by 3 4 by 3 4 by 3 so same as 64 by 27 2.37 electrical effort 4.5 and right now I haven't said it but let's say initial input capacitance is 1 by the way whenever not specified you assume 1 okay if CN is not specified it is taken in unit capacitance this is specifically written by book if not specified use 1 okay 4.5 by 1 so H is 4.5 branching effort branching effort is now you calculate the net branching effort you can see here how much actual capacitance this see first gate is driving 2 of them so it is y plus y is the net capacitance whereas actually for yourself how what is the capacitance you need only 1 y so the additional effort is y plus y divided by what actually you are wanting is by y so twice y plus y by 2 into x because that is the value sorry 2 into not similarly from the other part for the this how much will be this it has a branching for this there are 3 now z plus z plus z but you are only using 1 z so the ratio is 3 z by z which is 3 so you have a 2 from here 3 from here so the branching effort is 6 okay so that capital H B is now 6 in earlier cases we only use B as 1 no branch so the net path effort is GBH G is 4 by 3 4 by 3 4 by 3 H is 4.5 H B is 6 so it is 64 1.5 here which will give me 4.5 load output driving at the minimum delay of okay delay of 18 sorry why I am changing okay of course as I say this is still in a unit of absolute not absolute say relative and tau has to be used okay so now one can see given a network okay two things I can do one of course I can choose whether to use NAND gate nor gates I can also change the number of driving gates and driven gates okay architecturally to get same logic as shown you XOR can be of different architectures each gate you can think substitute them here and keep calculating deep on your path whichever among the two or three you get the minimal that is somewhere close to what real value will come start designing on that and you are you will hit the correct results okay that's the idea and people say oh it's taking as much time two hours so we could have done more faster in computers you do but you don't enjoy that you know at least I enjoy what I do that's the difference okay let's take another case let's say the driving is 8C similar the first was see now it is 8C I redo calculations and I say now the minimum delay achieved you can see now if the load increases that was how much this was 10 minimum achievable delay if the capacitance is same at the output was 10 if I do it now with the everything else same but the load is 8 8 times so your actual delay hasn't increased 8 times if you are gone through this minimum delay procedures okay please take it the wire this game was played the game was played because if the load changes drastically it doesn't if you follow me or this logical effort technique you may get the value of scene such that the delay does not increase 8 times if you are simple thinking would have been you have put extra load extra times because c dv by dt c increase it time would be our current is the proportionally should have increased by w you don't have to if you follow the logical effort from 10 I have reached only 14 okay and that's the trick which logical effort people suggested that don't go by this number suddenly load increases you need not worry that the low proportionately such high number of delay will come you can still optimize that delay to a lower value that's what I did here again g1 g2 g3 find g there is no h here which is one sorry no branching h of course is 8 now what was h there one now h is 8 recalculate GBH find out the minimum delay from the formula n f to the power of 1 by n plus p n number of whatever it is find that it is only 14 compared to what it was earlier 10 that's why I keep saying do it because if you do it you have you are now looking at the actual numbers okay okay that's what I said and recalculate what is that once you calculate D for stage effort of f you can calculate see out back calculations and get new seas all that has done is I changed the C values to get minimal delay which is not proportional so this is what I am saying if the load is higher the earliest stages should also get powerful okay I want to drive so what I do normally all inverter people what they do they always increase the next inverter by e times or two times okay 1 2 4 8 this is what all people normally follow buffer stages but that is only for inverters inverter design was known much earlier 70s or 80s or other but here is the case we are not sticking to inverter any logic on any architecture okay I can still calculate the minimum delay out of it and then I will say okay how much he here next is next is and I can go to the input side you input you need not calculate because see out by seeing you have taken one anyway for your simplicity given example calculate actually for the first stage whether you get that scene logically it should you have chosen H see out by seeing you start calculating from back for the first stage also calculate and check for your own sake whether that scene appears it will okay there is nothing but that is that another example here I think it is similar only thing is sizing is changed okay may be we will do that of this if you have different gates no worry all that you have to do is put logical effort correspond to that kind of gate for example in a nor gate logical effort is different from it is 5 by 3 9 gate it is 4 by 3 so the multiplication is now for this case is how much this is 1 g1 or g0 this is 5 by 3 4 by 3 1 so the new path logical effort is 5 by 3 into 4 by 3 which is 20 by 9 there is no branching bees 1 electrical effort is still say output is 20 and see in stance or to calculate capital F which is 40 by 9 f to the power 1 by n is your stage effort f small f min which is 40 by 9 to the power 1 by 4 now remember it is 4 now 4 stages so get 1.45 once I know the stage effort calculation of capacitance 1 by 1 is possible g into see out by f min 1 into 20 1.45 14 then use this as the capacitance here do calculations I get new calculations of x y z so one question sir so the previous example that you showed where you put the load as you know 8c and you work backwards and you found that you know subsequent stages should have 2c 4c and all so if you are not gone through this way and if you had kept like the c in to be same then what could have happened is the last driver would have had the transistor logic much larger much larger and then since it is much larger it will slow it out because the last stage it has to drive much larger load last to last okay so it will not be able to give that much delay smaller delay so it will increase the delay much higher than what you would have thought so that is why we say okay is something like a cardiff L1 should not fight with the big pelvan so cardiff L1 to 2 card to 2 card to 4 kind of thing finally big to big okay that is the idea note that you never size the first gate okay that is what my suggestion to all this gate size is assumed to be fixed is because we are using tiller serum tiller start with unit 1 so we always use that that can be any capacitance but that is treated as unit 1 okay if you are allowed to size this gate you may find the algorithm may have I mean proportionally has to change because that value has to be now taken care ahead right now do not play any game on the first gate size okay this is my this here is small another different this I have one logical simple block I have one inverter driving a four input NAND which is loaded to 8 c capacitance input is 1 so I had two possible options I have one inverter driving this this is an AND gate so I put a NAND gate followed by an inverter okay or instead of four inputs I use two two inputs followed by an OR gate which is logically they are same functions so I have now two options of course these are representative you can have many options in many real cases so if you do some switching algebra or logical analysis you may get more options than one okay so we take two options and find the delay so the first option I have a NAND gate followed by an inverter and I calculate G which is G 0 is 1 G 1 is 4 input but it is a NAND gate which is 6 by 3 okay 4 plus 2 N you have to take N plus 2 by 3 N is 4 so 4 plus 2 by 3 into 1 so logical effort is 2 no branch 1 capital H is 8 by C C 1 8 the path effort is GBH which is 2 into 1 into 8 16 recalculated minimum delay from N F to the power 1 by N plus P this is 3 into 16 to the power 1 3rd plus P inverter plus 4 times because 4 4 inputs 4 P in plus P in so total is 3 into 2.5 into 6 13.5 if I use this now logical effort is this path G 1 G 2 so 1 into 4 by 3 into 5 by 3 20 by 9 no branch H is C out by C in same as 8 path effort is 160 by 9 and is 12.8 which earlier was 14 or 13.5 is 12.8 this particular example did change it but not very drastically so either is okay but in some cases if a larger gates appear you will find this difference may be much larger and therefore you may say whichever is minimal and that is why we keep saying never input larger input gates as far as possible the 4 is the highest number of gate we should use. So here is the catalogue which of course you can see later inverter has a number of inputs 1 and the logical effort is 1 of course inverter will not have more than 1 input that is why it is inverter for NAND gates the formula is N plus 2 by 3 for a nor gate it is 2N plus 1 by 3 this is you can calculate from number of input and you can arrive at this function for a multiplexer it is standard 2 for X star X nor it is 2 input X star 4 3 input 12 4 input 32 then the parasitic delay I already said inverter is P in normally use 1 N input NAND N times P inverter N input nor N times V inverter N way multiplexer is 2N because 2 paths 2N and for 2 input X or it is 4N P inverter so we are done derived that expression there for case if you have seen any a PJ or any logical systems where you are using inputs most of the times you create 2 and complement input at one time okay the idea there is that if I use a and put an inverter to create a bar then a and a bar are not in the same synchronize synchronization because there is a delay on an inverter okay so what you normally will like to do is to equate the 2 delays so we call it in our designs we say non inverting inverters or buffers are used to equalize the delay on the a part cell so that non inverting inverter will have a delay same as inverting inverter and therefore I can equalize the delay so here is that problem which is called fork problem fork means you have one this pass to two of them okay so input may be a and you are creating a a bar okay so here is a problem this is a this is like a branching effort okay you are actually branching one going to two okay a common case of branching is generating true and complement from a signal such circuits are of course called forks for example in a multiplexer on XR circuit I just shown you I may requires from same DD bar xx bar yy bar kind of thing so the lower one is called lower leg upper one is called upper leg and I want to see that the delay on the upper leg or higher leg and lower leg are same that is what ideally I want so you can see the way I did I put a non inverting buffer here and inverting buffer here both have same delays so delay at this and delay at this is same so how do we get this a far consist of two strings of inverter that share a common input so you have a two inverters here and one inverter here this is non inverting and this is inverting but now I must balance the delay in the upper part that is higher level leg so that it is exactly same as lower leg because that is what I am looking for there can be more than two requirement depends on the drive capability you are the load you are driving that means in a polyline is too long erase too long I may require a huge buffer but instead of huge buffer we know buffer is broken into n parts okay so there will be more than one inverters there or one buffer there so you can see from here you can have 2 1 fork 2 3 4 3 4 4 depends on the kind of for requirement of the load so essentially a general fork will have a load here and here and there will be n stages here and n minus 1 or n plus 1 stages on the other side okay the total capacitance at the input is the input capacitance here plus the input capacitance here that is the net capacitance this CN is okay is that okay since net I am driving to so I am having one and then I am branching on that okay so CN is seen a plus CN B okay the total electrical effort is still whatever is C out which is CA plus CB divided by CN no difference okay individual electric efforts can be fine from here here this work path I can find H they may be different so it is CA by CN a CA by CB by CN B that is H okay even if CA is equal to CB let us say these capacitance are same HA HB still may not be same because to equalize the delay these two capacitance will not have the same value I repeat even if this capacitances are same to maintain the delay here and here same these two capacitances will have a different value okay values they may not be same the net H is same the load driving individual is also same even than CN A will not be equal to CN B if delay equalization has to take place okay that is exactly what this branching is all about a forking is all about okay the idea is what I say I know see how a CN is some of CN I will only show one example and stop CN A here and CN B here the first thing I assume since the total capacitance is some of the two which is input I portion one of them has a beta times that value beta is less than 1 and the other is 1 minus beta of the time okay CN B into beta into CN is CN A and 1 minus beta into CN CN is equal to CN B total is still CN A plus CN same as CN okay so that is I assume now that part of the capacitance is above and part of the capacitance is below on that ratio I am calling as beta okay let us say the total capacitance I am driving is 200 for both okay an input initially is 10 and I am using 2 to 1 for 2 below and or 2 upper and 1 lower either way now I assume that CN CBR equal 200 fine total capacitance is 100 on the upper branch 100 on the lower bar net is 200 even that is simple case so we say the branch was one of them input is beta times CN the other is 1 minus beta times CN so I calculate and if I want the delay to be same what do I want delay to be same so I calculate for both stages the delay one has how many stages 2 inverters so 2 stage the other is single stage so take on the right side this is the single stage GH because capacitance is 1 minus beta times CN so ratio of CN out by CN is H G is 1 in this all cases G is 1 because inverters are used that logical effort is one one I am not multiplying this is essentially H okay GH and no branching so B okay so this is GH plus V okay G is 1 so H plus V now for the 2 fought state which is the circuit I am talking this one 2 1 here okay lower one I calculated which is one stage the second stage if I do now 2 n is to 100 by 10 beta to the power half plus 2 times now it is to please take it it was one inverter here here 2 inverters so 2 pn and they must be equal that is what we are looking for equal delays so I can solve this equation which is slightly quadratic in nature not very simple linear equations a non-linear equation to the power half is appearing beta to the power half so it requires some calculations numerically if you solve which I did of course I have solved it by quadratic method only and I find the beta turns out to be 2.6 or 0.258 so don't take as I say all engineers keep telling here you know the other day someone said the leakage current is 0.2456 pico amps 2456 maybe a 7 8 also now can anyone measure at 2 amps or something or this you are talking so why talk numbers which are no relevance in real life okay so same way don't say 0.258 means I will use 0.258 use closest integer or closest decimal number which I use 0.26 using this beta I can calculate now delay I substitute beta there in the upper this I calculate the delay which is equal for upper fork and lower fork and then I know the beta is 10 be seen is based 10 beta capacitance into beta the other is 1 minus beta into CN okay so I calculate CN as 10 times beta is 2.6 10 times 1 minus beta is 7.4 so I have now calculated the size of upper turn inverter first stage second inverter on the lower leg and also I calculated the delay which is 4 in 5 units which is same for both legs that's what we did when you equate it you said it is equal and for that you calculate so please take it I told you example even if the loads are same CA is equal to CB CN A and CN B will not be same if you want equal delay if they are different you may have still have a very different because then you will actually have a different part delays but even if they are equal this issue will be very important okay so the reason why you took them to be unequal is to get the minimum delay this is minimum delay the minimum delay in both the parts yes that formula is always valid GH plus whatever formula F to the power 1 by N that formula is always valid for minimum delay no no no but the formula I used is for minimum delay and F to the power 1 by N equal no no no his point is N need not I mean that need not be minimum delay but any circuit you are using you will prefer to have minimum delay anyway okay so that is one issue which is always true but assuming whatever delay you have the minimum the at least you should have equal delay even if it is not minimal delay the minimum requirement is the delay should be equal no my point was like if I you know put beta equal to 0.5 and I try to do the adjustment in the you know in the subsequent state I can but as I said tiller said the first stage for half matala yeah so never try okay as I said you can scale scale down scale up but then you have to do for all of them every time so the method is keep one constant okay so start from here that value may be anything okay so it is easier okay similarly if you do for 3 to 4 instead of 2 1 I calculate beta turns out to be 0.5 1 3 and I calculate capacitance again for that so so I can do any number there can be more than one fork 1 2 3 so 1 2 3 4 5 any number you can calculate the delays equate the delays and find out how many stages you should go through but again a question I would prefer to keep it as 2 2 2 dash 1 only now why would I yeah I would no no but if that delay you take it if the dad delay is lower than the other one path you must check check you should not only calculate C1 C2 whatever it is but the net delay also you may find out that the 3 to 4 to 4 will give average delay lower than the 2 to 1 form the sizing will be such in a length then it will be lower delay is that clear to you want to minimize the delay on the path as well as see to it that you have equal delays so you may require to do more than one it is not necessarily it will be better of course not every that is what you are seeing at the end what loads you see that will decide how many stages you will have to go through ok so H because it is deciding H on that so you will have to calculate every time any number of says in fact you will sign this goes like this then the other so there is a inflex point where both are equal kind so you may have 2 to 1 or 3 to 4 2 to 3 will have same delay something below you should have only 2 to 1 something above you should have 3 to 4 keep doing like this this is the table I am talking somewhere at 9.6 set electrical effort both are same but if the electrical effort is larger then you must go to 3 to 2 delay 3 to 2 4 if the electrical effort is far higher let's say at 38.7 it is same use lower one but if it is more than 38.7 is your actual this then go for higher size because the H will decide how much delay you are tolerating here is an example instead of inverter you may have gates method is same is that clear so it is not that method is restricting to only fox of inverters size the circuit from minimum delay draw a network buffer non-critical path with minimum size gates estimate the total effort along each path verify the number of stages estimate the branching ratio how much we have compute this is not for this last part this is for total what I say compute the accurate delays in including parasitic effects adjust the second stage to minimize the net delay here is small catch before I quit all this and I say it is symmetric sizing is 2 is 2 1 2 is 2 1 you can have any sizing it is called asymmetric S need not be half S can be lower than half more than that is P may be stronger N may be weaker N may be stronger P may be weaker this is possible and you can still do same analysis as I did here S is that factor which is called the asymmetry factor how much is symmetric to asymmetry I have and I use like for example on this simple gate this is 1 by S this is 1 upon 1 minus S this is gamma gamma times that okay and I recalculate I can recalculate the logical effort for any asymmetric gates as I did so what is the insight in this logical effort it allows to compare alternative circuit topologies that is most important circuits are fastest when effort delay of each stage is same one should select number of stages to make effort close to four part delay is very insensitive to modest deviations and don't go for 2.63 small numbers are which change name back on up because as I believe what process I remember this word I have picked up from him here in his every talk maybe today also must have backup envelope so I stuck me so much in over the years so I started using myself backup envelope more than him it seems so if I want to do something optimization at backup envelope calculation this is the ideal way delay of well-designed path this formula I can derive but the logical effort of a gate increases as the number of input grows this has to be understood is input grows firstly p times that will also grow so first thing worries how much input so try never use more than 3 or 4 inputs complex gate you have seen as larger the complex inputs larger is the delay so don't go more than 4 input in series any time it will be worst case 4 of course is the highest allowed branch circuit should differ by not more than one gate between the 2 if 2 1 3 2 4 3 always do better to use 1 2 or 2 3 Fox instead of 0 1 Fox choosing p to n channel ratios square sizing equal to square root of the ratio which gives equal rise and fall delay beta should be close to 1 okay so that equal rise and fall typically it is found the ratio p to n ratio of 1 and half works for most technologies most technology this is not true for 65 down or 40 even 65 but okay so here is a block diagram of course you will see this is like whatever I said this is exactly what is shown in a computer flow chart kind of thing the procedures you can use it from this start with function scenes see how delay select circuit family static or whatever it is sketch path label each gate with logical effort level wire lengths layers default minimum pitch compute RC delays wire RC delays label nodes with lumped wires and then keep doing my logical effort when the blocks are available to you and minimize optimize it and come back and put the values back okay thank you very much