 So, the next talk is the talk on LibreSilicon, a project that's meant to create a free and open silicon manufacturing process. And our speakers today are Leviathan, Chip Forge, and Andreas Westerwick, creators of LibreSilicon. So, let's give them a warm round of applause and please welcome them. That's what essentially is all this part about, is actually a description of how we, what is waveform means and where we will go with it. And yeah, I give now already over to Hagen, which already starts elaborating on the basic conceptional things. Okay, hello everybody, hope you have a fresh mind, it could be heavy, okay, let's start. What we are, last year, David was involved at the project to looking for free silicon, a way to manufacture his own chips and figured out it's difficult, you need a lot of contracts for that, NDAs, non-disclosure agreements. So he looked around and found a clean room, we had to come in and say, okay, we can rent it. Then he entered a scene on the last congress, a lightning talk, and said, I like to do that. And I wasn't in the auditorium there. But a guy talked to me later, okay, look at this lightning talk, it's very interesting, you already doing chips. So I entered in, seen the talk, recording, and said, nice idea, I will do that too. And now the whole year, we meet us by mumble, just to think of distance, you know, David is located in Hong Kong, the clean room is there, and I worked from Germany. So we exchanged emails, we talked on a mailing list, we built up a small community for that, and we had a first hacker son, just to figure out what we are doing with the tools, which tools are available, how we can use them, are they usable at all or not. And this was in May. And during the process, the group was up, and already two of us get the qualification to enter the clean room. The Hong Kong University is a little bit strict in that. You have to sitting there in the courses, you have to do exams, and if you are fine with the exams, then you get the permission to go in. So Victor, which is on the most left, and David are the both guys, they have the qualification for that, and they manufacture our wafer, which you have seen there. It's a small one, but it's the first stuff we have, right? Okay, the basic points, what we are doing. We are using a quite, let's say, old technology, it's from the 80s. It's one micron meter feature size, it means the gate length of the transistor has one micron. It's not comparable with all the processors you can buy now. It's quite old, it's really stuff from the 80s. But we do it on a new way. We don't use the technology from the 80s. We do it with knowledge and all the experience from newer technology, doing it again and using some steps which are not the common or wasn't common in the 80s. So why one micron? One micron also means that the transistors are very robust against five volts. Five volts was a usual supply voltage in the 80s, 90s, or something like that. Now the supply voltage is going down to less than one volt. But for tinkerer, for hobbyists, for makers, it's a nice value because all the stuff, many of boards are still working with five volts. And we are able to handle this voltage. So we have a twin weld process. Usually in the 80s there was just one weld. Okay, we have to hurry up. We have three metal layers, we have interesting additions, and we are suitable for low tech, ghetto tech I would say. You can use it without sophisticated equipment. We can analog stuff and so on. An analog stuff means you don't need small structures. Okay, our areas where we have to work on first supports us. It's almost done. You have figured out what it works, we're measuring, okay. The next stuff, we need the tools. But the tools are also very old or mostly not usable. We have to deal with that stuff. We have to rethink the tooling for that. And we need standard cells, that's my task. Okay, so a couple of words about standard cells. They are very common. Usually if you have need to translate your very lock or VHDL and to bring it on a silicon. You need small gates, NAND gates, OR gates and so on. But these gates need a lot of representation, they're combinatorial sequences. So okay, these are typical cells. Just a couple of them. But imagine we need much, much more. And the design goals for the standard cells are we need almost complete possibilities. If you have just a small selection of cells, the net list becomes huge. And every gate in the net list also means a dedicated delay. If you have long change, we have a long delay, so our operating frequency goes down. So if you have a more complex gate, we are better. But doing all this stuff is heavy. And we like to be low power, it means our cells have to be consumption less power than usual. We want to be fast. But yes, of course, it doesn't fit all together. Okay, for simulation, we need it. We need it for synthesis, we need it for timing. As you can see, everywhere on the slide. And of course, documentation. That's a lot of work. We have a small team. I am the only guy dealing with the standard cells. Usually our teams are also doing that. So okay, we need a tool for that, which do all the stuff for us. And this cell coordinator, I called it popcorn, because I put in some corn and advised up with the heat. Okay, we get all the representation. So usually, or currently, I have a tool on the repository, which is tackle, which does some stuff I like, I need, but not all. But it already seems very ugly. So for me, I like to rewrite it, but I don't figure out currently which language I like to use for that next time. It could be rust, it could be scheme or something like that. We need to have a language for that. So if someone wants help, please. But it's the next task, if you have a waiver done completely and measured. Okay, that's the link for the repository, where you can look at the queue and status. And there's a wiki where I like to describe why I doing what and which way. Yes, we have to do it a lot. Still more. Okay. Okay, hi. I took, I take a look at the current tooling that exists, like layouting, place and route to minimize the yield on the wafer. And obviously, because this is a Libre Silicon project, we look at open source tools. So we have YOSIS and Cravel of Q router and several other FPGA routers that exist. YOSIS is pretty good. We can probably use this for the synthesis, but the other tools, they lack very critical qualities for this, for Silicon, because they're in, for example, they are part of Q flow, which is an FPGA workflow. So the Gravel tool, it originates in academia. It's like, it's many decades old. It comes with some very good ideas. For example, simulated annealing, which, which is a meta-horristic you can use to solve NP-hard problems. But it's only one of the many choices you can make to solve the, the extra hard problems. But it also comes with bad implementation. For example, inline syscalls is a very bad idea. It's also written in C and blah, blah, okay. Q router is actually, it's pretty good. It started in 2011 by Tim Edwards. And it's widely used by hobbyists and enthusiasts to, to route for FPGAs, but it's not ready for Silicon, and it's especially not ready for our lipro-silicon process, which would require us to, to, to write a lot of C code for Q router. Also, parallelism apparently is not in scope. So I mean, if we want to scale up, for example, place and route in the cloud or whatever, or use modern CPU architectures, we are stuck with sequential routing, which is pretty bad. Also it lacks a very important aspect, in my opinion, which is formal correctness. So when we produce wafers in the fab, we want to make sure that they don't blow up in our faces. This is why we need some form, some form of proof that our algorithms are correct and therefore the result is correct. There are also other productive tools that are proprietary, which, where we can look at, but we cannot use it or fork it or whatever, but we can learn from the research that has been done. For example, BonnRoute, BonnRoute is used by IBM. The Cadence Suite, I believe, is used by Intel, and the Alliance tools is French academia. Very Unix-y, I mean, it's a very large set of small tools that convert different file formats to another. I mean, maybe you encountered this problem before when you did some hardware design. You have many different file formats that all don't play together very well. So you have tools like X2Y, which convert file format X2Y. And you see, when you want to place and route a layout, a very, very large chip, like a very large silicon integration, then this isn't even done automatically by tools. This is done with manpower when you look at a very large chip done by Intel or IBM. So this is an example of a very, very large chip. As you can see, I mean, do you think this has been done by automation? Like Industry 5.0? No. This is all manpower and a lot of manpower, which we don't have in the Libra Silicon project at the moment. So this is, the state of the art is like, okay, the manpower thing is one aspect, but the other thing is, so what you do is you do placing and routing at different steps at the design process. So you do placing for a very large chip, floor planning, and then you do a global routing, which is, you can imagine it like routing along a rough chessboard. And after that, you do a very detailed routing where all the different constraints regarding your technology come into play. And so, again, the formal correctness aspect. So you have some imperative algorithm that you cannot prove will blow up. And it's also not a very parallel code. So you're still stuck with the sequential nature of the code and you have no parallelism. What we propose is to not place and route for large chip, but decompose the large chip into much smaller units, like a component hierarchy or a sub-cell hierarchy. And then place and route the small chips at the same time. And then reuse the small units in larger units. So you get an evaluation tree you can work on and compile just the components you need. Also, we propose satisfiability modulo theory solvers. So we can have some first order logic where we can have constraints on the components, how they are placed. For example, they must not overlap. That's the most simple example I will show you later. And also, we want to achieve parallel or declarative code. So as you can see, we have many disagreements with academia and industry which work very well together. For example, when you want to study semiconductor design, you have to assign some NDAs with IBM or Intel to do that. So they say placement and routing or floor planning and routing are different problems and they need to be solved at different times in the process. And then all the components can be registers or NAND gates. It doesn't matter. They all treat it the same. It only matters that the floor planning is done first and then the routing, the floor routing and then the detailed routing. What we propose is that placement route is actually the same problem and that registers are different from full adders. So the geographical partitioning of the wafer is called floor planning or the placing step and this results in a cut tree. So this is how they do routing hierarchies. They just divide the wafer into smaller pieces and then do the following steps based on this placement. What we want to do is have subcell hierarchies and those subcells, they are either explicit. They are explicitly developed. For example, the rocket ship is where you're modular and it has many explicit very lock modules you can use and place and route that and then reuse it. And it also has implicit subcells like, for example, most of the time, for example, you have a full adder. It obviously is composed of one-bit adders so you can place and route a one-bit adder and then place and route based on the one-bit adders that you're awfully placed and routed and as a result you get a full adder. That's just one example. But I will show you a tree a few slides. So there you see a parallelism is something very important for us. Bond route allocates a lot of research to have some mathematical model for concurrency and shared memory models. Queue router, which is the open source alternative, has none, apparently not in scope. And what I propose for the Libre Silicon compiler is the map and reduce approach. As I've mentioned, you get explicit subcell hierarchies through high modularization that is done by the developers and you also get implicit subcell hierarchies by compression like algorithms that X line as opposed to inline the registers or one-bit adders. And this is also about preserving these new found hierarchies in the compiler interfaces so you don't end up inlining them again because this is not the von Neumann architecture where it would make sense to inline a lot of code. So the code runs on the stack in the level one cache. This is about reusing components. So this is a part of the rocket chip. The system bus is one component of a very modular chip rocket chip. And as you can see, it is composed of several simple lazy modules and those simple modules are again composed of other components. And then you have a lot of queues. And this number on the left says how many times it's been used. For example, a queue 15 is used five times in the AXI for a day interleaver. This is only the explicit hierarchy that is declared by the developer. Now when you apply some compression like algorithms, you can actually gain or you can get more leaves so you can be even more modular. For example, queue one is composed of several implicit modules and you can see one queue is even reused seven times. So you just route, place and route the green leaves like once and then you can reuse it in the queue one and everywhere where queue one is reused at some other point in the chip. Now I want to state a very simple optimization problem. What we need for the process is to have components and wires that connect the components or nets. And these nets and components are rectilinear geometries. The components shall not overlap and the nets shall overlap with the respective pins they are supposed to connect. The minimizing goals of this optimization problem is layout area, which is the most critical one because this is what maximizes yield. The maximum wire length because it's about resistance. The wire count, you want to keep very small, but you want to allow for wires. The crossing number is a computational thing. It doesn't really matter for the implementation on the silicon. And you also maybe want to minimize wire jogs, which is bends in the wire. So to solve optimization problems in 2018, maybe you want to use an abstraction from the SAT solvers you used to know. Academia came up with some pretty neat theories called satisfiability modulo theories. And you can just put some first order logic and give it to a solver. I've listed a few. For example, ABC is used by YOSIS and SET3 from Microsoft is also a very promising product. But you can obviously choose from many products by academia and industry. Just a quick reminder of what boolean satisfiability is. And assignments for all these six variables which are boolean so that the whole term is true. And now with SMT or satisfiability modulo theories, you can do the same thing. But now with integers and also more complex data types, but integers are the most interesting. So let's do something with SMT. For example, let's have a component that is rectangular. And now you can see this is like a Cartesian coordinate system. And you have the left bottom point, which is x and y. And then you have the right in the top point. And now if you, for example, have this problem that you don't want to have overlapping rectangles, you can have rectangle A and rectangle B. And declare these coordinates. And then have some proposition that shall be true. And to have a proposition that says they shall not overlap is to say this. I mean, it's actually the lower half, the lower half makes sure that they don't overlap. And the upper half makes sure that the components actually have the right dimensions. Well, in this example, they obviously have the same dimensions, the same component. And so you make sure that the left point of the second rectangle is like a right of the, okay, no, never mind. Okay, one last important point I want to make is that this framework we want to create, it's not based on the inheritance model that we've seen in the process steps right now. But we want to combine the problem, so example, the overlapping problem, the pin connect problem, and then arbitrary constraints that come up during the process development that Dave and Hagen will supply me with. And I will formulate that in first order logic. And then this makes sure it's formally correct. And it doesn't blow up. And as you can tell, I mean, I've combined many NP-hard problems at the same time. But I think we can manage that if we have very small cells. So I suggest we just stay here and don't do all this for very large chips, but reuse small chips and then reuse the small chips and other small chips. The Silicon compiler is one half of maximizing yields. And the other half is to get the process right. So to get the process right, we have David and Victor. So please. So thanks for the handover here. So very first, there's a lot of questions why Hong Kong. So one thing where this is a really suitable place to do that is because of history. Like the epic Commodore 64 has been made in Hong Kong. Then the chips in the first Macintosh have been made in Hong Kong. And all these manufacturing lines, some of them, at least one, is still available. So also there is a very advanced laboratory. That's the NFF, Nanofabrication Facility in Clearwater Bay. And they let us kindly use the equipment to develop this process. Also, one of these factories I mentioned before, Arsial Semiconductors. They're really open to introduce Libre Silicon in their mass manufacturing lines. One in Taitpo. Yeah, so in conclusion of that, we have advanced R&T labs there. There is factories available. We can easily export it to here over channels which already exist, right? And also in general, it's just more relaxed over there. And I don't like minus degrees. So our process is a little bit of a monster. So it makes sense to tackle that one by one. So we're right now feeling ourselves upwards to get the standard CMOS debug final with optimized frequencies there, right? But we already have on the Pearl River, I've shown you. We already have test structures for high-voltage MOSFETs, B-junctions resistors, Zeno diodes, even flash, resistors and caps. So, and this is the only question of effort, I guess, in the next few months to get it working, right? When we designed the process, like, how it usually works when you make a process as you look at the machines, you have available, what can these machines do? Optimum operation range, then you look what substrate, what material you have available, and then you start tinkering your own little proprietary process. That's how Febbs do that. And we said, okay, well, to the point where we look at the machines, what can they do? We do the same, but afterwards we look that it's portable, not specific to the equipment. So just because we have certain machines which can do awesome things, but they're really exotic, doesn't mean we have to use them. So we avoid exotic machines so that it's as portable as possible. And we also try to use wet-etching whenever possible in order to make sure that you even can build it in a basement. And yeah, Evan Heisenberg might be interested now in changing business into a less dangerous business. And yeah, they even can't build it in the innovation at Palmburg, I've seen, like this improvised clean room with just a diffusion furnace. That's cross-section of the, it's not final list, but you see a cross-section theoretical. That's, by the way, you can find it on GitHub as well. It's all in the publications, everything we develop, all the measurement data, all is on GitHub. So that's actually the layout of these little squares here on the wafer. The, you see the apple in the middle, it's the same as here. It's nice, I have a Python script in the GDS2 generator tool folder for Python. And you can take any PNG or anything and just convert it into layout format. So you can put your own pictures onto the metal-free layer. So in case you already are interested in making little chips or so. It's also possible to make like ear rings also with, we don't care as long as your beta is coming in meters on the silicon. You can put pictures on the silicon. So that was the Pearl River, right? And the Pearl River fulfills the function for us at the moment to debug all the features of our process, of the silicon process. Then the next thing, we have to use it to calibrate new foundries. So now we developed it at NFF in Clearwater Bay, right? And afterwards we go over to the RCL guys, right in Taipo, and they have the machines and then we have to pipe the Pearl River layout through there as well and repeat that process over and over again until the measurement data, like the frequency, you know the beta depending on omega of the transistors and the resistance of the virus and everything, kind of is the same as at NFF. So that you can basically, as I mentioned before, one of the design concerns is portability, that you can basically prototype a chip at NFF and then produce it in RCL or in maybe some auto-fab in Sunshine or whatever. And so, and if there are new features coming out, we just make a new release of the Pearl River test wafer and we give that around, we push it to GitHub and people can introduce and calibrate the process to support a new feature. And so that's how does it work? So usually typically you have something like a photo mask, like here. I didn't bring that one because it's in a clean room there and the dust might scratch my microstructures on there. So also afterwards I have to clean it for half an hour and I just, when I come back to Hong Kong from here, I'm so chat-like that I just want to get started again. No, no, no, wait for the mask. But that's a picture. And these masks usually are a stepper, a liner specific. So if you have a stepper, no. If you don't have a stepper, then you need to make a direct transfer. That means you have to make, you actually have to put the chips in the size you want to expose them directly onto the mask, then press the mask onto photoresist, expose and develop. That's messy because you have to clean the mask all the time. And it really depends. So actually you can do exposure even with data stepper. So you actually really could do it also there in this university lab in Hamburg. So all you need is this new UV light. So we have a little bit more advanced tech in Hong Kong. So we have here an SVG quota. This baby, this band says automatically HPR 500, the resist. So we actually just have to put in the left, you see the cassette slot. So you put there like 25 wafers also. And then you have a receive slot and put another cassette there. And it just starts sucking in the wafers one by one, put primer on it, softbakes it and easy. Then you expose it, develop it, hard bake it, chilled. We have two types of resist actually. And the 6400L for the implantation unfortunately has to be put in manually. So yeah, it comes and it gives you 10 seconds to open the chamber and put the resist on it. In both cases, however, it doesn't really matter so much because the thickness of the resist is depending on the RPMs of the spin coating unit. So you just have to kind of put two thirds of the wafer should be somehow covered with the resist and then you cover and then it must and the excess resist goes away. But you have to control the RPMs because depending on when you do wet etching, for instance, the HBR504 has to be enough thick because of selectivity so that you don't etch, consume, you etch and also consumes the polymer, the resist. So you have to make it enough thick that you don't have consumed all the polymer before you have etched your structures. And the same goes for the implantation because you can use, for that unit, 6,400 L. This one can sustain higher temperatures so you can use an implanter. Ah, thanks. But yeah, scatter. Okay, now afterwards, after exposure development, it looks like that. That's an alignment cross for our optical stepper. And, for instance, that's our ring oscillator. So it's one of the structures on our Pearl River, actually. So, Enwell Peewell. I have to hurry up, only 10 minutes, so sorry. So that's a picture. After developing, we have some Peewell masks developed so you have everywhere resist, except in these little crosses and stripes there, that's there below is the silicon, where we implant. So the receipt is easy. First coat, expose, implant and then resist strip. Same for the other, for the Peewell. And after the resist strip, you can put it into a diffusion furnace in an atmosphere for like four hours. So where does the four hours come from? So we have to fix equation. And the fix equation is essentially in a similar shape like the Laplace heat conduction equation. So there's already nice solutions for it. So for instance, if you use boron and phosphor, which have the nice property that they have the same constants for this DE. So if you have the same temperature, you basically have the same DE for phosphorous and both boron. So you can implant them next to each other and then put them at once into the diffusion furnace and the wells are the same depth. So that's why these two materials are usually used for diffusion. So that's one of the solutions. With that you get surface doping for the threshold equation, which I also will rush through in a moment. So yeah, the equations you see here with background doping, it's a little bit much. As you have here this natural logarithm inside. But besides that, you see this jump and that's how you essentially build a well. You have the background doping and you compensate the donors and acceptors with each other. So that's what this absolute value of the difference means. So the threshold equation is pretty easy and they are like basically mirrored for PMOS and NMOS. They're just like mirrored in the sense that one of the transistors, so PMOS is built on a N well and NMOS is built on a P well. And what essentially controls the threshold voltage or the operation voltage, which usually in the standard CMOS is around 0.8, respectively minus 0.8, that's doping here, like the donors respectively acceptors. And the QSS usually, that's the oxide charge, is usually a process specific constant, but that can change. And then you get flash. It can change QSS and then it's flash. That's what you use in Sonos flash. Stands for silicon oxide, nitride oxide, silicon. So there you have a standard, again, NMOS in this case, but you have a sandwich. Instead of a normal oxide layer and for the gate oxide, you have an oxide, a nitride and an oxide. And these oxide layers above and below the nitride are called tunnel oxides. And the trick is that with a high enough energy, you tunnel electrons through the oxide into the nitride where it's trapped and then you shift the operation voltage, the threshold of the transistor. And when you then put one at it, it doesn't turn on anymore. And that's essentially how the most used flash solution besides normal floating gate works. It's really simple. So, and after you get your wells out of the furnace, so a little detour, you wanna make sure that the lateral diodes which got into existence after diffusion don't create unwanted short circuits. So we use the technology actually developed much later after one micron already has been out. It's called STI, shallow franchise isolation. It's from the ULSI technology, as well as the silly side we use to reduce the resistance of the polysilicon gates. Here are some pictures. We did edge this one in the lab. That's the islands. So that around everything going down, that's the trenches in between the gates, between the wells. So we isolate them from each other. So the recipe is pretty easy. So either you have a plasma at your round or if you are not rich and don't have money to buy a plasma at your from eBay, you can also get this tetramethyl ammonium hydrox, and it's not having a German name, a word, so cool. The diluted with ionized water, three to one, and this 25% TMAH solution, you heat it up to 80 degrees Celsius, dip your wafer for in for six minutes, and then you get your structures. Metal is amnesia. So we did here the metal into connect for the ring oscillator. There, etching it also, you make a vacuum. Deposit 100 nanometers aluminum, 30 nanometers titanium for passivation. Take the vacuum away, dip it into HF until you don't see streaks from the titanium, then into aluminum edge until you don't see streaks from the aluminum, and then you have your wires. Yeah, I skipped that one. That's just really into connect, but I plan to make videos soon where I go through the daily video blog of results, but just that you see the oxide, depending on the angle, it has different colors. So that's LTO, the resolution. And then you see our topological measurement device. You see this one micron because we only deposited one micron for now. You see the height differences, and we see that one micron is not enough. So we still have this sharp edges, which we don't want. So when I'm back in Hong Kong, I have to deposit another two microns. And if you want to follow up, you go to my GitHub, okay? So Victor, that's him, and I have done that so far. It's only like two weeks because it took a lot of time to get all the masks manufactured, and so a lot of bureaucracy. We already have that much, and just stay tuned. We already have figured out so much in the last two weeks that it shouldn't be long before we can, well, finish all the features of Pearl River, create models with Harkins Popcorn, and start figuring out all the analog stuff for our MCU, and then we make an MCU. That's the first thing we want to do as soon as we have the features figured out of Pearl River. If the goddess is nice to us. Yeah, this code you are figuring is really cheap on eBay. So yeah, that's like the overall of the features. We want to build this microcontroller. And yes, because all the folks don't believe that there are people who want to buy such a MCU, please fill out the survey. Yeah, that one is from Hagen, I just skipped it. But yeah. So yeah, thanks, I'm done, I'm too late, but sorry. Thank you for the talk. All of these too late, we have time for questions. So there are two microphones, one is in the middle, and one is on the left side of the stage, line up, and we're going to take some questions. And there is already one question from microphone number two. Okay, sorry. Thank you for that interesting talk and all the development that you're doing. I was wondering, have you had any time to test your trend, this is yet, and then later on do you plan to release some sort of analog simulation capabilities? Yes, it was planned for the next few weeks, sometimes I'm back in Hong Kong. We're going to go back into the clean room. We actually wanted to provide a way to solve the problem for the Congress. Unfortunately, we were noticed, a short notice, that Thursday and Friday, they take the wet stations and the machines offline for maintenance of the AC. So we have already like the waiver, we have the isolation oxide, but we didn't have any time left to actually test the, you know, only having polysilicon, it's not enough. You have to also have metal to go with probes there. The stuff is micron-sized. Okay, your question, as Anna said, was in the direction of simulation, right? We like to measure all the stuff we have to produce. And with the values we get, we like to feed in spice models. So you can do analog simulations. And yes, we like to use this technology for analog stuff, because as I already mentioned, one micron size is enough for analog. You don't need smaller structures. Analog are always having huge transistor size for 20 or 50 microns, so they're huge. You don't need the small technology. So they are quite feasible for analog stuff. But let's say in this way, if you're doing analog stuff in a conventional way, you have to assign all the NDAs and you're stuck on this technology you're using. You can't transfer your design to the next FAP, because in the next FAP the PDK is a different. You have to transfer or to translate all the structures you have or rebuild again for the new technology. If you have a technology which you can take from one FAP to another, like our one, you are quite happy, because the analog stuff you're designed once also fits for the next FAP. So yes, of course, we like to support analog stuff. We need help for that. Of course, we have to measure. We are currently developing the wafer. We are currently working on the documents, how to measure, what we like to measure, and then we have to transfer the values to spice. But we've also documented how we are doing that, and so everyone can use the knowledge. Thank you. Thank you. Mike Wan, please. Do you have any plans for open source mask production? Like? Yes, actually, the problem is only that, as I mentioned before, if you want to have an opto mask for Staples, that's always manufacturer specific. If you want to have a direct transfer mask, not a problem. So I guess, so Sam is really helpful in the lab. He runs the laser scriber. We could talk with the folks at NFF. They were really lovely, helpful. They really like to, they really help us a lot. And also now that we talk with RCL, and they also have laser scribers, there we could actually also start producing masks in the long run. So yes, that's certainly one of the things I intend to do is providing optical masks for exposure. Yeah. Thank you. One more question from microphone too. Hi, yeah, great talk, thanks. I'm really interested in the, what it would take to build the FAB. What's the minimum set of tools? We've already seen a couple of orders of cost, reduction in sort of DIY biohacking by making the tooling a lot cheaper. Do you see that happening within the nearest decades in your sort of work? Yes, so for instance, I made my process by purpose this way that you can actually improvise most of it like the LTO growing and deposition and everything with the furnace. So what you need is a wet etcher, like some wet etch station. You can actually, there is a video from Jerry Esworth called making micro trips at home cooking with Jerry and he does micro trips in the kitchen. So, so it's not, you get scared, like HFS dissolves your bones and so on. And then you see the guys who already have qualified or employed there, they just without any PPE, nothing, just wrap into the way. Jeff. It's just a skill to scape folks from generating insurance problems. In general, it's not really that dangerous, right? So you can't do the stuff at home, no problem. And yeah, so we intend, so this process I made is so trivial. So we have also a branch called Super Low Tech. We just essentially, but that needs more R&T but you could actually help there, for instance, figure out the last details, get a furnace from eBay, put it on your kitchen table, start R&Ting, make some get pull requests and we're super happy. Okay, so it's doable and the furnace you get on eBay so it's not a problem. Thank you. Microphone one again. Yes, so you just said about the analog stuff that a lot of that is usually on the NDA for the fab. So have you encountered any problems with the fab that you're currently using in that you're actually trying to discover these processes for yourself? Like you're generating competition that they might not like. Have you had any problems with that? Oh no, I had the nice phone calls, emails with the owner of the fab over in Taipo, who also has the second brand in San Cien, that's Arsiel. I actually asked him recently, hey, is it okay when I use your logo in the presentation and implicitly make advertisement for your fab? And he, no problem, go ahead. So second, he's really eager to, Libra Silicon is what they need because every fab usually has to invest money to develop, first they develop the proprietary process, right? Or they license some proprietary reprocess from another company. And then they have to invest R&D costs to develop IP costs for their setup. With Libra Silicon the problem is solved for the companies because this foundry is using Libra Silicon. Everything the community develops is on GitHub. And that's the IP catalog, essentially. So they don't have to invest any additional money into R&D and IP costs. That's in the nature of open source that there are IP costs popping into existence all the time. They can focus on the thing they're best at making Silicon, right? So it's actually positive, but only for the small foundries, they're really interested, especially San Cien, now some in India, but the big foundries, they will not, they anyway, the big companies have the tendency to be as mobile as a cargo ship. So it will take at least like two years until they haven't acknowledged that Libra Silicon exists. And that, you might expect some legal, you know, bullying, but for now they won't even, they just laugh, right? They just laugh the best, yeah. We're going to have two more questions before we're out of time. Microphone two. Hi, why did you go for the Twin Well process as opposed to the simpler single well? That's a good point. That's also something with portability. If you have different vent or different supplier for substrate, it might be that's an endoped or an undoped substrate. So with Twin Well architecture, and actually we have on the end well, we also built P bases and in these end base, as well we have actually like stacked wells in the end wells and P wells. So actually it's a one, two, pentagon well, I don't know. And that's just that you can shift the doping of the end and the P substrate according that you fit Libra Silicon requirements to still have the physical properties ensured by Libra Silicon, no matter whether you get your substrate from somewhere from Great Britain or from Taobao. Okay, the thing is we looked before at eBay, which way for we can get. Currently, NFF is supporting us with Wafers. But if you're looking at eBay or Alibaba or what else, we get different Wafers with different top agents. And if we have something, let's say, okay, we just building an end well, we have to verify or lie on the P base, right? Or on the P substrate. And to avoid this obstacle, the difficulties we're doing Twin Wells, we can just regulate our own dopant inside and we are fine. We don't have to rely on the wafer or substrate itself. What was the basic point? Thank you. And the last question from microphone too. All right, so once you have your complete die, how about packaging and bonding? Because if you want to use it, you have to place it somehow on the PCB. Yes, so we have a bonding set up at Taipo already. That's what's still being used at the moment in Hong Kong is the packaging. Then we have some guys in HKSDP with packaging set up. They haven't can make nice taperels and they have also like after packaging tests, like did the bonding work, is it damaged by the bonding and so on. Hagen and I, we figured out some nice bonding pads design which didn't fit at all anymore into the talk. I already over talked like that. But it absorbs the physical stress from bonding. So we think that it's aluminum covered with titanium. So you don't have to sweat away any oxide. You have better bonding properties. So it shouldn't be such a problem and we have plenty of bonding and packaging labs which we have already promised to help us. So it's really like, it's more like to choose which one we take. Just an annotation. If you like a dedicated package, please mail us. We are fixed now on the dual inline package. We are thinking about Flipchip BGA but if you have other package which is more common for Tinkerer or something like that, please mail us. Thank you. Thank you for the talk. That was the talk on LibreSilicon, Leviathan, Chipforge, Andreas, Westerwick and Victor. Thank you. Thank you.