 Hello and welcome to this presentation of the interface of STM32U5 Digital Filters for Sigma Delta modulators covering both the Multifunction Digital Filter, or MDF, and the Audio Digital Filter, or ADF. This presentation is split into three parts. First, an overview, then a comparison between ADF and MDF modules present in the STM32U5 and the DFSDM module present in the STM32U5. DFSDM stands for Digital Filter for Sigma Delta modulators interface. And finally, a detailed description of the ADF and MDF modules. The Multifunction Digital Filter, or MDF, and Audio Digital Filter, or ADF, are high performance modules dedicated to the connection of external Sigma Delta modulators for sample acquisition. They also support configurable filter functions. ADF is a subset of MDF, except for the Sound Activity Detector, which is supported only by ADF. ADF and MDF target the following applications. Audio Capture and Detection, Metering. In addition, MDF can be used for motor control. The figure on the right shows an example of the spectrum aspect of a sine wave converted by a fourth order single bit Sigma Delta ADC. The main goals of MDF and ADF are to keep the lower frequency part, here the signal, to up to 10 kHz to remove the quantization noise and to reduce the sampling rate. The STM32U5 includes a module called DFSDM, which stands for Digital Filter for Sigma Delta modulators interface. Let's list the improvements made by ADF and MDF compared to DFSDM. Firstly, ADF and MDF support Low Power Background Autonomous Mode, or LP BAM, which allows these peripherals to be functional and autonomous in stop modes without any software running. Another clocking benefit is that the kernel clock of ADF and MDF only needs to be twice the beat stream rate, while the DFSDM requires a ratio of 4. In the frequency range, from half of the sampling frequency to sampling frequency, ADF and MDF improves image rejection. Refer to the figure on the left. The Cascaded Integrator COM or CIC filter implemented in ADF and MDF also improves in bandroop. A high pass filter is added to remove low frequency noise from the input signal. The gain or attenuation can be adjusted with an accuracy of 3 dB. ADF and MDF also feature saturation blocks which prevent wrap around of the binary code when the code exceeds its maximum or minimum value. Finally, ADF supports a voice and sound activity detector. All these innovations contribute to reducing the power consumption and improving the quality of the speech capture. A flexible trigger interface can be used to control the start of the conversion. This timing control can trigger simultaneous conversions or insert a programmable delay between conversions. MDF incorporates several features making it very suitable for interfacing Sigma Delta modulators for audio capture, motor control and metering applications. MDF incorporates six flexible serial interfaces called SITF and two common clocks for connecting of external sensors. A full digital matrix called BSMX allowing any serial interface to be connected to any digital filter. Six flexible digital filters called DFLT configurable for motor control, metering or audio capture. Two parallel interfaces for the internal ADCs only one is used in the STM32U5 to interconnect ADC12MDF. Flexible trigger interface to control filter acquisition and many other functions short circuit detector or SCD out of limit detector, clock absence detector, saturation, gain control, snapshot. MDF has two clock domains to increase flexibility and reduce power consumption. ADF is a subset of MDF making it very suitable mainly for audio applications. ADF incorporates one flexible serial interface and two common clocks for connecting of external microphones. A BSMX for selecting the desired bitstream. A configurable audio digital filter for audio capture. Two parallel interfaces for internal ADCs not used in the STM32U5. Flexible trigger interface to control filter acquisition. A sound activity detector for sound or voice detection. ADF has two clock domains to increase flexibility and reduce power consumption. This slide shows the integration of MDF and ADF in STM32U5. MDF is in the main domain while ADF is located in the smart round domain for low power applications. Thus the ADF can run autonomously in stop 2 and an interesting use case is a wake up request from ADF in the case of voice detection. Some pins are shared between MDF and ADF in order to share the same microphone if needed. MDF can be triggered by several peripherals such as timers, EXTI. ADF can trigger MDF when a sound is detected or when an acquisition is started. Trigger details are explained later in this presentation. RCC provides a rich choice of clock sources for the MDF and ADF kernel clocks. Note that the SAI-XCLK and PLL1 PCK sources are common to the SAI's kernel clocks. The clock frequency for MSI-K can be chosen from 16 frequencies. For the internal processing MDF and ADF use a processing clock which is obtained by dividing the kernel clock by the PROC-DIF prescaler. This processing clock is used for the serial interfaces, the ADC interfaces, the trigger functions, the digital filters, the short circuit detectors and the out of limit detectors. The MDF-CCK and ADF-CCK pins can be either output or input depending on CCK-DIF. When the MDF-CCK clocks are generated by ADF or MDF they are derived from the kernel clock divided by CCK-DIF. MDF supports two main serial modes, SPI in SDR or DDR mode and Manchester mode. For greater flexibility each serial interface or MDF can use its own serial clock input from a dedicated pad or a common clock either generated by MDF or received from MDF-CCK0 or 1 pads. ADF doesn't support the serial interface clock input. The maximum speed supported is 25 MHz. MDF only needs a kernel clock twice the speed of the serial link rate for audio applications. In SPI mode the serial interfaces sample the incoming data on the following and rising edges of the serial clock. Each serial interface provides two data streams to the digital bitstream matrix. One representing the data sampled with the rising edge of the serial clock, the BSXR signal and one representing the data sampled with the falling edge of the serial clock, the BSXF signal. In Manchester mode the clock is recovered from the data stream. Valid data is available on the BSXR output. A clock absence detection allows the application to detect if there's an absence of clock transition for a defined period of time. Example 1 shows the case where several sensors share the same bitstream clock. MDF can either provide a common bitstream clock as in this figure or receive the common bitstream clock from the external sensor. The second example shows the connection of several digital microphones. Only three IO pads are required to connect four microphones. Each microphone pair shares a single data line. It's also possible to provide one microphone with a dedicated clock signal in order to keep that microphone active while the others are in standby. Example 3 shows the case where independent sensors are connected to MDF. Each data line has its own dedicated clock. BSX receives the bitstreams from all serial interfaces and provides the selected input to the digital filters. For each filter any bitstream input can be selected. Each serial interface provides two streams, one with the data sampled on the falling edge and one with the data sampled on the rising edge. The SCD detects if the incoming bitstream remains fixed to the minimum or maximum value for a certain amount of time with a very fast response time. The application can program the time during which the bitstream remains at the same value. If the bitstream remains fixed for an amount of time longer than the programmed value, then an interrupt and break events can be generated. Break events can be used to perform an emergency stop of the power stages by asserting the break signal. SCD is used to detect short or open circuit errors like overcurrent or overvoltage. An SCD block is available for each selected bitstream. The figure shows an example where interrupts and break events are generated if the incoming bitstream remains fixed to the same value for more than 5 bitstream clock cycles. The MCF digital filter embeds several blocks offering great flexibility in filter configuration. The most important parts are the data source selector, the delay block, the main cascaded integrator COM or CIC filter, often called MCIC. The auxiliary CIC filter, often called the ACIC. This filter is included into a function called out off-limit detector or OLD. An offset error correction, a gain adjust called scale, a reshape filter called RSFLT, a high pass filter called HPF, a discard function, an integrator called int. The digital filter can be configured in multiple stages so not all parts of the filter will work at the same frequency. We call the FPS frequency domain the clock domain working on the bitstream clock. The FRS domain is the domain working at the frequency of the reshape filter, FPCM is the sampling rate at the output of the reshape filter. Finally, the FINT frequency domain is the final sampling rate of the samples stored in the RX-VIFO. The final stage is storing the data processed by the filter in the RX-VIFO. Note also that the filter works with the processing clock. ADF digital filter embed several blocks giving a greater flexibility on the filter configuration. The most important parts are the data source selector, the delay block, the main CIC filter often named MCIC, the auxiliary CIC filter often named the ACIC. This filter is included into a function called out off-limit detector or OLD. An offer error correction, a gain adjust called scale, a reshape filter called RSFLT, a high pass filter called HPF, a discard function, an integrator called int. The digital filter can be configured in multi-stage and thus all the filtered parts will not work at the same frequency. We call the FPS frequency domain the clock domain working at the beat stream clock. The FRS domain is the domain working at the frequency of the reshape filter. The FPCM is the sampling rate at the output of the reshape filter. Finally, FINT frequency domain is the final sampling rate of the samples stored in the RX-VIFO. The final stage is storing the data processed by the filter into the RX-VIFO. Note as well that the filter is working with the processing clock. The samples processed by the digital filter can be provided either by BSMX or by ADC1. The BSMX provides a serial bit stream and a symbol remapper is used to translate this beat stream into a series of plus ones and minus ones. The samples from ADC1 are resynchronized by the ADC interface number 1 ADCITF1. ADC1 provides the samples and the sampling clock. ADF has no connection to the ADCs. The delay block can be used to delay one or more data paths relative to others. Delays are performed by skipping a certain number of samples before decimation. Delay granularity depends on the bit stream clock rate or on the sample clock rate provided by the ADC. This feature is useful for beamforming applications with digital microphones. For example, in a typical speech capture at 16 kHz with a decimation of 64, the resolution of the DIY block is about 976 ns and sounds travels at about 0.33 mm in 976 ns. Increasing the decimation rate improves the resolution proportionally. The delay range depends on the depth of the RX-Vifo, but generally it's not necessary to delay more than one PCM sample period using this block. Other means should be used if longer delays are needed, either by software or by using the discard block. The abbreviation CIC stands for Cascaded Integrator COM filters. MDF contains a single flexible CIC filter then can either be split into two filters, the auxiliary and main filter, or used as a single main filter. CIC supports three configurations, main and auxiliary filters. This configuration is dedicated to motor control. In this configuration, the main filter can be CIC1 or CIC2 or CIC3 or fast CIC. And the auxiliary filter can also be CIC1, 2, 3 or fast CIC and is used for the out-of-limit detector or OLED. The CIC filter can also be configured as single main filter in CIC4 or CIC5. Those two configurations are generally used for audio or metering applications. In this case, the out-of-limit detector cannot be used. Note that the ADF only supports CIC4 and CIC5 configurations. The CIC data size is fixed to 26 bits. The gain of a CIC filter depends on the decimation ratio D and on the order N. The same applies to the data size. The decimation ratio and the order must be adjusted in order to avoid having a signal amplitude larger than 26 bits at the output of the CIC filter. In order to satisfy this requirement, this slide indicates the maximum decimation according to the order of the filter. CICN is a filter of order N. The CIC has a very simple filter structure based on adders. Higher orders attenuate high-frequency components more but also introduce a droop in the useful band. The amount of zeros depends on the decimation ratio and the zeros are a multiple of FBS divided by decimation. The figure represents the frequency response of CIC filters assuming a decimation ratio of 16. The offset error correction block can be used to cancel a DC component value from the signal provided by MCIC. The value offset is subtracted from the incoming signal. The application can change this offset value dynamically if needed. In addition, the saturation block prevents wraparound issues. A saturation flag is set in case of saturation to inform the application. The scale block is needed in order to adapt the width of the filter configuration and to the targeted application. When the reshape filter is used, the signal at the output of the scale block must not exceed 22 bits. If the reshape filter is bypassed, then the signal at the output of the scale block can be up to 24 bits. The gain steps are 3 dB plus or minus 0.5 dB. The gain range is between plus 72 dB and minus 48 dB. The gain value can be changed on the fly. A saturation is done at the output of the scale block to limit the signal width to 24 bits. Ideally, for a full-scale input signal, the signal provided to the reshape filter should be as close as possible to 22 bits in size. If the reshape filter is not used, then the signal size should be as close as possible to 24 bits. Too little gain can degrade the signal-to-noise ratio. Too much gain can cause saturation. The table shown in this slide gives the optimum gain value for several filter configurations. The left-hand side of the table is applicable when the reshape filter is active. The right-hand side is applicable when the reshape filter is bypassed. Also note that some specific applications may require a different gain setting. The reshape filter is a low-pass filter designed to improve image rejection and in-band ripple. The reshape filter performs a decimation by 4 after filtering. The reshape filter can be completely bypassed or it's possible to bypass the decimation by only 4. This feature can be helpful if additional processing must be performed by the software. The reshape filter needs 24 cycles of MDF Proc CK to output a sample. A saturation to 24 bits is performed after the low-pass filter. The following figure shows the transfer function of the reshape filter alone without the decimation by 4. The cutoff frequency is fixed to 0.444 times FPCM. The in-band ripple is plus or minus 0.4 dB. The stopband attenuation is 30 dB at FPCM divided by 2. The out-of-band noise is attenuated by a bit more than 70 dB. The filter gain is about plus 9.5 dB. HPF is a first-order high-pass filter designed to cancel low-frequency components which can be bypassed. HPF has 4 selectable cutoff frequencies. The gain of the HPF is 0 dB. The table shows some examples for audio capture at 16 and 48 kHz. The HPF output is saturated to 24 bits. The response frequency for the 4 cutoff frequencies is plotted in the chart. MDF offers the possibility to program the number of samples to be discarded after each restart. The discard block allows the first samples provided by the digital filter to be discarded in order to mask the filter transience due to the impulse response or settling time of the sensor. The discard function can also be used to delay the acquisition. Up to 256 samples can be discarded. In the example shown in the figure, the discard function is used to drop the first 5 samples S1 to S5 provided by the digital filter. The first sample transferred to RX-54 or the int block if enabled is S6. The integrator performs an additional decimation. The integrator simply sums the data provided by the discard block. The integration value can be any value between 2 and 128. The integration output can be rescaled by 4, 32 or 128. The integrator gain depends on the integration value interval and the rescale factor. To bypass the integrator, initialize the interval value to 0. The out-of-limit detector triggers an event when a signal reaches or crosses given maximum and minimum threshold values. The out-of-limit detector or OLD contains 2 digital comparators. These comparators are connected to the output of the auxiliary CIC called ACIC. This auxiliary CIC filter can be configured in CIC1, CIC2, CIC3 or FAST CIC with a decimation ratio up to 32. The ACIC size is 26 bits, the data source of ACIC is the same as MCIC and can be either a sensor connected to the serial interface or ADC1. The out-of-limit detector generates events if the signal is inside or outside the boundary defined by the thresholds. The generated event can drive an interrupt or break signals. This slide describes the triggers present in MDF. Each digital filter and the clock generator have their own trigger block. The trigger blocks are used to start and stop the acquisition of main digital filters or to start the generation of the MDF-CCK-10 clocks. Possible trigger sources are 14 signals from the other circuit blocks, various timers, LP timer 1, ADF, EXTI. These trigger sources are common to all trigger blocks. One common internal signal, TRGO, one dedicated internal signal, each OLD block can trigger the main filter. Several acquisition modes are available for the digital filters, asynchronous or synchronous triggered modes, and single shot or continuous acquisition modes. Several trigger possibilities, edges, rising or falling, and window. This slide describes the triggers present in ADF. The digital filter and the clock generator have their own trigger block. The trigger blocks are used to start and stop the acquisition of the digital filter or to start the generation of the ADF-CCK-10 clocks. The possible trigger sources are EXTI-15 signal and the internal signal TRGO. Several acquisition modes are available for the digital filter, asynchronous or synchronous triggered modes, single shot or continuous acquisition modes. Several trigger possibilities, edges, rising or falling, and window. Each digital filter can be enabled by the DFLT-XEN bit. The MDF-DFLT-XCR register for filter X contains two flags that allow the application to check the current state of the filter, DFLT active and DFLT run. The DFLT state can be off, the filter is disabled, wait, the filter is enabled and waiting for a trigger event, run, the filter is processing samples. In asynchronous single shot acquisition mode, the acquisition of each filter is triggered when its enabled bit is written to 1. Whenever the digital filter is in wait state and the DFLT-XEN bit is written to 1, a sample is processed and stored in the RX-VIFO. If the application sets DFLT-XEN to 1 while a conversion is ongoing, the write operation is ignored as indicated in the upper timing diagram. Consecutive samples are required as long as the enabled bit is equal to 1. When DFLT-XEN is de-asserted, the current sample is lost as indicated in the lower timing diagram. In synchronous single shot acquisition mode, the acquisition of each filter is triggered by the selected trigger signal with the selected sensitivity. Whenever the digital filter is in wait state and the trigger condition occurs, a sample is processed and stored in the RX-VIFO. The DFLT-XEN run flag informs the application whether the digital filter is ready to accept a new trigger event. Trigger signals are ignored until the filter is in wait state as indicated in the upper timing diagram. In window continuous acquisition mode, the acquisition of each filter is triggered by the falling edge of the selected trigger and stopped by the rising edge or vice versa. In the lower timing diagram, the falling edge of MDF-TRGIY signal is used to trigger the acquisition and the rising edge to stop it. When DFLT-XEN is de-asserted, the triggers are ignored. Several filters can be acquired simultaneously by selecting a common trigger source and sensitivity for several filters. A simple option is to select TRGO as trigger source and then set the TRGO bit to 1. Any other common trigger signal can also be used. Note that starting several filters simultaneously is needed for audio beamforming applications. With synchronous snapshot mode, it's possible to capture the last valid sample and the state of the CIC and INT filters using the trigger inputs. This feature can be used to interpolate several intermediate values between two decimated samples. Each FIFO has a depth of four words of 24 bits. MDF supports two modes of data transfer, independent and interleaved transfer modes. In independent transfer mode, RX FIFO streams are completely independent of each other. The transfer of samples into memory can be triggered by two events, when the FIFO is not empty or when the FIFO is half full. Each RX FIFO has its own DMA request or interrupt service. When the DMA is used, the application will find a block of data per FIFO in the memory as shown in the figure. This mode can be used for any kind of application. Interleaved transfer mode allows a single DMA channel to be used to get the samples of several filters. Interleaved streams must be sampled at the same sample frequency. In interleaved transfer mode, data is transferred to memory when all the RX FIFOs set in interleaved mode are not empty. Only the interrupt or DMA request of RX FIFO 0 is used. This mode is typically used for audio applications. As shown in the figure, digital filters 0 to 2 can be programmed to work in interleaved transfer mode, while digital filters 3, 4 and 5 work in independent mode. When the DMA is used, the data inside the memory block corresponding to the interleaved streams is also interleaved. See block 0 in the figure. Four break signals are available. Timer break inputs put the timer's output signals in a safe user selectable configuration in the event of an abnormal condition. Only out-of-limit detectors or OLED and short-circuit detectors or SCD can generate break events. It's possible to mix within one break signal the break events coming from all OLED and CSD blocks. This is achieved by the OR gate in the figure. This figure details the MDF interrupt management. Each digital filter path has its own interrupt vector. Alert events and data flow events can generate an interrupt. The alert events are RxVFO snapshot or RSFLT overrun, data saturation, out-of-limit detection, short-circuit detection and clock absence detection. The data flow events are RxVFO level reached and snapshot data ready. This figure details the ADF interrupt management. Alerts events and data flow events can generate an interrupt. Alert events are RxVFO or RSFLT overrun, data saturation, clock absence detection, sound level detected and sound level value ready. Data flow events is RxVFO level reached. MDF can be active in all modes except in stop 2, stop 3, standby and shutdown modes. In the stop modes, the content of MDF register content are kept. In stop 0 and stop 1 modes, MDF supports low-power background autonomous mode or LP BAM. In standby mode, MDF is powered down and must be reinitialized after exiting standby mode. ADF can be active in all modes except in stop 3, standby and shutdown modes. In stop mode, the ADF register content is kept. In the stop 0, stop 1 and stop 2 modes, ADF supports the low-power background autonomous mode or LP BAM. In standby mode, ADF is powered down and must be reinitialized after exiting standby mode. This upper figure shows the overall frequency response for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is as follows. CIC order 5 with a decimation ratio of 16, RSFLT enabled with a decimation ratio of 4, HPF enabled with a cutoff frequency of 40 Hz. The lower figure shows the inbound ripple for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is the following. CIC order 5 with a decimation ratio of 16, RSFLT enabled with a decimation ratio of 4, HPF enabled with a cutoff frequency of 20 Hz. The resulting inbound ripple is plus or minus 0.41 dB for CIC 5. The minus 3 dB cutoff frequency is 7061 Hz. The table on this slide provides measurements of the digital filters implemented in MDF and ADF. These results are obtained with the 5th order Sigma Delta Modulator microphone model delivering a signal having a DR of 126 dB at 0 dB full scale. The configuration of the filter is as follows. CIC order 5, reshape filter, high pass filter. Values of signal to noise ratio and dynamic range are provided for various decimation ratios. SAD stands for sound activity detection. The SAD function is offered by ADF. SAD can be used to observe the signal provided by the digital filters 0. It's intended to be used for audio applications. When enabled, SAD continuously computes the sound and ambient noise levels. SAD can work in two different modes. In sound detector mode, SAD can detect when the sound level or the ambient noise reaches a defined threshold. In voice activity detector mode, SAD can detect when the sound level is larger than a threshold referenced into the ambient noise level. When enabled, SAD goes into the learned state. During this state, SAD performs a first estimation of the ambient noise level using successive values of the sound level. When a first estimation of the ambient noise is made, SAD transitions to the monitor state. In this state, SAD waits for a trigger event that continuously computes the sound level and updates the ambient noise value. When SAD triggers, the state changes to detect. In this state, SAD continuously checks that the detect condition is still true. Even in the detect state, SAD continuously computes the sound level and updates the ambient noise value. To improve flexibility, SAD offers three options for controlling the transfer of the observed signal data to memory. Samples are always transferred in memory. Samples are never transferred in memory. Samples are stored in memory when SAD is in the detect state. Once enabled, SAD continuously computes the sound level value. The sound level represents the average of the absolute value of a number of PCM samples given by FR size. The ambient noise level, or ANLVL, is computed when the SAD working mode is binary 00 or 10. The ambient noise level is estimated in two different ways. By averaging SdLVL when SAD is in the learn state, by updating smoothly the ambient noise when SAD is not in the learn state, ANLVL is updated using the current SdLVL value when this sound level is considered as ambient noise. SAD is very flexible and several parameters can be adjusted to meet the needs of the application. The frame size, called FR size, it defines the number of samples used to compute SdLVL. The number of learning frames, called LFRNB, defines the number of frames used to compute the initial ambient noise level. The ambient noise level slope, called ANSLP, defines the slope of the ambient noise estimator during the monitor and detect states. The level just, called SNTHR, defines the trigger level. This trigger level is used differently depending on the detection mode selected. The hangover, called HGOVR, defines the minimum time the SAD remains in detect mode between two trigger conditions. The sensitivity, or level, called ANMIN. In voice activity detection mode, it defines the minimum ambient noise. In sound activity detection mode, it's used to adjust the threshold. It's also possible to have hysteresis on the threshold value with the HIST EN parameter. In voice activity detection mode, when enabled, SAD computes a first estimate of the ambient noise level. The ambient noise level is estimated using the sound level values, or SdLVL. The duration of this learn phase is given by the parameter LFRNBR. When an estimate of the ambient noise level is available, SAD goes to the monitor state. In monitor and detect modes, every time a new sound level value is available, SAD updates the ambient noise level and computes the threshold level to be compared to this new sound level value. If the sound level is larger than the threshold, then SAD goes to the detect state. When the SAD goes to the detect state, an interrupt can be generated and the signal ADF-SADDET goes to 1. SAD goes back to the monitor state if the successive sound level values are lower than the threshold. HDOVR is used to adjust the number of successive values. When SAD goes back to the monitor state, an interrupt can also be generated. Here's an example of SAD used in voice activity detection mode. At the end of the learn state, THR and ANLVL are updated and SAD monitors the input signal. In black, we can see the successive sound level values. ANLVL in dark blue is continuously updated and the threshold level, the red signal, follows the ambient noise level exactly with a gain given by SNTHR in this example set to 24.1 dB. When the sound level is higher than THR, SAD triggers. The green signal shows the SAD detection. When the signal is high, it means that SAD triggers. We can also observe that the ambient noise level is not updated when the sound level is higher than the threshold level, but the ambient noise level is updated when the sound level is lower than the threshold. The hangover function allows SAD to stay in the detect state for a given number of frames. Notice well that the light blue signal ANMIN defines the minimum allowed value for ANMIN so it's a kind of sensitivity adjust ensuring that THR will not be lower than a given value. In sound activity detection mode 1, SAD triggers when an absolute value of the sound level is reached. In this mode, the ANMIN field defines the reference threshold and SNTHR is used to define the trigger level or THR. The formula shows the trigger condition. In this mode, the ambient noise level is not used, but SAD still goes to the learn phase when enabled. Here's an example of SAD used in sound activity detection mode 1. In black, we can see the successive sound level values computed by SAD. The threshold level THR is computed from the value of ANMIN multiplied by the gain factor selected with SNTHR. When the sound level is higher than THR, SAD triggers. The green signal shows the SAD detection. When the signal is high, it means that SAD triggers. The hangover function allows SAD to stay in the detect state for a given number of frames. In sound activity detection mode 2, SAD triggers on an absolute value of the ambient noise level. In this mode, the ANMIN field defines the reference threshold. This reference threshold level is compared to the ambient noise defined by the gain selected by SNTHR. The formula shows the trigger condition. Note that if SNTHR equals 12 dB, then THR equals ANMIN because 10 power of SNTHR divided by 20 is approximately equal to 4. Here's an example of SAD used in sound activity detection mode 2. In black, we can see the successive sound level values computed by SAD. The threshold level THR is computed from the value of ANMIN multiplied by 4. The estimated ambient noise is multiplied by the gain factor selected with SNTHR before being compared to the threshold. When this amplified ambient noise level is higher than the threshold, THR, SAD triggers. The green signal shows the SAD detection. When the signal is high, it means that SAD has triggered. The peripherals listed below influence the behavior of MDF and ADF. Please refer to the corresponding presentations for more information. RCC for MDF and ADF clock control and MDF and ADF enable and reset, interrupts for MDF and ADF interrupt mapping, DMA for MDF and ADF output data transfer, GPIO for MDF and ADF input and output pins and triggers, timers for MDF and ADF trigger and break signal and peripherals interconnect matrix for MDF and ADF interconnection.