 Hello, this video is the second part of a series on practical RF impedance matching and filtering of the STM32WL. In this part, we focus on the transmitter matching network and a second harmonic or notch filter. The overall design of the transmitter RF path can be divided into several steps. In this part, we cover these ones. Initially, the entire transmitted path is not fitted with components except the RF switch. Let's focus to the first step about biasing the RF4-LP pin and the optimum loading impedance. Recommended biasing circuit is described in the application note 5457. The output pin of internal voltage regulator, VRPA, is connected to the RF output pin through the RF choke. Value of the choke is 47nm for our case. Values of the capacitors are not frequency dependent. We can use these values. The implementation of the circuit on the board looks like follows. There is additional DC switch which is not needed in our particular case. We will use only low power output. The optimum load impedance is the impedance we need to load the power amplifier to get the maximum output power. It can be visualized in the Smith chart and may look like this. This graph is the result of a so-called load pull measurement where we observe the output power as a function of the load impedance. The optimal load impedances of the STM32WL are summarized in the application note 5457 in this form as a snippet around the maximum power. Optimal load impedance depends on many parameters like package, frequency and power. Optimal load impedance may depend also on the PCB for example. On one board the graph may look like this and on other board like this. The actual optimum load impedance on a particular board may usually be somewhere around the nominal value as specified in the application note. Circles in the loading impedance graph are circles of constant power. The same color means the same power. Darker color means higher power. Then there are also curves of constant current. One curve means one specific value of current consumption. For our parameters, BGA package, 14 dBm output power and frequency 860 MHz, we can use load impedance measurement from the application note. We can see that a maximum power of 14 dBm is achieved when the optimum load impedance is around 12 plus J1 ohms. Current consumption is around 25 mA. We can verify that we have achieved the optimum load impedance by measuring the output power and current consumption. This method is used in this example. On the nuclear board we can measure power consumption of RF stage labeled as VDDRF. The solder bridge SB28 is closed by default. It must be opened. Then we can connect the arm meter to JP2. This current is labeled as IRF. Position of JP2 on the board is here. Now let's focus on how to calculate and fine tune the transmitter matching network. The stage maximizes the output power. As we discussed earlier, to have the maximum power we must load the power amplifier output with optimum load impedance. A matching network is needed. It transforms 50 ohms to the required impedance. Usually there is some kind of transmission line between the power amplifier output and the matching network which can have also impact to the calculation mainly if it's too long. Then it must also be taken into account in the calculation. We will load the matching network with spectrum analyzer which is used for power measurement. Design of the transmitter matching network can be divided into two main steps. Estimation of matching network values based on theoretical calculation. We usually don't know all parameters like impact of the PCB. This calculation can give us good starting point. Then we can fine tune the values based on the measurement. We know where we are and with small adjustments we can get to our destination. The transmission line between the power amplifier output and the matching network on the nuclear board looks like this. It's about 3.4 millimeters long. In our calculation we will assume an idle transmission line with an impedance of 50 ohms and neglect all side effects. For example there are some discontinuities and their impedance may not be exact 50 ohms. Ideal values of the transmitter matching network can be easily calculated in the Smith chart. We want to transform impedance 50 ohms to optimal load impedance. We can use 6.4 picofarad parallel capacitor and 3.3 nanohenry serial inductor. Then we also assume small impact of ideal transmission line. Measurement point is here. The rest components C16 and L6 are not fitted on the board. Here we can see the layout with power amplifier biasing, transmitter matching network and place where the pigtail is connected. It is connected to a spectrum analyzer through an RF cable. For simplicity small insertion laws of the pigtail and the RF cable are not considered in these measurements. Real connection of the pigtail looks like this. The quality of the connection has a big influence to the measured results. It's recommended to connect the ground as close as possible to the active pin. For power and current measurement we can use unmodulated carrier. The tconf configuration command with the following parameters is used for configuration. On the yellow parameters frequency and output power are important in this case. The ttone command is used to switch on the carrier. To turn it off we can use toff command. Here we can see the spectrum measurement. The carrier is a bit lower than 14 dBm. The current is also higher than 25 milliamps. This means that the power amplifier output is not loaded with optimum load impedance. We can fine tune it. We can see also a lot of harmonics in the spectrum. They will be filtered in the next stages of the transmitter path. We measured power of the carrier 13.59 dBm and the current 30.36 milliamps. If we visualize these values in the smith chart we can see that we are somewhere in this area. There are many reasons why we are not exactly in the calculated area. In our simplified calculation we assumed ideal components and the transmission line. The hotspot with maximum power may depend on the PCB. The load by the measuring probe may also have an impact. But even these non-ideal values are useful to us. We know where we are and know where we can go. We want to go here more to the inductive region where the power is higher and the current lower. To do this we can increase value of the serial inductor. In my measurement I increase the inductor value of L then by 1.3 nano Henry. The final inductance is 4.6 nano Henry. Here is a measurement after increasing the inductor L then. The carrier is higher about 13.9 dBm and the current is about 25 milliamps which are our target values. If we visualize our power and current in the smith chart we are somewhere here almost in our target point of the load impedance. If we load the matching network with the next stage of the transmitter path the load impedance may move a bit. This can be fine-tuned again when all stages are applied in the design. The next step is the design of the notch filter. Main purpose of this stage is to suppress the second harmonic. There are also several approaches how to design this stage. We will show one of them. As a rule of thumb the inductor L6 is about three quarters of the L10. In this case 3.6 nano Henrys. The reason on frequency of the LC circuit must be at the second harmonic. From this we can calculate the value of the capacitor C16. It's about 2.3 picofarads. Then we can measure the spectrum after the filter. We should check the level of the carrier and the second harmonic. If the suppression is not enough we can fine-tune values L6 or C16. This stage loads the previous stage and may detune it. Based on the carrier and current measurement as in the previous stage we can fine-tune values C21 or C14 to set the optimum load impedance again. In this case C21 was not modified and C14 was not used. The output of notch filter is loaded by the measurement probe which has also impact to the measurement. Here we can see the connection of the measurement probe after the notch filter. If we compare measured RF spectrum without and with the notch filter we can see that the main harmonic was decreased a bit by about 0.3 dB. The second harmonic has been reduced by approximately 25 dB from about minus 17 dBm to minus 42 dBm. Measured current was 23.9 mA which is a bit lower than without the notch filter. It means that the matching network has been detuned a bit. The root cause of the decrease in the main harmonic is detuning of the magic network and insertion loss of the notch filter. Because there are other stages behind the notch filter detuning will change a bit. It can be fine-tuned at the end. In this part we are focused to the transmitter matching and notch filter. In the transmitter matching part we optimize the output power and current consumption. The load impedance of the power amplifier output is close to the optimal impedance. The notch filter attenuates the second harmonic by about 25 dB. Following blocks have impact to the matching network so parameters as output power and current consumption will change a bit. Final optimization must be done later after the transmitter path is complete. Thank you for your attention.