 Hello. This session is related to the ADC Interleaved Mode. So I'm going to show you how to improve ADC something right. Today we will provide you tips and tricks on how to implement the ADC Interleaved Mode and in this way increase equivalent something right. As a part of the session I'm going to provide the ADC Interleaved Mode details from practical point of view the dedicated mode of the ADC DMA data transfer, so-called MDMA, using common data register. The example will be provided with a base on the Nucleo STM32L476RG. So quite popular board and quite popular low power STM32L4MCU, which is based on Cortex M4. So at the end of the session I hope you will be in position to reuse the material and implement the interleaved mode of the ADC on your side. So what is it ADC Interleaved Mode? It allows you to perform faster ADC conversion just by using two ADCs connected to the same input channel. So we have two ADCs, ADC1, so-called master ADC and ADC2, so-called slave ADC. So the first action to perform is to start the conversion of the master ADC. So then after sampling the stage of the master ADC and 0.5 ADC clock cycle and programmable delay, which is given in the clock cycles, the conversion of the ADC2 of the slave ADC starts automatically by hardware. So the master ADC after this delay starts slave ADC. And the user can control three parameters. The sampling mode period, which is given in clock cycles and you can select the particular SMP value from these numbers. You can find the SMP values in STM32L476 datasheet. Then user can configure the delay between conversion start of the slave ADC and also user can configure the resolution of the ADC. So it can be 6-bit, 8-bit, 10-bit or 12-bit. Today we will use 12-bit ADC resolution as the highest one. So once again ADC master starts, then sampling stage, then 0.5 ADC clock cycle fixed delay and then programmable delay also given in clock cycle and then automatic, by automatic I mean by hardware start of the ADC slave. We have two ADC active, so we can consider two data registers. Data register for ADC1 and data register for ADC2. The most efficient way in terms of performance, the handling of data output data stream from the ADC, it is ADC-DMA transfer. So the obvious solution is to use two separated DMA transfers, one from the one channel dedicated to ADC1 and second channel dedicated to ADC2. But thanks to the internal structure of the ADC peripheral on STM32L4 family there is data register so called ADC-CDR register. CDR states for common data register. So when ADC works in dual mode, it is possible to use this register, having the data from both ADCs in this register and this way save one DMA channel. So we can use common data register for DMA transfer and this mode of the ADC-DMA is so called ADC-M-DMA, multi-DMA. And if we would consider the highest resolution, the 12 bits, the CDR data placement is the following. The higher half-word consists of slave ADC data register, the lower half-word of the CDR consists of master ADC data. If we would select six or eight bits, the higher half-word of the CDR is empty and the lower half-word of the CDR consists of two outputs as well, but in this case we have higher byte for the slave ADC and lower byte for master ADC. But this is not our use case. Maybe it is a little bit better visible on the diagram given, on the drawing given in the reference manual. I mean the DMA transfer trigger. So let's try to find this within the reference manual. So here it is reference manual 0351 for the STM32L476 microcontroller and here on the figure 133 you can see the DMA requests in interlift mode when NDMA mode is active. So when we are using the common data register for data transfer. So we have end of conversion of master ADC then we have the following end of conversion of slave ADC and then following the end of conversion of slave ADC we have DMA request only for ADC master and following this request the common data register data are transferred to the RAM memory. Let's analyze our particular application. So as already discussed we want to acquire the data using the highest ADC resolution 12 bits and we would like to use the highest possible or just the highest something rate. So if the highest something rate is expected it would be good to use fast ADC input fast channels. So you can see in the datasheet that there are five ADC input fast channels connected to PC0, PC1, PC2, PC3 and PA0 we can also switch for a moment to the datasheet and see what is the difference between fast and slow channel of the ADC this is table 76 ADC characteristic so let's consider the highest resolution here so for the resolution 12 bits we have maximum output data rate or maximum something data rate 5.33 mega samples per second while for slow channel for the same resolution we have more than 1 mega sample per second lower data rate 4.21 mega samples per second so let's use ADC input fast channel it would be good to analyze also the conditions for the input circuit of the ADC as the signal source output resistance or the resistance which is seen from the input of ADC is important and also the capacitance the input capacitance or the output capacitance of the signal source is also important you can analyze the application node 28, 34 for the details let's switch to this application node for the moment and let's try to find the drawing showing the internal structure of the ADC it will be simplified structure yes, it is here so it is on figure 26 once again application node 28, 34 this is the figure showing the simplified external and internal successive approximation so as you can see there is an analog signal source and there is an output resistance this source has an output or internal resistance which is from the ADC point of view it is seen as an R-A-IN so the input resistance and there is a companion capacitance which combines both the parasitic capacitance of the PCB so this is CPCB and the capacitance of the input pin of the MCU then internally because we have analog switch as a part of analog input multiplexer of the ADC there is a parasitic serial resistance of the analog switch parasitic capacitance of the common pin of the analog multiplexer and then we have also the sample hold capacitor so it is CADC so we must consider especially the R-A-IN and C-A-IN impact accuracy of ADC conversion all the details related to all the considerations related to this point you can find within this application just below this figure the conclusion of the consideration on that point is that we can use the results of the simulation provided by ST and gathered or covered a very useful tool in order to estimate the SAR-ADC sampling rate this tool can be provided following your request on demand and this is online tool and as a result following given R-A-IN and C-A-IN you can get the suggested sampling mode period in ADC clock cycles so maybe I will switch to this tool as you can see the user interface it is web user interface so you need to use the web browser in order to analyze your application so the analyze is provided for the worst case in terms of temperature range or supply I think quite robust approach then first action is to select your target family of the microcontrollers in our case it will be STM32L4 you can configure the expected range of the ADC peripheral clock so let's do it we want to analyze the application for the highest possible output data rate so we can expect that it is possible only for the maximum ADC clock frequency so let's set the minimum clock frequency of the ADC peripheral to let's say 40 MHz and keep the maximum value because according to the datasheet the maximum peripheral clock frequency of the ADC it is 80 MHz then we perform the analyze for both fast and slow channel we need to analyze the parameters for the highest resolution 12 bits we have a and the maximum expected error it is 1 LSB then let's select this is the schematic you already seen so taken from the application node internal structure so the model for the simulation then we need to select the resistance of our signal source or resistance which is seen from the input pin point of view of the microcontroller I mean the ADC input pin of course so I selected 47 ohms and then you need to select CA in so the external capacitance or the input capacitance from the ADC point of view I selected 22 picofarads please remember these capacitance covers both parasitic capacitance of the PCB and also the input the capacitance of the pin of the microcontroller so then I can add plot the curve in red color it is for fast ADC input in violet it is the parameterization for the slow ADC input so let's focus on the red color and let's focus on the highest possible value so you can also see the numbers in the table on the right part of the screen here and as you remember the maximum clock frequency of the ADC peripheral it is 80 MHz so here it is FADC it is the maximum frequency so let's try to find the fast channel parameterization it is here so the item number 81 so the recommended sampling mode period 6.5 clock cycles and as a result we will get 4.2 mega samples per second data rate so we can also see this on the chart here so FADC 80 MHz output data rate 4.21 sampling mode 6.5 clock cycles ADC clock cycles having in mind the input resistance of the ADC pin 47 ohms and capacitance of the input circuit 22 picofarads ok, so let's switch to the slides again so we know already the recommended sampling mode period 6.5 then we can select the number of samples to acquire let's say 40 this is arbitrary decision so the ADC clock frequency has been already discussed we want to achieve the highest possible output data rate so let's select the highest possible clock it is 80 MHz synchronous clock then let's select the delay of the trigger of slave ADC just to remind you I'm talking about this delay so having in mind the 12 bits resolution and the period for the conversion 12.5 bits sorry clock cycles I selected 3 clock cycles as a delay between master and slave ADC start of conversion so the single ADC full conversion takes sampling mode period plus SAR conversion so 6.5 plus 12.5 it is 19 clock cycles and having in mind triggered the slave ADC after delay so here so the slave ADC will be triggered after sampling hold stage then 0.5 clock cycle and delay so in our case it is 6.5 clock cycles plus 0.5 clock cycles and delay 3 clock cycles and the slave ADC will be triggered after 10 clock cycles since the start of the master ADC conversion Output data rate of single ADC it will be 18 megahertz divided by 19 clock cycles what gives us 4.2 mega samples per seconds it is also mind you this value you can find also using this tool and you can see here output data rate is 4.2 or 21 regarding the user interface of our mcu application we are going to acquire the data every one second so every one second we will acquire 40 ADC samples dual ADC samples then after the end of conversion we are going to print out the data using onboard as telling the bugger virtual comport and we are going to print the data in csv text format in order to import the data in easy way to excel for example so ok then dma transfer one shot mode so stop of the dma transfer when the ram buffer is full we are going to save one dma channel having to ADC active so we will use ADC command data register and multi dma mode so mdma mode the printf output data stream will be redirected to uart and uart is connected to the onboard virtual comport of the excel in the bugger and here you can see in details the timings of our dual interleaved mode so the first action it is the sample hold stage of the master ADC so 6.5 cycles clock cycles and then the ADC conversion of the cell conversion starts of the master ADC 12.5 cycles but from the ADC point of view ADC 2 point of view the conversion of the sampling hold stage starts after 0.5 clock cycle plus delay which is 3 clock cycles so as a result we have interleaved 2 conversions and single ADC sampling period it is 19 clock cycles but if we consider the equivalent sampling data rate so the dual ADC sampling period it is 10 clock cycles here because here we have end of conversion of master ADC and then after 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 clock cycles we have end of conversion of slave ADC so we can evaluate the equivalent output data rate for dual interleaved mode it is 80 megahertz divided by 10 clock cycles so it is 8 mega samples per second so we almost doubled the output data rate of single ADC because the single ADC is 4.2 in dual mode we have 8 mega samples so the next part it is the practice we can start our tool, IDE tool and it will be STM32 cube IDE