 Good morning to all of you. We were looking last time a single ended diffam and we were trying to show that this single ended diffam, one of the gate inputs of a p-channel device a gate of that is connected to one of the output which is v out 1 and that makes it single ended. We also have derived from this by variety of ways that this v p remains constant so ac for ac that can be treated as ground. So this is what we did last time. I will just show the last equivalent circuit which I drew. What we said last time that since v out 1 is in ac output for m 4 that is acting like an input because connected since it is connected this will act like an input and since this is equal to of this value. So there is an input signal for m 4 and there is an input signal for m 2 and we say since both have the same output resistance this r o parallel this or this parallel this for this output at the node both transistors are give r o parallels and therefore r o p parallel r o n is always at the output resistance independent whether you derive from here or you derive from here and if you superimpose on them the output net v out can be that is what we discussed last time and we derived finally a equivalent circuit which I just we want to do it again show you again that for the m 1 m 3 side you have a g m v i d by 2 r o 1 r o 3 parallel g m 3 and this is g m 3 may dominate because it is a diode connection there and therefore this may actually dominate over r o 3. However as I said v o 1 output is v g s 4 and that is further used here m 2 m 4 side and we say say g m 2 v i d by 2 r o 2 r o parallel again I said it but this again g m 4 will be neglected because this will dominate and then this is the next source coming from the other input at the m 4 m 4 and then if I since I use the same r o both so I can directly add or subtract the currents and then put across this resistance to get the output which is essential doing superposition you stop this get a drop stop this get a drop add up okay okay so this was what last time we did. So let us look at the actual values actual expressions since v g s 1 is v i d by 2 and v g s 2 is minus v i d by 2 is reasonable assumption we also observed that v g s 3 is v g s 4 or v g s 3 if you are small signal you look at as I say some books may show you. So essentially if the v x is the output at node voltage which is our v out 1 then it is g m v i d combination of r o 1 parallel r o 3 parallel g m 3 whichever will be smaller will be dominating okay. So I just right now kept all 3 in parallel in reality whichever comes smaller among the 3 will take care okay 1 upon r plus 1 upon r 1 so whichever is smaller is the dominant term. So I just right now for the sake of simplicity or generality I put r o 1 3 g m as the this resistance output and then g m times this is there so g m 1 by and if finally if that becomes g m 3 dependent which is the smallest among them or g m 3 is very large compared to r o 1 upon r o so g m 3 will dominate so you get g m 1 upon 2 g m 3 times v i t. Now this fact that this is the output of the first stage that is m 2 m 1 m 3 is going to be the input for m 4 is what is going to be utilized to get the final v o value. So this derivation is necessary simply because this is going to be an input to the m 4 at the other side okay is that okay so this is what we did last time so far maybe this expression I just showed you. So from here you can get if you see a value of this if you are holding the current constant as the ISS then you can see from here it is only a function of W by L and mu because 3 is P channel device so it is essentially governed by the ratio of W by L and also mu n by mu P all under roots. So we can we always know roughly how much is the size of the transistors and we can get the alternatively what will be given to us given some final gains you will have to come back and figure out what is the size of W 1 by L 1 and W 3 by L 3 but typical design since all all circuits are kept symmetric in most cases except for the perturbations they have one can always say g m 1 will be equal to g m 2 and g m 3 will be equal to g m 4 or to say size of 3 and 4 will be same and 1 and 2 will also be same except that they may have some variations even if we feel that we are done in the same technology zone. So that essentially is why CMRR comes finite otherwise would have been infinite so this is the only criteria you should look that this is the size dependent gain it only depends on the sizes of the transistors or a designer my only interest is in getting the surface sizing okay because these are called mask in fabrication so for each layer what should be the channel length what should be the channel width that mask which I will create at the end for the gate is going to decide my performance so please remember my output is only sizes given a circuit specification I must arrive at the sizes of every transistor because when I translate them into a circuit for fabrication I will have to generate layout that layout will be depending on W by L which I create and those will be then transferred on silicon during fab and hopefully chip may work okay normally it may larger the technology node more guaranteed will work we will see today time permitting if short channel happens what is the major worry with us there are many worries but one of the major worries I may show you so is that okay so I can calculate the input to be m 4 or to the output of the first stage which is view one now looking at the output side the second part of the circuit we know we out is output voltage with minus vi d input and view with Vgs for the another input so we just super pulls them for as I just now said the method is open a current source use the only one of them open the other one and start looking for me other currents so if I do that by substituting all this it will become we out to be gm 4 R O 2 4 where R O 2 4 is R O combination of R O 2 and R O 4 is that clear this is a short in writing R O 2 4 is nothing but parallel combination of R O 2 and R O 4 that is at the output side what is the impedance you are seeing output impedance parallel combination of output resistance of 2 and 4 I repeat what I said if you see the circuit these are the only output resistances are in parallel R O due to this R O due to this which are at this node are parallel is that okay R O here R O here at the output both are in parallel because this is ground for AC this is ground for AC this is ground for AC so these two resistances are in parallel for this node is that correct for this node as I said since gm 4 is not a diode connected R O's will dominate gm 4 is almost infinite time it will it is it will not be see I kept it there because in case tomorrow you do something else there that term may there and automatically it will get cancelled if it is larger or smaller corresponding in general I kept it but as such it will not be there because it is not diode for this it is gm 3 is appearing for this there is no diode connection that is a normal transistor whose output resistance is just the R O same is true for true same is true for true okay unless there is a diode connection the gm will not dominate is that correct we are done that case for a diode connecting load and that is what we proved that time okay so the idea I substitute all these values once again Vgs 4 is V out 1 minus this and by substituting finally I get V out is equal to gm 1 gm 4 and assuming right now gm 1 is gm 2 gm 3 is gm 4 all P channels are identical or N channels are identical that means what are identical the W bales are identical the thresholds are identical is that correct the identical word means the Mu C ox is constant Mu N C ox is same for both Vt's are same for both and W bales are same this is essentially means identical as I said I repeatedly saying perturbations will take care only in the case of CMRR because that is hurting us and I write which was infinite value otherwise you can always assume them for equivalence of this say if I substitute all this you can see of course this is not exactly what is given in a book but you can write down V out is gm 1 gm 4 upon GO 1 plus GO 3 plus gm 3 many a times instead of using RO in parallel it is much easier for us if we use geos because then you can directly add is that correct many a times for the circuit people you should realize that if they are in parallel R is parallel it is much easier to add these rather than putting 1 upon R plus 1 upon R plus 1 upon R so I normally suddenly convert times so please do not feel anything wrong this is just the way of solving simplicity using simple solutions so gm 1 by gm 2 upon GO 1 plus GO 3 plus gm 3 plus 1 upon GO 2 GO 4 in plus the second term which is for the VID by 2 is gm 1 by GO 2 plus GO 4 into VID by 2 so once I get the relationship V out and VID by 2 I can always calculate V out by VID which is essentially the gain of this single ended differential amplifier in difference mode is that correct this is not a common mode gain it is difference mode gain AVDM this is essentially a AVDM case okay so please write down if you wish because I am not sure whether this is given in Radawee but I did not check may be there at least they do not use these the way I use of course I also when I see that book then I see oh they are using different term but I feel it is much easier instead of RO writing write G's which is easy to add of course this method of writing G's have come from you know my other Cali pressure Sharma who has very fond of conductance rather than resistance things which can conduct is what all electrical engineering is about if it is stopping right then it is not good now so I think I also once I will take his Q and I use G's because I see almost all his analysis he rarely use ours you always write one of on G or G so I figured out that I should also follow after so many years of my friendship 35 years so I just make a fun of it nothing serious is that okay so I divide this VI2 by VID and then I get this expressions and then I start putting GM3 is much larger than G01 or G03 and therefore I neglect those terms so I got POW by VID which is GM1 upon G02 plus G04 okay and if I suffer is that clear if I neglect these two terms this becomes one GM3 by GM3 this becomes to these two cancels so GM1 upon G02 plus G04 is essentially your difference gain maybe I should write AVDM so which is what is GM1 why I wrote this expression is relevant for us because from a designers point of view let us say what is GM1 GM1 is substituted as two times current in the each arm is ISS by two W by L1 into beta in dash divided by lambda 2 plus lambda 4 into ISS by 2 okay lambda 2 and lambda 4 are not same why 2 is n channel device 4 is a P channel device so lambda is not identical for n channel of course you can make this in process for possibly but in normal circumstances lambda 2 will not be equal to lambda 4 they may not differ drastically but since the mobility in P channels are lower than n channels normally resistances are higher in P channels once a while you think of it it may be better to use P channel as loads is that correct because it will give larger resistance per se okay the issue here is lambda 2 by lambda 4 ISS by 2 I took it up so it is beta in dash W by L1 by ISS and what is the output resistance I said you do not have to put a source and measure because obviously visible in calculation so it is one upon G02 plus G04 which is like this and case which is what I say normally may not be but if case you make lambda 2 equal to lambda 4 lambda this will become lambda I said which is same as what we have derived earlier from lambda ideas okay so once we get output resistance we get the gain the two major specification for if I am having found out and they are functions of what? The bias current and the W by L is that correct the bias current and the W by L so you have as a design parameter with you there are only two parameters governing the gain one is the size of the M1 M2 and which is same which is which is essentially governed is governing Gm1 okay and the bias current ISS which is also controllable externally is that correct either by the transistor which I will put for source ISS either the size of that transistor or the bias of that transistor or a mirror it from some other source which actually will go exactly the current which I wish I will show you mirror once later when I calculate so essentially I am trying to tell you that the designer I now have related okay if you want so much gains 10 to power 4 10 to power what a number you say also in many cases in books we should know this the gains are always specific voltage gains will be specified as voltage by voltage though it does not mean because it essentially is trying to tell that it is both dimensions are same but it is written V by V why because trying to show you say voltage amplifier is that correct so you also should get imbibe this because there are four kinds of amplifiers which we can use we all of you have gone through this earlier output current input voltage output voltage input current input voltage input currents and output input voltage input output so four process so is called conduct trans conductance trans resistance current amplifier voltage amplifier all four okay is that clear so this is essentially what we are doing and therefore we say that this V by V only tells input is voltage and output is also voltage okay so mean I did not write but I just thought you should know many books or many places the data sheets give V by V what is V by V it is trying to tell you it is the voltage gain dependent terms which are being specified sometimes they were a V by I I by V I by I so these are the methods of representing the amplifier outputs against if we further make an assumption which we will we are know that the P channel devices are same and N channel devices are also identical to each other which they will be in most cases we are now saying it means W by L1 is equal to W by L2 and W by L3 is equal to W by L4 this is not a necessity but it is much easier to lay out much easier to derive if these are available to you but that is not a necessity expression does not require anything equivalence of that if they are different we can calculate with all different RO different GM so what I mean there is nothing very seriously problem a problematic for getting all difference but in normal case defined design on an integrator circuit will give you this GM 1 very much same as GM 2 and GM 3 very much same as GM 4 in which case one of these sizes if you figure out 1 and 3 or 2 and 4 you will be able to why I am telling you this word 2 and 4 is related to output resistance so some way if I am giving you a ideas I am actually giving you some way W by L2 indirectly 2 and 4 but if I know 2 and 4 I know I know 1 and 3 as well so this is the design issue from what data is given to you and what specs are given to you and what is expected out of you then you can figure out which term is I will show you today and then some few expressions when I design things so is that okay but I repeat this is not a necessity this is just for the heck of it and in general I see people believe that it to be symmetric as much as possible they try it but that does not mean it is a necessity as far as the gain or any of the parts are concerned there is a problem why it is normally kept which I did not say so far is there is an issue of stability of an amplifier if they are not equal the capacitances will not be equal and there is a possibility of 2 stage amplifier oscillating okay having done this small signal analysis all through let us look at little bit carefully other 2 or 3 parameters which are essentially large signal parameters what does that large signal means if the input voltage is not only restricted to VID by 2 and minus VID by 2 okay if they exceed what would happen one of the major worry of any amplifier is and that question was asked and I think most of you must have written correctly that we are looking for large linearity that is V o V in relation should have stand unity or whatever number for a larger input voltage swing is that correct if that happens then we say we have input swing can be larger so larger inputs can be amplified that is called larger large linearities we also want as I said we do not want linear mode because answer within linear mode is non saturation so square lot turns will not be possible and it will give lot of distortions so that question which was asked is large linearity but device should still remain in saturation and not a linear mode means it is a non saturation we are already shown V o Vi characteristics if V in is outside the slow part the V o is not human sometime governed by V in it may become constant that is exactly what the saturation part appears there so this issue we look into this again we want to see the limits okay so these are called limits or ranges to ranges of interest to me one is at the input the other is at the output the output voltage maximum to minimum what I can get is called the output swing so one of the spec of a difference amplifier of other matter open is the output swing how much output maximum can you can achieve from a given circuit which you design the other of course is how much maximum to minimum input I can vary which will still give me gain is that correct so what does that mean the device still remains in saturation for those inputs beyond that they may not so I will figure out where they turn over from non saturation and then say okay this is the limit okay now in some cases that limit may still have distortion because the linearity may not be as good but does not matter you may actually tune some of the distortions or you may tolerate some of those distortions which distortion is most important third harmonic distortion think of it why THD is most dominant distortion problem then the second harmonic which most people first derive but it is the third harmonic which essentially is the trouble creator so linearity is such that the third harmonic distortion is small okay so we will see that when the game comes okay so here is an amplifier gains same thing which I showed now let us say case I just tell you how the data can be given to you that this is not being used specifically here but just to show you for a let us say I have a 5 volt supply this 5 volt has supply has come from 0.35 micron process okay we used to use 5 mic so all the books whenever you see barring the latest ones which may probably have 1.2 volt supply otherwise this is the data given by everyone so I thought if at all someday you are going to read the book you should have this okay the VDD is 5 volt on VTO of NCHO means stand for without substrate bias typically it will be 0.7 volt let us say plus minus this is the tolerance you will get actually similarly VTO P will be assuming right now we are using the same in many technologies allow that minus 0.7 plus minus 0.15 and for this 3.3 micron 0.35 micron technology you can use beta and dash which is NCHO this data of course I will provide you whichever technology file I will use the data will be coming from that technology file but as far as we are right now concerned it is the numbers are only numbers okay we are not saying that this is specific to a technology you may say okay this is the data okay or this is the spec in reality spice will not allow you random numbers for a given node they will specify each of them because their oxide thickness are known their capacitance they know everything there okay so they will specify automatically these values which you do not have to even worry but if you want to read you they will show you also what are the values they are being using in this so typically beta and dash is used 110 micro amp per volt square please take it units should be correct in every sense because this is something I do not like people do not putting any units sometimes I also forget but if I do I write become a teacher you are a student you are no writes so this is micro amps per volt square beta P dash is chosen 55 what is that means half of that means the ratio of mobility is chosen as 2 okay mu n by mu p is 2 if they specify something else obviously this numbers will also change okay there is another number which is what we are going to use is called input common mode voltage which is defined as V ICM and typically for this supply okay we will come back this we are this is what one of the thing which we want to calculate right now evaluate but right now assume it for this is roughly 2 volts which is fixed W by L for all transistors chosen here are 2 no reason just that is that okay so if I use this okay I mean this is a data probably I may use in my problem so that is why I give you data it is not that this data is very relevant data or something this is typically for 0.35 micron most people believe this is okay values in reality the table from spice will be made available to you whatever specs they get it they will specify so those values are only arbitrary from my side but they will give you exact values many books actually gives you data files okay if you see a book they will for a given technology they will give you tables for all parameters he asks everything water and variations everything they will specify okay all cga cgd every capacitor everything they will specify okay of course per micron they will specify because width will change the net capacitance but they will specify all data file data file will get every detail of that so please if you have already done ng spice or whatever spice you have technology file there you see all these things are provided by the there are of course the specter or spice does not allow so much easily but there is a model card in spice which you can write yourself so it is not that what their default values are there you have to only work with it you can change your model parameters and still work on it if you have used model card of your own so do not come and say that sir both of fix any you can always change your spec of your choice by putting another model card there I am not sure with ng spice or spice to see 3.3 has that but just figure it out the model card allows you to specify all news to ox everything of your choice so please take it these are some issues of interest this figure is very important I think this is what we are going to explain once again if I plot the V out versus input V ID I figure it out from here this minus V ID by 2 somewhere if you look at it very even up to minus V ID by 2 there is some slope there is some slope beyond that it becomes almost constant is that clear so we say okay what should be up to this or up to this what should be the range up to which device can be treated in saturation so here is the figure we which we have plot this need not be exact numbers but just to show you if I see from V ID minus somewhere close to V out of 1 volt for example for V T of these values around point to V ID or something it starts climbing at this value device enters saturation below that device is in non saturation or linear mode this active word is used by analog people very much in a wrong fashion because active essentially saturated mode in MOS transistors okay but that is the time where device amplifier is active so I think this active word is not very true but you should maybe we should write non saturated because that may create some bias okay so similarly if I see go beyond from 0 towards plus V ID somewhere close to this value of point to or something V ID I figure it out at around 4 volt of output the device enters non saturation from where this value that I have VGS minus VT exceeds V ID VDS as long as so we have now said gain can only occur when both M2 and M4 are in saturation okay at the output M2 and M4 are the two transistors so if they are not in saturation this RO parallel this will not be there GMs will not be there and therefore by the way you calculate GM linear and figure it out why I keep saying it is much lower okay otherwise you say why the GM henna but that is much smaller than GM side and therefore this is the game so we say now we start looking into the please keep your figure up there I will keep figure for myself here we would say if VDA for the M2 transistor to be in saturation VDS 2 which is the drain to source voltage of that transistor should be larger than or equal to VGS 2 minus VT is that okay VGS 2 minus VT this is straight forward transistor theory however if you look at the VDS 2 it is nothing but this voltage minus VS call it okay this you call VS 2 so they are equal but these are voltage at the source which are grounded but let us put them there okay so I say okay then it is V out minus VS 1 is my VDS 2 which should be greater than now this is very interesting the VG this VG 2 part is essentially the maximum input available and from where saturation is guaranteed is VID by 2 so that is the swing available for you VICM is the end of that and VID by 2 you are going to put so what is the range in which because we are finding bound so what is the maximum available to you is this much okay so if I do that analysis so I say VICM minus is actually VG 1 VG 2 minus VS 1 this is VGS 2 minus VT but have you yes what is VICM is the input common mode range maximum and minimum range so if you are away from VID by 2 up to which transistor remains saturation the test we are giving but it will still require one VID by T to turn it I mean to have a signal so the difference available for me to see whether device still in saturation is VICM given to you minus VID by 2 since VID by 2 is this but essentially the transition occurs very close to 0 itself so that turn can still be neglected by you but just to say that it is there I kept it normally books do not put that term they say it is VID only VICM but I say okay in case you feel it the reason why they are doing it because the transition if you see is occurring very close to 0 okay is that clear and that is why they normally neglect that VID to turn but if case you want to keep you can keep but that is smaller than other values so it will automatically be numerically neglected physically maybe it is that okay now I always try to say people that why people are saying something in the books or otherwise so explanation there is nothing very great I am telling so I wrote that if the transition set to non set occurs very close to the 0 VID value then we can neglect this term anyway so we say essentially what we are saying the V out should be greater than VICM minus now similarly I can calculate the limit for this was for M2 is that correct this was for M2 now I calculate when M4 will remain in saturation so what is the criteria for M4 then that the VDS4 should be larger than VGS4-VTP VTP is the P channel threshold so I say and this has to be subtracted by numerically so I put a mod otherwise it will get added you know minus of minus may get added so I just put them on so if that is so it is VSG4-VTP but let us look at the game okay now we can see from here VDS4 this value is how much VDD-V out VDD-V out so I substitute VDS4 is VDD-V out okay it should be less than now because this is minus is that correct change the equality so V out source is for a P channel source is power supply and why otherwise holes cannot come down okay so if I write this then V out should be less than equal to VDD-VSG4-VTP I flip the inequality if I get this how many V out I got it now first I got it V out from the M2 side the other I am now getting from M4 side which one you feel will be larger please remember from the input side is coming from the ground side look at it this is what input to ground but this is what output to the ground okay so it goes to ground but VDD ground is AC ground but it is VDD so always the output side has larger value from the VDD side and smaller value from input side or lower side and therefore M2 decides the minimum value of the swing and M4 decides the maximum value of outputs so if I do this expressions which you have written down if I do that clearly the output swing of a defam is V out max-V out min which is V out max is VDD-VG4-VTP V out min is equal to VICM-VTN and therefore please take it that this is AC what is the criteria I have come from that M2 M4 should remain in saturation so from there I derived these two values and say difference between them is the maximum swing output can have this has some okay ramification word was difficult so it has an influence okay on the next device input characteristics what voltage it receives okay yeah we will we are not I am not said we cannot evaluate VG4 is known to us V out 1 he cannot but you are right I am not denying but why I left this because some what will be given to me and what will be right now I do not know so I am keeping expressions as they are okay when I evaluate I will figure out what is given to me and I will come back to the evaluate this value from each other either they may give me this or they may give me something else so I will arrive at this value from please take it what is VGS essentially can be written as in terms of ideas is equal to VT plus under root of these items you can always write so whichever way I am provided VSG I will be able to calculate anyway that is right now I do not want to say what is that you are perfectly justified in asking but I did not evaluate earlier because I will see which value value if I know that is this current I will say I know how much is because this current will be output current is decided by something which we will see now so that also may decide VG4 gain is essentially is very small because the end we are looking at the end of the games linearity just going out of linearity their gains are anyway very small is that clear if you are in this range then only is you dv0 by dvn is very large but if you are here you are anyway very small games so we did not consider assuming unity gains which is not true to some extent is that okay but these are bounds we are not saying these are the value these are the bounds up to which this swing can be all please remember I have put larger or less than I never said equal to equal is the better possibility but may not they should actually satisfy the inequality is that correct okay so one swing one parameter of one specification of defend we have seen gain other we have seen the output resistance third we have seen swing and the fourth we will now see which is what is caller input that I see my use so now I will derive that ICMR another important specification of a defam is called input common mode range is that okay so should we go ahead a was output swing so B is named as input common mode range so what is the input variations you can have from VDD to VG1 is one possibility and from VG1 to VSS or ground is the other possibility now that is how input will vary is that correct please take it input will vary from source to the VG or VP to this or from VG to VDD as we did for output same way we now do it for input side is that okay Raj okay from VDD we can reach VG1 through M3 and M1 please look at it if I had to reach here I can say drop across this drop across this and subtract here or add whatever signs so one path is like this which is the other path other is to come here and you directly write from here okay if you do this so there are possibility of either this but if you reach this value you can also reach from here to here so VG1 can be attained through this way or through this way or through this which is actually these two are identical because this VDS will be related to VGD okay so either I come from here or I come from here I have the access to reach VG1 and same is true for VG2 okay so if this is what I am saying I have two paths so I said same way I said there are similar there will be two paths for VG2 we can reach through M4 and M2 is that correct identical so either a both either each path will give us VIC max and we will figure out whichever is lesser okay that will be my range because lesser why I should choose because I am finding the limit up to which device will remain in saturation is that correct so I will figure out two VICMs okay and then I will say which one is smaller that I will use so here are the two way of doing it path one which is VIC maximum one is VG1 max please remember what is the input common mode value which is the input maximum value available to you which allows device to remain in saturation so it is VG1 max how much is VG1 from the figure this value minus this value so you reach here okay that means you reach here minus this value okay minus this value okay so not minus why we are climbing up so it is minus that is plus so VDD minus VSG3 minus VDS1 plus VGS1 is VGG1 max however at the age of saturation what is VDS1 when this transistors and this VDS minus VT or VGS minus VT is equal to VDS that is the age the lowest value of that so I write VDS1 is VGS1 minus VTN at the age of saturation so I write VIC max1 is VDD minus and I replace this VDS1 by this okay this substitute here so I get this VDD minus VSG by 3 plus VTN is the value which I am going to get what is is that clear to you what did I say I substituted VDS1 in terms of VGS1 minus VT okay and then that VGS1 cancelled and only this minus this cancelled and VT become positive so in terms so it is VIC maximum 1 is VDD minus VSG3 plus VTN the other path which is part 2 okay which is VDD minus VDS4 this minus this drop so reach this output minus VDS2 please look at it what is the other path I come here VDS4 VDD minus VDS4 minus VDS2 once I reach here I just add VGS2 to come here or VGS1 to come to the other side is that correct so if that is so I have solved now the other one VIC maximum 2 is VDD minus VDS4 saturation minus VDS2 plus VGS2 is VIC max but what is VDS2 at the age of saturation VGS2 minus VTN okay so substitute this here is that correct at the age of saturation which is the limiting point for then the saturation will go so that is the value I want max I am looking now so the age I am looking so we I substitute this VDS2 here okay magnitude wise you are right subtract VSD by 2 but it does not matter as far as the P channel device everything is in opposite sense okay so it does not matter so if I substitute now this I get VIC maximum 2 is VDD minus VDS4 plus VDN VTN and but VDS4 is VGS4 minus VTN but VGS4 is VGS3 we are connected them okay so I write VDS4 is VGS3 minus VTN and substitute that again here oh sorry sorry but VTP is equal to VTN so it does not matter so VIC maximum is VDD plus VSG3 plus 2 VTN is the value of VIC maximum 2 so which one is smaller among the two expressions I derived one is what was the value I derived first one VIC maximum is VDD minus VSG3 plus VTN and this other one is VDD plus VSG3 okay so what I am trying to say VIC max 1 is smaller than VIC max 2 so what is the VIC max we should use is lower 1 which is VDD minus VSG3 plus VTN is the value we are using for VIC maximum input common mode range which will allow the transistors to get output both sides and still remain in saturation is this value one of this which is the other value I am going to get from from the ground side or the source side is that okay method so please take it in all analysis of amplifier the max value come from V a VDD side and min value come from ground side or VSS side okay so let us derive the VIC minimum part so what is the path of VIC minimum for either transistor this drop please look at it from ground or VSS this drop plus this is that clear this plus this this plus this so that is the only VIC available to you to reach to the VG1 or VG2 okay if I use this and we do have to be since we have VIC minimum is VG1 or VG2 minimum to VSS path we derived VIC minimum is VG minimum or VG2 minimum which is VSS plus VDS5 plus VGS1 or VGS2 because we are assuming VSS to be 0 anyway okay drop at the p point is 0 so I get this value which is VDSat5 plus if VSS is taken 0 then VDSat5 plus VGS1 or VGS2 whichever way typically VDSat please take it VGS minus VT for the data given to you is typically the value which you get at the age is around 200 millivolts okay but this is again for the 0.7 volt supply okay so one should not use 0.7 volt VTs if you are another technology this 200 millivolt is not true this 200 millivolt I just want to show you order in which this numbers appear okay so VDSat is typically for 200 millivolt for the source which is used current source so we now define input common mode range as VIC max minus VIC min and this is the value which is please remember this normally will be specified by us how much is the drop across the current source okay that is VDS5 is normally specifiable these will be given to you as technology parameters this you will have to calculate from currents or voltages through whichever you come this is given to you so everything is given to you so you know ICMR or if I give you ICMR one of the parameters which is missing can be evaluated typically VDD VT and this will not be only thing will you will be able to evaluate is VHG3 or equal to VHG4 if I have specified you input common mode range is that correct this is the range so I am essentially specifying to great extent this value is that clear one kuchhara tha na VHG3 kaas yaan se laasastha specify karjaya tha baaki sub constants so we can always get VHG3 okay is that point clear this is a trick in designs which spec is given and which you have to evaluate please remember this VSS is 0 is not a normal case in most opams you will always have dual rail so you will have VDD 2.5 and VSS minus 2.5 swing still may be 5 why there is a necessity of putting a minus supply instead of why not single supply 0 to 5 0 to 3.3 why people in analog in specific always want to run dual rails there are many other four reasons but the major reason why we did was to reduce noise considerations okay is that expression okay so ICMR is VDD minus VHG3 plus VTN minus VDSAT pipe plus VGS1 okay so let us do the next parameter of my interest I have done so many I am now giving one by one all the spec for a given defam and whatever I am giving from defam are almost true for every one of them for opam with few more with opam okay the next important parameter for me is this power dissipation this also will be specified from where this gets specified why should I specify power dissipation do you know from where this power is actually getting limited you can say power supply yeah that is a great issue but that is not the only reason in pressure so essentially it is decided by the change in temperature of the device and we know around 150 plus the junction loses is junction property and because of that no junction will remain as junction versus the leakage current will go so high it will be higher than the what we call diffusion current will be dominated by drift currents so we want to void that situation so what do we do then how do I decide that I say okay how much is the sink heat sink I am providing for the chip that is called the thermal resistance available for to the ambient from the source of heat so I saw a thermal conductivity equation continuity equation and figure out for given thermal time constants that is the conductivity of the materials I am going to have in series of them and I have figured out how much heat I can dissipate so that I mean temperature does not exceed this delta P by delta P is called thermal resistance delta T by delta P is called thermal resistance so I must know that for a given temperature rise with the available day thermal resistance of the path I know how much is delta P possible that is P possible so power is limited by the heat sink and not anything else is that if you can remove the heat you can guess from this your laptops or nowadays iPads or whatever Android based any other annual system they have been very low in power for variety of reasons okay but they are not only are power supplies low but they are the method they are used the materials are much better heat sinking material where as in a desktop system huge fans are put at least your main power supply okay you know the motherboard is fixed with the SMPS used if your SMPS goes your motherboard also has to be changed because the voltage we are using a so high for speed that we do not bother heat generation but then it has to be removed okay that is the reason why power is essentially decided by the thermal gradients you create of course in real chip there are another problem if thermal source is away from the actual ground this and they are huge transistors at different sources they themselves conduct across and then there is a huge thermal pattern comes so all device properties are different at different point of time and one does not know what character see this called thermal simulations so one of the major simulation we do first in real chip design is to do thermal assimilation where the pattern thermal patterns are microprocessor make a you can pass as a hotspot one type so power dissipation is the power supply multiplied by the source current which is ideas 5 in our case generally we will be given PD max or we may say given PD max divided by the supply for the technology node we will decide maximum current available to you is that correct what is the source maximum current given to you is decided by the power dissipation for you okay it is a jada current kahi be flowing on that please remember this is for one arm in fact if there are 5 farms you have to divide by 5 that is power in each arm you have to get and then find the idea 5 because at any time gradient should not be okay so this is one term which is limiting currents please remember if I change the current what changes everything changes so far whatever terms I derived everything is related to ideas okay ISS which means any change there will affect all other parameters so we must guard that the set for the fifth or sixth what a number I made the next parameter of interest to me is the slew rate okay now if you see a simple circuit shown here this defam is driving a load capacitance of CL so one can say slew rate is defined as how fast the output rises to the maximum or change from higher to lower or lower to higher so essentially it is defined as dv0 by dt rate if I multiply it by capacitance and denote divide by capacitance I get CL dv0 by dt by CL which is same as the rate but what is CL dv0 by dt is the capacitive current and the maximum current available to you is ideas why we will show you why that is the maximum current in the capacitors will show you the right now it is not so visible but so ideas 5 by CL is the slew rate so what does now I am going to get it if I am given a specified slew rate so many micro volt per microsecond 10 20 100 whatever number I specify as soon as I specify slew rate to you and in the load is given to I am also now giving you limit for ideas 5 so which one I should use optimal which satisfy most of them that correct not all of them exactly but close to that if you can get so ideas 5 is a design parameter and that is why I say normally I prefer GM by ideas design because ideas is now your design parameter is that clear is that point here ideas decide I fit that is source current decides how much is everything going to be and therefore you must actually look for this value from variety of specification given to you slew rate Bola BOX Fisker KK power Bola GM Bola gain Bola all okay if you look at the frequency response the bandwidth part let us say for this all other capacitance are not very relevant which may not be true and this is the dominant pole so the 3 dB value which is my bandwidth is 2 by R out CL so R out is this 1 upon 2 pie 3 dB 1 upon lambda I okay what is lambda what is the R 1 upon lambda I my idea is this R out could be may up may is transistor case of silicon so it is 1 upon GO 2 plus GO 4 or lambda p ideas 5 by 2 however the difference gain if I now substitute GMR this like this which I had derived now I can see from here ideas 5 can be evaluated from power supply requirements that is power requirement fluid requirement I may choose one ideas 5 and then start looking for the gains power dissipation the slew rates is that clear once I fix this then I will compare with my specs given then I will okay change this that is what and that is why I keep saying nowhere the gains will be specified as 1000 greater than equal to 1000 okay so you have play enough slew rate will be also said not less than so many micro volt per microsecond not less than is that clear same way the power dissipation maximum allowed is this it does not mean you cannot have lower power dissipation it does not say gain should not be more than what you say it is the bound which I am giving the designer should choose values which suit therefore all specs as much as possible is that clear to you so ideas 5 being my design parameter let us see if you fix something and your gain does not come what is being specified so increase W by 1 L1 is one possibility or increase the ideas 5 itself okay if you increase W by L1 indirectly you are also increasing ideas 1 which is connected to GM 1 so please verify which term GM by ideas I told you now please take a GM by ideas I am looking into this will decide my GM part ideas will be decided by the other three so I am a design parameter therefore is GM by ideas not GM not ideas though I can independently look for them but the ratio should be used by me as my design specification is that clear to you GM is W by L1 related so use case ice came with a meal guy okay but ideas so that you get the gain you get the slew rate you get the power dissipation you get every spec which you want to attain to this that is the minimum value which is allowed sorry should be higher than that anything which is higher slew rate I am not this is the minimum value I must think of slew rate is always specified not less than so much the minimum value of slew rate is 40 millivolt micro volt per microsecond okay so is that point there is a designer what is the criteria I am saying GM and ideas ratio is I am adjusting is that clear to you and that decides me almost all specifications so as a designer I keep watching what parameters I should tweak so that I get whatever specification for an amplifier is specified is that so different between analysis and design is clear in analysis we are derived the expressions but we never look back and say why why what should I do now here we just go back and see oh if I change this what will happen if I do this what will happen so I design okay I design only on two such things and I will I will be satisfied before we quit for the day we will solve one problem at least expressions I will give you again since we are now going to even 0.35 is a short channel device but 19 nanometers below is certainly very very short channel device and the current technology of RF and digital is around 45 down so many worries are there but one of the major circuit worries is what I am looking into of course there are variation in mobility because of mobility become functions of fields both the gradual channel approximation is no more valid depletion approximation is also a pseudo approximation VT reduces with reduction in channel lengths please remember higher the channel length it is nearly constant as channel length goes down VT keeps falling then the worry which is most me is the third one which is increase of RS and RD source resistance and drain resistance of the source drain areas as everything shrinks well by a actually increases is that clear because that increases that series resistance of source and drain is one of the major of course there are huge problems in leakage currents but that will see that is that clear so there are of course there are many more short channel effects right now I specified this from the circuit point of view I know even if it reduces I know how much mobility changes I know for that how much so I am not worried too much on them I am designing with base but this something I have not earlier calculated now I may have to see remember mobility and VTs are still difficult values but they will be specified for a node okay so which is not in my hand but I know okay I have to work with these leakage current is also technology dependent of course is circuit dependent also to great extent but in that case at least we are designing from the process itself to minimize the leakage it is something is not here taken care in long channel and this is the only one which I am going to show you please do not think there is no influence of others everyone is influencing badly but the one which I can immediately see my worry is this do you believe short channel device will be better or a long channel device okay the criteria is the linearity because amplifier what is important the linearity do you believe that the short channel device will be more linear or larger linearity than the long channel what is your idea okay the drain resistance anyway adds up to the drain value ro plus something that that small we do not worry too much but if the source side has the resistance this RSX is the source resistance of the M1 and M2 what do they act like source degeneration is that correct great things happen okay so let us do for a normal this device we have done it VGS 1 is VTN plus 2 IDS 1 by beta 1 no RSX used right now but VGA anyway VGS 2 is written this however VGA 1 minus VGS 1 minus IDS RX is the value now this value was not there earlier short channel this value appeared and that of course from the other side VG 2 minus VGS 2 IDS 2 RX now we define a term IODS which is output current difference of output currents IDS 1 minus IDS 2 and which we know is GMV ID okay we know this we are already calculated so what is the measure of linearity whatever is the input current change how much is the output current change if that is better I say yeah we have better linearity if not I will say it is less linearity we want IOD proportionate to I in now so if they are larger than I will say we are better linear is that expression all of you because GMV ID is the current the transistor converts voltage into current so I will see linearity is only coming because of the current available if current reduces that is the VID term we send a range ICMR beyond that is not linear we are looking for where up to which this relation is valid please remember this expression will use often VGS VTN plus under root 2 ID by beta is a very standard way of replacing IDS into VGS or VGS into IDS this is a very standard technique in a long channel device please remember what is non-linearity of IV character IO characteristics or VOVN characteristics is can be done by Taylor Taylor series expansion if I do Taylor series expansion the IODS by ISS if you want you can do read some papers I have just copied from some paper so just check it IODS by ISS VID by VOV see I am plotting the ratio of output current with VID is that trans conductance were clear output is the current input is the voltage so I am just doing that this is current which is actually getting at the output ISS is the normalized current and VOVID is your voltages so IODS by IS is VID by VOV minus half one eighth VID plus higher turns these two are good enough cubic turn is good enough so if you are long channel device this is the expression that okay IOD by ISS VID by VOV minus one eighth VID by VOV cube however in a short channel device what should I replace now this VOV will then become because of the D generation 1 plus GMRS times VOV we have done it earlier and just replacing source D generation value so the new value of VOV will be 1 plus GMRS time VOV RS is the source is this current source resistance minus one eighth of this is now do you see the denominator is increasing in the this since the denominator is cube here and increasing okay short channel case different amplifier with RSX will show you a better linear characteristics than the long channel device what that is true see what is designed if you achieve something you lose something okay but do you get the point this was something which many people did not realize that short channel device everything goes wrong here is something can do good your linearity may improve and that is something why we when a new design I start I should look into whether which technology I am using and what linearity addition I got through that has an advantage on output things because some application may help you in that is that you said now someone said in a last line like that IDRX drop will also reduce GM equivalent so I am not saying that there is no penalty it is a penalty but at the gain of linearity