 Hello and welcome to this presentation of the STM32-L4 Reset and Clock Controller. Please note that this presentation has been written for STM32-L47X48X devices. Key differences with other devices are indicated at the end of the presentation unless otherwise specified. The STM32-L4 Reset and Clock Controller manages system and peripheral clocks. STM32-L4 devices embed three internal oscillators, two oscillators for an external crystal or resonator, and three phase locked loops or PLLs. Many peripherals have their own clock, independent of the system clock. The RCC also manages the various resets present in the device. The STM32-L4 RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication baud rates, and also to keep some peripherals active in low power modes. Finally, the RCC provides safe and flexible reset management. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets, the system reset, the power reset, and the backup domain reset. The peripherals have individual reset control bits. The first type of reset is the system reset, which resets all the registers except certain registers for the reset and clock controller and power controller. It also does not reset the backup domain. The system reset sources are the external reset generated by a low level on the NRST pin, a window watchdog event, an independent watchdog event, a firewall event, a software event through the nested vectored interrupt controller, a low power mode security reset, which is generated when stop, standby, or shutdown mode is entered, but is prohibited by the option byte configuration, an option byte loader reset, and a brownout reset. The reset source flag can be found in the RCC control and status register. Here is the simplified block diagram of the system reset. All internal reset sources provide a reset signal on the NRST pin, which can be used to reset other components of the application board. In addition, no external reset circuitry is needed due to the internal glitch filter and the safe power monitoring feature, which guarantees the reset of the application when VDD is below the selected threshold. The internal pull-up on the NRST pin, which maintains a high level when no reset signal is driven low, is deactivated when an internal reset is driven in order to reduce power consumption under reset. Additionally, all IO pins are placed in analog mode during and after reset to eliminate power consumption through the Schmidt trigger when the IOs are floating under reset and before software initialization. The second type of reset is the power reset. The brownout reset, or BOR, resets all registers except those in the backup domain powered by VBAT, which contains the RTC and the external low speed oscillator. When exiting standby mode, all registers powered by the regulator are reset. When exiting shutdown mode, a brownout reset is generated. The third type of reset is the backup domain reset, which resets the RTC registers, the backup registers, and the RCC backup domain control register. This reset occurs when the BDRST bit is set in the RCC backup domain control register. It also occurs when VDD and VBAT are powered on if both supplies have previously been powered off. The RCC offers a large choice of clock sources, which can be selected depending on low power, accuracy, and performance requirements. STM32L4 devices embed three internal clock sources. A high speed internal 16 MHz RC oscillator, or HSI16, a multi-speed internal RC oscillator, or MSI, and a low speed internal 32 kHz RC oscillator, or LSI. STM32L4 devices embed two oscillators for use with an external crystal or resonator, a high speed external 4 to 48 MHz oscillator, or HSE with a clock security system, and a low speed external 32.768 kHz oscillator, or LSE, also with a clock security system. STM32L4 devices embed three phase locked loops, each with three independent outputs for clocking different peripherals at different frequencies. The system clock can be derived from the high speed internal 16 MHz RC oscillator, or HSI16, the multi-speed internal RC oscillator, or MSI, or the high speed external 4 to 48 MHz oscillator, or HSE. The AHB clock, called HCLK, is derived by dividing the system clock by a programmable prescaler. The APB clocks, called PCLK1 and PCLK2, are generated by dividing the AHB clock by programmable prescalers. The RTC and LCD clock is generated by the low speed external 32.768 kHz oscillator, or LSE, the low speed internal 32 kHz RC oscillator, or LSI, or the HSE divided by 32. The LSE can remain enabled in all low power modes and in VBAT mode. The LSI can remain enabled in all modes except shutdown and VBAT modes. The multi-speed internal oscillator, or MSI, is a configurable oscillator, offering a compromise between ultra-low power and performance. The MSI, which is the system clock used at startup from reset, standby, or shutdown modes, is programmable. It supports 12 ranges from 10 kHz to 48 MHz, selected through the MSI range control bits. The MSI RGSEL bit must be set in order to select the frequency provided by MSI range. The MSI frequency after wake-up from standby mode is configurable between 1, 2, 4, or 8 MHz, through the MSIS range control bits. The frequency after reset or at wake-up from shutdown mode is 4 MHz. The MSI can be selected as a wake-up clock from stop 0, stop 1, or stop 2 modes, and as the backup clock if an HSE failure is detected by the clock's security system. The MSI has 2 modes, normal mode and PLL mode. PLL mode offers an automatic calibration feature with the low-speed external oscillator at 32.768 kHz. The accuracy of PLL mode allows the MSI to be used as a USB full-speed clock in device mode and to be used as a UART peripheral's clocks. The MSI in normal mode is trimmed during production testing and can also be user-trimmed. The high-speed internal oscillator is a 16 MHz RC oscillator, which provides 1% accuracy and fast wake-up times. The HSI-16 is trimmed during production testing and can also be user-trimmed. The HSI-16 can be selected as clock at wake-up from stop 0, stop 1, or stop 2 modes, and as the backup clock if an HSE failure is detected by the clock's security system. The HSI-16 can be automatically awakened when exiting stop mode in order to make it available for peripherals when it is not used as the system clock. This avoids waiting for the HSI-16 to wake up when the system clock is the MSI. The HSI-16 is requested by the I2C and the USART-LPUART peripherals to support wake-up from stop 0, stop 1, or stop 2 modes. HSI-16 is enabled only for the wake-up sequence detection and remains disabled outside of this wake-up sequence. This table compares the HSI-16 and MSI characteristics. The HSI-16 accuracy is better than that of the MSI when not used in PLL mode. In PLL mode, the average MSI accuracy is the LSE accuracy, 32.768 kHz external crystal, resonator, or clock. The MSI power consumption is much lower for the same frequency than the HSI-16 and is only 600 nanoamps at 100 kHz. The HSI-16 offers the fastest wake-up time, only one microsecond. The maximum time needed for the MSI to be stabilized at 1% of final frequency in PLL mode is 1.5 milliseconds. The high-speed external oscillator provides a safe crystal system clock. The HSE supports a 4 to 48 MHz external crystal or ceramic resonator and also an external source in bypass mode. A clock security system allows an automatic detection of HSE failure. In this case, a non-maskable interrupt is generated and a break input can be sent to timers in order to put critical applications such as motor control in a safe state. When an HSE failure is detected, the system clock is automatically switched to an internal oscillator, the HSI-16 or the MSI, so the application software does not stop in case of crystal failure. STM32L4 devices embed an ultra-low power 32 kHz RC oscillator which is available in all modes except shutdown and VBAT. The LSI can be used to clock the RTC, the LCD, the low-power timers and the independent watchdog. The accuracy of the LSI is plus or minus 1.5% over temperature and plus 0.1 minus 0.2% over voltage. The LSI consumption is typically 110 nanoamps. The 32.768 kHz low-speed external oscillator can be used with external quartz or resonator or with an external clock source in bypass mode. The oscillator driving capability is programmable. Four modes are available from ultra-low power mode with a consumption of only 250 nanoamps to high driving mode. The clock security system monitors for failure of the LSI oscillator. In case of failure, the application can switch the RTC clock to the LSI. The CSS is functional in all modes except shutdown and VBAT. It is also functional under reset. The LSI can be used to clock the RTC, the LCD, the use-arts or low-power UART peripherals and the low-power timers. STM32L4 devices embed three phase-locked loops, each with three independent outputs. The input clock of the PLL can be selected between HSI16, MSI and HSE. The main PLL can provide the system clock. Then the different PLL outputs can be used for the two serial audio interfaces, ADC interface, USB, random number generator and SDMMC peripherals. Here is a configuration example where the first PLL is configured to generate the 80 MHz system clock. The second PLL, PLLSAI1, is used to provide the 11.29 MHz audio clock used to generate a sample frequency sub-multiple of 44.1 kHz and to provide the 48 MHz USB clock. The third PLL, PLLSAI2, is used to provide the 49.14 MHz audio clock used to generate a sample frequency sub-multiple of 192 kHz. The system clock is selected between the HSI16, HSE, MSI and PLL output. The maximum system clock frequency is 80 MHz. The APB1 and APB2 bus frequencies are also up to 80 MHz. The maximum clock source frequency depends on the voltage scaling and power mode. The system clock is limited to 80 MHz in range 1, 26 MHz in range 2 and 2 MHz in low-power run, low-power sleep modes. The clock tree is shown here. The AHB clock is generated from the system clock divided by the AHB prescalar from 1 to 512. The AHB clock feeds the CPU, DMA, memories and AHB peripherals. The two APB clocks are derived from the AHB clock divided by the APB1 prescalar and the APB2 prescalar each from 1 to 16. Several peripherals have their own clock independent from the system clock. This is the case for the USARTs, low-power UART, I2Cs, low-power timers, single-wire protocol master interface, ADC interface, serial audio interfaces, USB, random number generator and SDMMC interface. All of these clocks can be selected from the internal or external oscillators. The various clocks can be output on an I.O. The microcontroller clock output feature allows you to output on a pin of one of these seven clocks. GSI 16, HSE, MSI, LSI, LSE, SYSCLK and PLLCLK. The low-speed clock output feature allows you to output on a pin the LSI or LSE clock. The low-speed clock output is available in stop 0, stop 1, stop 2, standby and shutdown modes. The dynamic power consumption can be optimized by using peripheral clock gating. Each peripheral clock can be gated on or off in run and low-power run modes, except SRAM 1 and SRAM 2, which are always clocked in run and low-power run modes. By default, the peripheral's clock is disabled, except the flash clock, which is enabled by default. When a peripheral's clock is disabled, the peripheral's registers cannot be read or written. Other registers allow for configuring the peripheral's clock during the sleep and low-power sleep modes. This also affects stop 0, stop 1 and stop 2 modes for peripherals with an independent clock active in stop modes. These control bits have no effect if the corresponding peripheral clock enable is cleared. By default, the SRAM 1 and SRAM 2 clocks are enabled in sleep and low-power sleep modes. If they are not needed, the SRAM clock enable bit should be disabled to reduce power consumption. This slide lists the RCC interrupts. The LSE and HSE clock security systems, the PLL ready and all five oscillator ready signals can generate and interrupt. In addition to this training, you may find the power control and interrupt controller training is useful. For more details, please refer to application note AN2867, an oscillator design guide for STM8S, STM8A and STM32 microcontrollers, and application note AN4736, which explains how to calibrate STM32L4 internal RC oscillators. This slide presents the key differences between baseline STM32L47X48X devices and other devices. The features listed below are not implemented in STM32L47X48X devices. A new HSI48 internal oscillator is now available, allowing a crystal-less solution when coupled with the new clock recovery system or CRS. The HSI48 clock can be output on the MCO pin. On the audio side, the HSI16 is now a possible input to SAI peripherals, and the PLLP division factor has been extended to the range 2 through 31 in order to allow more flexibility on the SAI input clock frequency.