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Published on Feb 22, 2008
Google Tech Talks February, 21 2008
It is will be too costly to design many of these chips at the polygon or even gate level, so they must be highly programmable. Furthermore, they should not just be FPGAs as we now know them because with that many transistors, we should specialize more for power efficiency. I envision FPGA-like chips where the computational elements combine CPUs with more traditional FPGA-like fabrics.
For embedded real-time applications, which I argue will dominate, I argue that the temporal behavior of these processors should be as easy to analyze and control as their functional behavior.
I present a vision such a precision-timed (PRET) processor, which incorporates a variety of techniques. At the ISA level, it provides cycle-accurate timers, a predictable memory hierarchy based on scratchpad memories, and an interleaved pipeline that provides predictable, hardware-efficient concurrency. It will be programmed in a C-like language that includes user-specified timing constraints and concurrency, perhaps with synchronous semantics. Both compile- and run-time checks will ensure the program meets timing constraints, similar to array bounds checking.
Speaker: Stephen A. Edwards Stephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992, and the M.S. and Ph.D degrees, also in Electrical Engineering, from the University of California, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York, which he joined in 2001 after a three-year stint with Synopsys, Inc., in Mountain View, California. His research interests include embedded system design, domain-specific languages, and compilers.