 Hello and welcome to this presentation of the STM32 Inter-Processor Communication Controller or IPCC module. It covers the main features of the module, which is used to signal message exchange between CPUs. The Inter-Processor Communication Controller module integrated inside STM32 products provides interrupt signaling, allowing microcontrollers to exchange messages in a non-blocking way. This module allows for simplex communication where a dedicated channel is used to send a message from processor A to processor B. It also allows for half-duplex or message response communication using a single shared channel to communicate between processor A and processor B. Applications benefit from non-blocking interrupt-based message exchanges and channel flow control. The Inter-Processor Communication Controller is able to wake up a CPU from C-sleep, C-stop and C-standby modes. The channel data location is not part of the Inter-Processor Communication Controller and is stored in shared memory. The Inter-Processor Communication Controller is an AHB slave module. It consists of an AHB interface containing the registers and an interrupt management part. Each channel has a single status flag to indicate the send status for one CPU and the receive status for the other CPU. Each CPU has its own status mask and set or clear register bit for each channel. The register area is split into two regions, one per CPU. Each region contains the registers associated with the CPU, preventing read, modify, write, access conflicts. Dedicated interrupts are provided for each CPU. A channel is associated with a direction from a sending CPU to a receiving CPU. The sending CPU can signal a channel to be occupied by setting the channel status to occupied using its set Channel N register bit or CHNS. If the receiving CPU has unmasked its channel occupied interrupt in its channel N occupied mask register bit or CHNOM, an RX occupied interrupt or message available is generated for the receiving CPU. The receiving CPU can signal a channel to be free by setting the channel status to free using its clear channel N register bit or CHNC. If the sending CPU has unmasked its channel free interrupt in its channel N free mask register bit or CHNFM, a TX free interrupt or flow on is generated for the sending CPU. The simplex procedure allows the transfer of a message from a sending side to a receiving side via a dedicated channel. To transmit a message using the simplex procedure, the channel status flag is checked. When the channel status flag indicates channel occupied or flow off, in other words, due to the receiving side not having freed the channel data buffer from a previous message, the channel free interrupt is unmasked. Once the channel is freed by the receiving side, a channel free interrupt or flow on is generated. When the channel free interrupt is generated, the channel free interrupt is masked and the message can be written in the channel data buffer. Subsequently, the channel status flag is set to occupied, which triggers a channel occupied interrupt for the receiving side. When the channel status flag is checked to be free, a message can be directly written in the channel data buffer. When a channel occupied interrupt is generated, the receiving side determines which channel is occupied and masks the appropriate channel occupied interrupt. Subsequently, the message can be read from the channel data buffer. Once read, the channel status flag is cleared to free or flow on and the channel occupied interrupt is unmasked. The half duplex procedure allows the transfer of a message from a sending side to a receiving side, followed by a response sent from the receiving side back to the sending side using a single shared buffer. In the half duplex procedure, the sending side will first check the channel status flag. If the channel status flag indicates the channel is occupied or flow off, in other words, due to the receiving side not yet having sent a response to a previous message, the sending side waits for the response, a software flag. When the channel is free, the message can be written in the channel data buffer. Subsequently, the channel status flag is set to occupied, which triggers a channel occupied interrupt for the receiving side and the channel free interrupt is masked. The channel free interrupt indicates the availability of the response sent by the receiving side. When a channel free interrupt or response ready is generated, the sending side determines which channel is freed and masks the corresponding channel free interrupt. Subsequently, the response can be read from the channel data buffer. When a channel occupied interrupt or message available is generated, the receiving side determines which channel is occupied and masks the corresponding channel occupied interrupt. Subsequently, the message can be read from the channel data buffer. The channel will only be freed once the receiving side has sent the response to the channel data buffer. Once the response is received in the channel data buffer, the channel status flag is cleared to free or response ready and the channel occupied interrupt is then unmasked. Here is an overview of the inter-processor communication controller interrupt. Each CPU has a TX free interrupt associated to its own sending channel. Each CPU has an RX occupied interrupt associated to the sending CPU channel. Here is an overview of the peripheral status at specific low power configuration modes. The inter-processor communication controller is not able to change states in sleep and stop modes. In standby mode, the inter-processor communication controller content is lost. The inter-processor communication controller will be in run mode whenever a CPU is in run mode. The inter-processor communication controller is able to interrupt and wake up a CPU in C run, C sleep and C stop modes. Here is a list of peripherals related to the inter-processor communication controller module. Users should be familiar with all the relationships between these peripherals to correctly configure and use the inter-processor communication controller module.