 This time we're going to be looking at clock cycle time and latency. We've already looked a little bit at what our clock actually is and what the clock cycle is. But now we're going to look at what it actually means for our processor. As the owner of a computer, you probably know you'd like your clock to be fast. It's nice when you have a high clock speed because it feels like your computer can get lots of work done very quickly. But our clock is actually related to how much work our hardware has to do. So in our single cycle processor, we have to be sure that we can complete every instruction within one cycle. Our hardware is just designed in such a way that it expects to write everything back to registers, the program counter, the data memory at the end of the cycle. And it can only get new data at the beginning of a new cycle. So our processor can get new data at the beginning of the cycle and write its results back at the end of the cycle. But it can't really do those in between. So we're going to have to make sure that our clock cycle time is long enough to accommodate any of the instructions that we've got. We'll be interested in seeing how much time any of our instructions require. And then we're basically just going to say whichever instruction takes the most amount of time is the one that we're going to base our clock cycle around. It turns out in general, that's going to be our load word instruction. This is because the load word instruction goes through all of the really, really complex stuff in the main workflow. No other instruction goes through all of those elements. If we look at our arithmetic instructions, they'll leave out the data memory. If we look at our store word instruction, it gets the data memory, but it doesn't write anything back to the registers. Those branch and chump instructions are just a whole lot cheaper. Even though they use some of this hardware up here, the branch and chump instructions are not going to be nearly as expensive as accessing memory and the registers again. So our clock cycle time is going to be limited by how long it takes a load word instruction to complete. So if we know how long the critical path for our load word instruction takes, then we know how long we have to set our clock cycle to. The latency for an instruction is how long it takes a single instruction to complete. In our single cycle architecture, it turns out that's the same as the clock time. In this case, every instruction takes one clock cycle to complete, so the amount of time it takes an instruction to complete is one clock cycle. However long that one clock cycle is. This will get a little more complex when we start looking at a multi-cycle architecture, but we can also have a much more complex architecture that has much more variation in the latency times.