 Hello, I am Mr. S.S. Shakapure, assistant professor, department of computer science and engineering, Valchand Institute of Technology, Soilapur. My today's topic is features and PIN diagram of DMA controller and the IC is 8257. And my learning outcome at the end of this session to understand concepts of direct memory access controller, how to initiate and DMA cycle and their use in a microprocessor based system. If you are looking the DMA controller, it's a 40 PIN IC package. It allows devices to transfer data without subjecting the processor a heavy overhead. Otherwise, the processor would have to copy each piece of data from the source to the destination. So, without any interference here, with the use of this particular IC, we can transfer heavy overloaded data from source to destination is what our main functioning behind using this particular PIN IC package. Now, one by one, we will check it out the function of particular PIN in this IC about the PIN number 1, IOR, it is active load tri-state buffered by directional input line. And in the slave mode, it functions as a input line. IOR signal is generated by microprocessor to read all the contents 8257 registers. And in the master mode, it functions as output line. The same way about the IOW, it's a PIN number 2. It is active load tri-state buffered by directional control line. In the slave mode, it functions as a input line. IOR signal is generated by the microprocessor to write the contents 8257 registers. In the master mode, it functions as output line. IOR signal is generated by 8257 during read cycle. And about the next two more PINs, MEMR and MEMW. So, MEMR, it is the low memory read signal, which is used to read the data from the address the memory location during DMA read cycle. Same way, it is the MEMW is the active low signal, which is used to write the data to the address the memory location during DMA write operation. Now, about the next PIN mark, it is a modulo 128 mark output line. It indicates the current DMA cycle is the 128th cycle. It goes high after transferring every 128 bytes of the data block. In the next PIN ready, it is an asynchronous input line. It is an active high asynchronous input signal, which makes DMA ready by inserting wait state. About the next PIN, HLDA, it is acknowledgement signal from microprocessor, which indicates the DMA controller that the bus has been gained to the requesting peripherals by the CPU. And this is actually an acknowledgement of hold signals requesting generated from the peripherals. About the next PIN ADSTB address row, it is a control output line. This signal is used to convert the higher byte of the memory address generated by the DMA controller into the latches. And in the next PIN address enable, it is a control output line. It is used to isolate the system address, data and control lines. Actually, it is a register. This register is have the very specific function. It demultiplex the address and data line. The next is HRQ. This signal is used to receive the hold request signal from the output device. And in the slave mode, it is connected with a DRQ input line of 8257. And in master mode, it connected with the hold input of the CPU. The next one is CS. It is an active low-cheap select input line. In the slave mode, it enables the read-write operation from 8257. In the master mode, it disables the read-write operation from 8257. About the clock, it is a clock frequency signal which is required for the internal operation of 8257. And about the next PIN from 13 reset is used to clear modes at register and status register. So we have the special two operating mode registers. And these registers, if you want to clear, then use to go with the reset. Now we have the next four different very useful signals that is a DAC-K0 to DAC-K3. And these are the active low-DMA acknowledge lines which updates the requesting peripherals about the status of their request by the CPU. These lines can also act as strobe lines for the requesting devices. Now about the DR-Q0 to DR-Q3, these are the four individual channel DMA request inputs which are used by the peripheral devices by using DMA services. Then the fixed priority mode is selected, the DR-Q0 has the highest priority and DR-Q3 is the lowest priority among them. So in this particular side, we are going to check the data line from D0 to D7. It is a bidirectional tri-state buffered multiplexed data and address. In the slave mode, it is a bidirectional and in the master mode, it is a unidirectional. So bidirectional is behave like a data bus and in the unidirectional, it behave like a address bus. So now in the address line from A0 to A3, these are the four least significant address lines. In the slave mode, they act as an input which selects one of the registers to be read or written. In the master mode, they are the four least significant memory address output lines generated by A257. And the next higher 4-bit Nibble, A4 to A7, these are the higher Nibble of the lower byte address generated by DMA only in the master mode. Our one more last pin that is from 36TC, terminal count stands, terminal count which indicates the present DMA cycle to the present peripheral devices. So I have a question, think and write. Question is the pin that request the access of the system buses. You have the four options HLDA, HRQ, ADS, TB and enough. And your answer is, see the whole request output requests the access of the system bus. Now I am coming to the point features of A257. Here is a list of some of the prominent features of A257. The very first one is it has four channels which can be used over four IO devices. And each channel has 16-bit address and 14-bit counter. And each channel can transfer up to 64 kb of data. And each channel can be programmed independently. The next one, each channel can perform read transfer, write transfer and verify transfer operations. It generates mark signal to the peripheral devices that 128 bytes have been transferred. It requires a single phase clock, its frequency ranges from 250 Hz to 3 MHz. And it operates in two modes that are master mode and slave mode. In the summary section, the DMA controller are normally used in high performance devices where large bulk shop data need to be transferred from the input to the memory. And these are what my references are used for my this particular discussion. Thank you.