 This time we're going to be building a D latch. A D latch is similar to an SR latch in that it will hold data, but it also gives us the ability to control when we update our latch. Our D latch is actually going to be based off of our SR latches. So we're going to be looking at two different types of D latches. One will use the basic SR latch with its NOR gates. The other will use the negation SR latch with its NAND gates. We'll go through and we'll fashion two D latches, one made from each of these different types of SR latches. We'll see how they work and how you can control them. I will start with the SR latch with its cross-coupled NOR gates. So there is our basic SR latch. So you'll remember that our SR latch really only holds one bit of data. We only have one bit of actual data come in. The other input that we're going to have to our D latch will be the control signal. Something telling us whether we'd like to actually store the data or not. So I will have a data line over here and a control line. For this D latch, we're just going to use a couple of AND gates to determine when we update the SR latch. When our data comes in, if it's a 1, then we'd like to set our SR latch. If it's a 0, then we want to reset it. So when it's 1, we want the 1 to come in on the set line. When it's 0, then we'd like to put a 1 on the reset line and 0 on the set line. I'm going to just pipe the data directly to the first AND gate on the top. If I'm interested in resetting, then I'd want the negation of my data. My data would be 0, so the negation of 0 would be 1, and then I could potentially have a 1 on the reset line. My control signal, though, will just get fed directly to both of those AND gates. That way I can say, if I want to update my SR latch, then I can do so. But the D latch will only update if the control signal is 1. So I'll start by putting some numbers into this thing. I will say that my output state is currently 0, means that this be 1. So now everything else should not matter too much. It's not terribly important what's coming out of the AND gates at the moment, as long as we know that it's not changing the state of the SR latch. So we'd probably have a 1 there and a 0 over there as well. So I'm going to start with the case where our control signal is 0 and my data is 1. So this data is different from what's coming out, but my control signal is 0. So I should expect that when this goes through that the state of my system will stay the same. So my first AND gate sees 1 and 0. So that gives it 0. That doesn't change. Second AND gate sees not 1, which is 0 and 0. So 0 and 0 gives it 0. On this side I have 0, nor 0, which gives me 1. Then I have 1 or 0 gives me 1, but not 1 is 0. So my SR latch did not change, still producing 0 as the actual output. Now if I change my control signal to be 1, now I've got 1 and 1, which is 1. Then I've got not 1, which is 0. 0 and 1 is still 0. On this side I've got 1 or 0 gives me 1, not 1 will be 0. Then I'd have 1 or 0 would give me 1, not 1 would be 0. Now I'd feed both of my two 0s back around. I'd get 1 or 0 gives me 1, not 1 is 0. And 0 or 0 is 0, not 0 gives me 1. Feeding the 1 back through gives me 1 or 1 is 1, not 1 is 0. So now it's reached a stable state where my data has been stored, and it's actually being pushed out as well. But that only happened when I changed the control signal to be 1. When it was 0, it didn't update. So I'm going to try changing the data to 0 this time and the control signal back to 0. If it works the same way it did before, then the state of our delat shouldn't change. So here I'm getting 0 and 0, well that's 0. Down here I've got not 0, which is 1. 1 and 0 still gives me 0. So 0 or 1 is 1, not 1 is 0. 0 or 0 is 0, not 0 is 1. So we changed what was coming out of the top AND gate, but it didn't affect the SR latch. Now if I change my control signal to 1, now I've got 0 and 1 gives me 0. Down here I've got not 0, which is 1, and 1 gives me 1. For my SR latch, 0 or 1 gives me 1, not 1 is 0. 0 or 1 is 1, not 1 gives me 0. Those come back around. I have 0 or 0 is 0, not 0 is 1. And then 0 or 1 is 1, not 1 is 0. And then even when this 1 comes around we get 1 or 1 is 1, not 1 is 0. So when we use the SR latch with NOR gates, we only need to add a couple of AND gates, and they're relatively straightforward. We can control how it works pretty easily. We set our control signal to 1 when we want to update, and then it just takes the data or not. When we're working with the negation SR latch, it will be a little bit different. I'll start by drawing our negation SR latch. This time we're going to use a couple of NAND gates to control how this works. And again these will just feed directly into our negation SR latch. These are just here to control when our SR latch actually updates. This time our circuit is going to be connected a little oddly. It turns out that our top NAND gate will be connected to the bottom NAND gate. We will feed our data into the top NAND gate. Then the cross coupling will allow that data to be fed down to the bottom NAND gate if needed. But our control signal will be fed to both of the NAND gates. Start by initializing our circuit. For we had 0 as our result, so that would mean we would have a 1 coming out of this line. We need to have a 1 there, and we'd probably have a 1 down there. Because the circuit is stable when both of its inputs are 1. So we'll start by looking at the same sorts of inputs we had with the other D latch. Started with a data of 1 and a control signal of 0. So here we have 1 and 0 is 0, not 0 is 1. So that part doesn't change. Down here have 1 and 0 is 0, not 0 is 1. So in this case, our inputs matched up with what we already had inside our circuit, so nothing changed. I'll go ahead and change the control signal to 1. Hopefully this will change the output to 1. So now I have 1 and 1 is 1, but not 1 is 0. Down here I have 0 and 1 is 0, not 0 is 1. So now I have 0 and 1 is 0, not 0 becomes 1. So our output is 1. And over here I had 0 and 1 is 0, not 0 is 1. Once this updates to 1, then we get 1 and 1 gives me 1, not 1 is 0. So once we set the control signal to 1, it updated our output to 1. You can also notice with the sr latch, we had to have the negation of set or the negation of reset to control how the latch worked. Over here we're just able to talk about data. We don't have to talk about the negation of our data anymore. So now I'll go ahead and change the data back to 0 and our control signal back to 0. Now I get 0 and 0 is 0, so not 0 is 1. 1 and 0 is 0, not 0 is 1. Now we have 1 and 1 going into our negation sr latch, so this part won't change. 1 and 0 is 0, not 0 is 1. 1 and 1 is 1, so not 1 is 0. But when I change my control signal back to 1, then I've got 0 and 1 is 0, not 0 is 1. Then 1 and 1 is 1, not 1 is 0. Now I've got 0 and 1 gives me 0, not 0 is 1. Got 1 and 0 is 0, not 0 is 1. Feed both of those back around, I've got 1 and 1 is 1, not 1 is 0. And 1 and 0 is 0, not 0 is 1. This 0 finally makes it around 0 and 0 is 0, not 0 is 1. So in both cases, the delatch only updates when our control signal is set to 1. When it's set to 0, then it just maintains its previous state. And whenever we do set the control signal to 1, then they take the data in. They just store the data inside the SR latch, whichever one you're using. Both of these work. Chances are using the cross-couple nor gate seems a little easier than the NAND gates with its odd wiring. But both of them work. You could use either one of these to hold one bit of data.