 Welcome to this presentation of the STM32 Direct Memory Access Controller, or DMA. It covers the main features of this module, which is widely used to handle the STM32 peripheral data transfers. The two identical instances of Direct Memory Access, named DMA1 and DMA2 embedded on the STM32 MP1 series, are used to provide high-speed data transfers between peripherals and the memory and between memory and memory. Data can be quickly moved by the DMA without any CPU action. This keeps CPU resources free for other operations. The DMA controller combines a powerful dual-AHB master bus architecture with an independent FIFO to optimize the system's bandwidth, based on a complex bus matrix architecture. The two DMA controllers, DMA1 and DMA2, have 16 streams in total, each dedicated to managing memory access requests from many peripherals. Each stream has flexible hardware requests and support for software triggers. The stream software priority is programmable, and a hardware priority is used in case of equality. Streams are independently configurable. Each stream has its own data format, increment type, and data address for both source and destination. A forward FIFO per stream allows performing of data packing and unpacking and burst transfers. Independent stream interrupt flags allow triggering of half transfer, transfer complete, and transfer error events. In case of a transfer error, the faulty stream is automatically disabled without any impact on the other active DMA streams. For each stream, the source and destination data size format is independently configurable for 8, 16, or 32-bit packets. The transfer type for the source and the destination can be independently programmed in single mode or burst mode. The source and destination addresses and pointer increment are also independently configurable. The transfer data size can be pre-programmed up to 65, 535. Circular buffer mode is available to support a continuous flow of data. The source and the destination addresses and the number of data to be transferred are automatically reloaded after the complete transfer. Double buffer mode allows the switching between two memory buffers to be managed by hardware. Memory to memory mode allows transfers from one address location to another without a hardware request. Once the stream is configured and enabled, the transfer starts immediately. When data is transferred to or from a peripheral, the hardware request coming from the selected peripheral is used to trigger the data transfer on DMA peripheral port. Once the transfer is completed, the request is acknowledged. When FIFO mode is enabled, direct mode disabled, the DMA controller manages the data format difference between source and destination, or data packing and unpacking. Thanks to its internal FIFO, the DMA stream can reduce software overhead and the number of transactions over the AHV bus. In single mode or burst mode, the FIFO threshold level determines when the data in the FIFO should be transferred to and from memory. There are four configurable threshold levels per stream starting from one quarter FIFO full to FIFO full. Depending on the transfer direction on the memory port, when the FIFO threshold is reached, the FIFO is filled from or flushed to the memory location. Burst mode is only available when FIFO mode is enabled. When setting burst mode, the FIFO threshold should be compatible with burst size. It allows the DMA streams to have the burst data available in the FIFO to carry out a burst transfer. DMA controllers support circular mode allowing you to configure the number of data items to transfer once and automatically restart the transfer after a transfer complete event. Double buffer mode is only available in circular mode. It allows you to switch automatically by hardware between two memory addresses each time a transfer complete event occurs. In double buffer mode, a status flag and control bit or CT is available to monitor which destination is being used for data transfers. The DMA controller provides access to eight streams with up to 115 channels or requests per stream. Each of the eight streams are connected to dedicated hardware DMA channels or requests. The priorities between the DMA stream requests are software programmable. Four levels consisting of very high, high, medium and low or hardware in case of equality. Request zero has priority over request one, etc. Each DMA controller stream request can be connected to DMA requests from up to 115 possible peripherals by the DMA request router or DMA MUX. This selection is software configurable and allows a great number of peripherals to initiate DMA requests. Each stream also supports software trigger for memory to memory transfers. Each DMA stream is designed with this group of interrupt events. The half transfer interrupt flag is set when half the data has been transferred. The transfer complete flag is set when the transfer is complete. The transfer error flag is set when an error occurs during the data transfer. The FIFO error flag is set whenever a DMA FIFO underrun or overrun condition is detected or due to threshold burst size incompatibility. The direct mode error flag is set in peripheral to memory mode in direct mode when memory incrementation is disabled. It indicates that new data is being transferred to a memory location whereas the previous transfer is not yet complete. You can refer to training slides related to the DMA request multiplexer or DMA MUX and master direct memory access or MDMA peripherals for additional information.