 Assalam-u-Alaikum students, I am Wasimi Kram. This is the 14th lecture in a series of 45 lectures on digital logic design. I hope you are well. In the last lecture, we talked about combinational logic. We saw how you can make combinational circuits. We will talk more about it today. But before we start with combinational logic, let us quickly revise the topics which we did in the last lecture. In the last lecture, we started our discussion by looking at the Quinn-McLuskey method. We, in fact, used the method to simplify the expression representing the odd prime number generator circuit. The number of variables in that particular circuit were, if you remember, 5. So we could not use the Carnoff map. Therefore, Quinn-McLuskey method was used. The next topic which we discussed was the implementation of combinational logic. Basically, you combine different gates to form a circuit, which is known as a combinational logic circuit. We mentioned that the combinational logic circuit is based on two forms of Boolean expressions, sum of product form and the product of sum form. So basically, the combinational logic circuit, which you would implement, it would, of course, be based on either the sum of product form or the product of sum form. The circuit, which would be required, would be a combination of or and gates or and or gates. We also talked about the steps which are required to implement a circuit. So we mentioned that, first of all, you have to come up with the function table or the truth table of the circuit. So you need to have a truth table. After that, you can directly implement the circuit by looking at the main terms or the max terms. But the circuit, which we obtain by directly implementing it from the function table would be quite large. It would be using too many gates. So disadvantages, we said that the power will be required. Its size will be increased, gates will be increased, costs will be increased. So the appropriate step would be to simplify the expressions. You have the function table. You use the Karnaugh map. You have a method in Matlesky. You use it if there are more variables. You come up with a simple expression. The expression can be in any form. The sum of product form can be used. The product of sum form can be used. After that, you can directly implement the expressions using logic gates. So you would have a simpler circuit, which of course, works. We also saw alternate implementations. If you have a circuit, you can implement the same circuit using all NAND gates or all NOR gates. So these circuits, too, work in that. Then we did an example. Adjacent 1's circuit, which we did an example of. We implemented it in the form of product form, or product of some form. Both types of circuits work perfectly well. Now to have a look at the operation of any circuit, basically, we use the timing diagrams. So many adjacent 1's detector circuit, to see its operation, we drew some timing diagrams, just name input supply, output. So you can, of course, use timing diagram to view the operation of any logic circuit. Then we talked about active high or active low outputs, active high and active low inputs. Conventionally, up till now, we have been saying that the output of a circuit, any logic circuit is 0. Whenever the output is active, the output is set to 1. Similarly, the inputs, the active inputs are treated as 1's, inactive inputs are treated as 0's. Well, this is not the case. You could have a logic circuit, which could have an active output determined by a logic 0 value or logic low. So it could have active low output. Similarly, it could have an active low input. The last topic, which we discussed in the last lecture, was implementing a circuit for an odd parity generator. So odd parity generator such discussion at the bar is to start. Just to remind you what an odd parity generator is, basically, when you send or transmit data from one end to the other end, there are chances that some bits get corrupted. So you use a parity bit to determine an error or detect an error. So yeh ju example hum karenge, is main hum use karenge 4-bit data. So 4-bit data meh agar koi error aaj hai, kase determine karenge, we would append a parity bit. Hum odd parity bit append karenge. So how would you append the parity bit? Basically, hu 1 honna chahiye, value nya 0 honi chahiye. Basically, you would have to design a circuit, which looks at the 4 bits of the data value. And then, of course, it determines if the parity should be 1 or 0. Once you determine the parity bit, you just combine it, connect it, append it to the 4-bit data, and send the 5-bit information to the other end. So pishitavar meh baat ki thi ke jo odd parity generator circuit hai uske li pala function diagram hanayenge a uske baat pehre expressions likhenge, or pehre ultimately circuit koi implement karenge. So let us have a look at the different steps. The function table represents the 16 possible combinations of 4 data bits. The 4 data bits are represented by variables d3, d2, d1, and d0. The output p represents the state of the parity bit. Since odd parity is being used, therefore, the 4-bit data and the parity bit should add up to give odd numbers of 1s. The function table shows the parity bit set to 1 when the 16 4-bit data input combinations have no 1s or an even number of 1s. The information in the function table is mapped directly to a 4-variable Carnoff map to simplify the Boolean expression represented by the odd parity generator function. None of the 1s mapped in the Carnoff map are adjacent to each other. Thus, the function mapped to the Carnoff map cannot be simplified. However, using the rules of Boolean algebra, applying De Morgan's theorem and knowing the function table of exclusive or and exclusive nor gates, the Boolean expression can be simplified. Let's have a look at the simplification of the Boolean expression representing the odd parity function. The expression for the sake of simplification is represented in terms of variables A, B, C, and D instead of D3, D2, D1, and D0 respectively. The expression can be rewritten in terms of common product terms A bar, B bar, A bar B, AB, and AB bar. And some product terms and some of product terms C bar, D bar plus CD and C bar D plus CD bar. The expression can be further represented in terms of sum of product terms as C bar, D bar plus CD, A bar, B bar plus AB, C bar D plus CD bar, and A bar B plus AB bar. The four sum of product terms represent C exclusive nor D, A exclusive nor B, C exclusive or D, and A exclusive or B. The expression is seen in terms of x and y simplifies to A exclusive or B exclusive nor with C exclusive or D. Thus, the original eight-min term expression is implemented using two exclusive or and a single exclusive nor gate as shown in the diagram. Now, let us have a look at the timing diagram of the odd parity generator circuit. And let's see if it verifies the operation of the odd parity generator circuit. The A, B, C, and D timing diagrams represent the changing 4-bit data values. During time interval t0, the 4-bit data value is 0, 0, 0, 0. During time interval t1, the data value changes to 0, 0, 0, 1. Similarly, during time intervals t2, t3, t4, up to t8, the data values change to 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, and 1, 0, 0, 0, 0 respectively. During interval t0, the output of the two exclusive or gates is 0, 0. Therefore, the output of the exclusive nor gate is 1. At interval t1, the outputs of the two exclusive or gates is 1, 0. Therefore, the output of the exclusive nor gate is 0. The output p can similarly be traced for intervals t2 to t8. If you compare the timing diagram p for intervals t0 to t8 with the values of p in the function table, you would find that they are similar, they are in fact identical. So, this verifies that the odd parity generator circuit is working. We have looked at the operation of the odd parity generator circuit. In fact, we verified its operation by using the timing diagram. To implement the odd parity generator circuit, we have used exclusive or gates and exclusive nor gates. Basically, if you do not use these exclusive or and exclusive nor gates, then you can still implement the circuit using a combination of AND gates, OR gates and inverters. But exclusive OR gates and exclusive NOR gates reduce the size of the circuit, they simplify the circuit. So, what in fact are the exclusive OR gates and exclusive NOR gates? Basically they are functional gates, these gates perform a function. What is the function? Let us discuss that. Exclusive OR gate basically detects dissimilar inputs. So, let us suppose you have a two input exclusive OR gate, you have the combination 0 0, 0 1, 1 0 and 1 1. Now, for the combinations 0 1 and 1 0, the outputs are 1 and 1. For the combinations 0 0 and 1 1, the outputs are 0. So, basically, whenever the input, though no input is different, the output is 1. So, if you look at the NOR gate, those are the input combinations. Exclusive NOR case, when input combination is 0 0 or 1 1, the output is 1. So, basically, exclusive NOR detects similar inputs. Now, how would you implement this function? Basically, exclusive OR or exclusive NOR is a simple function performing, detecting similar inputs or dissimilar inputs. So, in Kogarap circuit, in combination circuit benign, those may you would require a combination of OR gate and gates and inverters. Now, since this particular function is very commonly used in logic design, different circuits use these type of functions. So, instead of you having to implement exclusive OR function and exclusive NOR function by combining these different gates, you can use an exclusive OR gate, in fact, or exclusive OR gate available in the form of IC chips. Now, exclusive OR gate and exclusive NOR gate are examples of simple functional devices. When you are working with digital logic design, when you are implementing different circuits, you would be implementing different circuits which are used routinely. For example, adder circuit, comparator circuit, again different logic circuits use the comparator circuit. Similarly, odd parity generator circuit, again different combination circuits would be using the odd parity generator circuit. Now, if you are going to be designing such circuits, then you do not need to design the odd parity generator circuit or the adder circuit or the comparator circuit. In fact, you can find integrated circuits which implement these functions. So, such combination circuits are known as combinational devices or functional devices. Now, as I said, the most common functional device which is used is the adder. So, let us start our discussion with the adder circuit. Let us start our discussion with adders. Now, in digital logic, you can implement adders, of course, which add two different numbers. Now, let me pose a question. If you have to add two numbers and both numbers are of one bit each, how many input bits would you require for the adder and how many output bits would you require for the adder? Basically, you are adding two single bit numbers. So, the input to the adder circuit should be two bits to represent the two numbers. Outputs, because if you just remember, when you add one and one, the answer is the sum is zero and the carry is generated. So, for a single bit adder, you would require a sum output and a carry output. Now, when you connect different adders together, then of course, they add the two numbers as well as the carry borrowed from the previous number, previous two numbers. So, your adder circuit should have a third input. So, it should have the two bits to represent the two numbers as well as the carry in. It should have two outputs, the carry out and the sum out. Now, in combinational logic terminology, there are two types of adders, a half adder and a full adder. The half adder does not have the carry in input, whereas the full adder has the carry in input. So, basically, let us have a look at the functional diagram of a half adder and a full adder and let us see how we represent the two adders symbolically. The diagrams represent a full adder and a half adder. A single bit binary adder circuit basically adds two bits and a carry bit, generated by the addition of least significant bits. The output of the single bit adder circuit generates a sum bit and a carry bit. An adder circuit that only has two bit input representing the two single bit numbers a and b and does not have the carry bit input from the least significant digits is regarded as a half adder. An adder circuit that has three inputs, two bits representing the two single bit numbers a and b and the third bit representing the carry in bit is regarded as a full adder. We have looked at the block diagrams representing the half adder and the full adder. Let us start our discussion with the half adder. How would we implement a half adder? Let us first look, let us first have a look at the function diagram of a half adder. Now as we have seen, the half adder has two inputs a and b. So, two inputs ke saath function diagram me, function table me, kitne columns ong ye, do columns ong ye, representing the two numbers, two single bit numbers a and b. How many input combinations? Basically four combinations 0 0, 0 1, 1 0 and 1 1. Outputs kitne ong ye is function table me, basically do ong ye, ek jo column hain, it would represent the sum output and the other column would represent the carry output. Now let us first have a look at the sum output column. Now sum column me, kab one hoga basically when the input is 0 0, the output is the sum is 0. When the input is 0 1, the sum output is 1. When the input is 1 0, the sum output is 1 and when the inputs are 1 and 1, the sum is 0. So basically if you look at the sum column, the function represented by the sum column is equivalent to the exclusive OR gate function. So exclusive OR gate kager function am dekhain wo be ye kam karay jo sum output aapko there a. So the sum output can be easily implemented using an exclusive OR gate. The two inputs a and b would of course, be connected to the input of the exclusive OR gate. Let us have a look at the carry out of the function, the carry out column of the function table. Basically carry out, kab generate hora when both the inputs are 1s for all other input combinations the carry output is 0. So what is the Boolean expression representing the carry out function? Basically it should be a b or product of a b. So a b jo ha kasser implement kager using an AND gate, a 2 input AND gate un ke do no inputs pe kya hoge the variable a the number a and variable b the number b. Let us have a look at the function table of a half adder, the expressions, the sum expression and the carry out expression and the circuit representing the sum output and the carry out output. The half adder function table has 4 columns, 2 columns for the input and 2 columns for the output. The 2 input columns represent the 2 numbers a and b. The 2 output columns represent the 2 outputs sum and carry out. The 2 input columns have 4 combinations of inputs 0 0 0 1 1 0 and 1 1. The sum output shows the sum output of the half adder circuit. So the outputs are sum outputs are 0 1 1 0 respectively. Similarly the carry out column shows the carry out output of the half adder circuit the outputs are 0 0 0 1 respectively for the 4 input combinations. Let us have a look at the Boolean expression representing the sum output. It can be directly derived from the function table. The expression is a bar b plus a b bar. Now this expression is equivalent to a exclusive or b. Let us have a look at the expression representing the carry out of the carry out output of the half adder. From the function table the carry out output of the half adder is represented by the expression a b. Let us have a look at the circuit. As we have mentioned before the sum is represented by exclusive OR gate. The carry out output is represented by an AND gate. So both the exclusive OR gate and the AND gate inputs are connected together and they are connected to the 2 numbers a and b. If you have looked at the half adder circuit we have looked at the function table the expressions representing the sum output and the carry output. We have also looked at the implementation of the sum output and the carry out output. The implementation is pretty straight forward only 2 gates are used. Now let us look at the full adder circuit. Full adder circuit as we mentioned before has 3 inputs the 2 numbers a and b and the carry in input. The outputs are the same as the half adder that is the sum output and the carry out output. Again how do we implement the full adder? Let us have a look at the function table of a full adder. How many input columns, how many output columns basically the full adder has 3 input pins the 2 numbers as I have mentioned before and the carry in therefore 3 columns representing the variables a b and c n. So there are 8 possible input combinations. Now let us have a look at the 8 input combinations and let us determine the sum output and the carry out output. Now for a combination 0 0 0 the sum output has to be a 0. For the input combination 0 0 1 the sum output is 1. For the input combination 0 1 0 the sum output is again a 1. The input combination 0 1 1 the sum output is 0 the carry output is 1. The input combination 1 0 0 the sum output is 1 carry output is 0. Similarly, for the input combination 1 0 1 the sum output is 0 the carry out output is 1. And lastly the input combination 1 1 1 what is the sum output it has to be a 1 and what is the carry output it is again a 1. So now we have 2 outputs for the sum output and the carry out output. Now how do we implement the circuit? Basically if you write out all the mentums representing the sum output you can implement a circuit. Similarly, if you write out all the mentums representing the c out output then you can again implement the circuit. The circuit implemented using these mentums would be using more gates. So let us simplify these expressions before implementing the circuit. So let us have a look at the function diagram, the expressions representing the sum output and the carry output and the implementation of a full error circuit. The function table for a full error has 3 input columns and 2 output columns. The input columns have the variable a b and carry n, a and b of course represent the 2 input numbers and carry n represents the carry from the previous 2 numbers. The output has 2 columns the sum represents the sum of 2 numbers and the carry out represents the carry generated when the 2 numbers along with the carry are added together. Now let us determine the Boolean expression for the sum output. Now if you look at the function table the sum column has 4 mentums represented by a bar b bar c plus a bar b c bar plus a b bar c bar plus a b c. Now this expression can be simplified or rewritten in the form a bar into b bar c plus b c bar plus a into b bar c bar plus b c. Now b bar c plus b c bar represents the exclusive OR function between variables b and c. Similarly, the expression b bar c bar plus b c represents an exclusive NOR function between the variables b and c. So the equation or the expression can be rewritten in the form a bar into exclusive OR between b and c plus a into exclusive NOR between b and c. Exclusive NOR is represented by the plus sign within a circle and a bar over the entire expression. The expression can be simplified to a exclusive OR b exclusive OR c. The carry out expression is represented by 4 mentums as can be seen in the function table. The 4 mentums are a bar b c plus a b bar c plus a b c bar plus a b c. The expression can be rewritten in the form c into a bar b plus a b bar plus a b into c bar plus c. C bar plus c simplifies to 1 applying the Boolean rules. The expression a bar b plus a b bar is represented by an exclusive OR function between variables a and b. Therefore, the expression simplifies to c into a exclusive OR b plus a b. Now let us look at the full adder circuit implementation. The sum term is represented by the expression a exclusive OR b exclusive OR c. So basically 2 exclusive OR gates are required. So the first exclusive OR gate is connected to the inputs a and b. The output of this first exclusive OR gate is connected to the input of the second exclusive OR gate. The second input of the second exclusive OR gate is connected to the carry n. The output is of course the sum of 3 inputs. The carry out expression is implemented using 4 gates, an exclusive OR gate, 2 AND gates and an OR gate. The term a exclusive OR b is represented by the first exclusive OR gate. The AND gate on the top does an OR AND operation between the output of the first exclusive OR gate and the carry n. Similarly, the second AND gate does an OR AND operation between the 2 inputs a and b. The OR gate basically adds the 2 product terms to give the c out output. We have looked at the full adder. We have looked at the function diagram describing the operation or the behavior of a full adder. We have looked at the 2 expressions, the sum expression and the carry out expression for the full adder and of course we have looked at the implementation of a full adder. Now can we implement a full adder using 2 half adders? Well we can. Now a half adder has 2 inputs so at any instant it can only add 2 numbers. It would generate an output. So if you connect another half adder at the output of the first half adder and you provide or rather you connect carry n to the second input of the second half adder. What would be the sum output of the second half adder? Similarly, it would sum the input a, the input b and the carry. Similarly, how can you obtain the carry out? Basically the carry out of the first half adder is ORed with the carry out of the second half adder. The output of the OR gate would give you the carry out. Let us have a look at the diagram which shows the representation of a full adder using 2 half adders. 2 half adders can be connected together to form a full adder. The first half adder is connected to the numbers a and b. The output of the first half adder generates the sum of 2 numbers a plus b. The carry out output generates the carry out by adding the 2 numbers a and b. The second half adder is connected to the first half adder. In fact, the sum output of the first half adder is connected to the input a of the second half adder. The carry in is connected to the second input that is input b of the second half adder. What is the output of the second half adder? Basically it is going to be the sum of variables a, b and the carry in. Let us have a look at the carry out of the second half adder. It is odd with the carry out of the first half adder. Now, what are the 2 terms? Carry out of the first half adder results in the term a, b and the carry out of the second half adder results in the term a exclusive or b and it with c, n. Now, if you add the 2 terms, you obtain a, b plus c, n and it with a exclusive or b, which represents the c out Boolean expression. We have seen the circuit diagram which shows the implementation of a full adder using 2 half adders. Now, a single bit full adder can only add 2 single bit numbers. It cannot perform some useful calculations. In order to perform some useful calculations, you need to have let us say a 4 bit full adder or an 8 bit full adder or a 16 bit full adder. So, that means you can add 2 4 bit numbers, 2 8 bit numbers or 2 16 bit numbers. Now, how would you implement let us say a 4 bit full adder? Basically, if you have a single bit full adder and you combine 4 such full adders together, you would have a 4 bit parallel adder. We are just going to see the diagram representing a 4 bit full adder. Basically the c out, the carry out of the least significant full adder, least significant full adder would be adding the least significant 2 bits of the 4 bit numbers. So, a 0, b 0 represent the 2 least significant bits of numbers a and b. So, the least significant full adder would be adding bits a 0 and b 0. It would generate some output of s 0 and a carry out of c 1. Now, if this carry out is connected to the carry in of the next full adder which adds bits a 1 and b 1, the output of the second full adder would be s 1 and the carry out would be c 2. Similarly, the carry out of the second full adder is connected to the carry in of the third full adder and similarly the carry out of the third full adder is connected to the carry in of the fourth full adder. So, in this manner you can by connecting 4 different full adders together implement a 4 bit parallel adder circuit. Let us have a look at the 4 bit parallel adder circuit. The least significant full adder which adds bits a 0 and b 0 is shown on the right. The sum output is of course s 0. The carry in to this full adder is connected to 0 because there is no carry in to this particular full adder. The carry out from this full adder is connected to the carry in of the next full adder which adds bits a 1 and b 1. The sum is the sum output is s 1. The carry out which is c 2 is connected to the third full adder. So, the third full adder basically adds bits a 2, b 2, c 2. The output is s 2 and it generates a carry out c 3. The fourth full adder adds bits a 3, b 3, c 3 and it results in some output of s 3 and the carry out which is also equal to c 4. We have seen the connection of 4 full adders to form a 4 bit parallel adder. You can similarly add or connect 8 different full adders to form an 8 bit full adder. You can connect 32 different full adders to form a 32 bit parallel adder. Now, we have a problem with this particular circuit. If you look at the carry output generated from one adder, it is connected to the carry in of the next adder. Now, let us suppose you have a 4 bit full adder which we just saw. The carry out generated from the most significant full adder that is c 4. It would have to propagate all the way from the first full adder through the second full adder through the third full adder and ultimately through the fourth full adder. Now, let us suppose that the propagation delay for each full adder is 50 nanoseconds. So, how long would it take for c 4 to be valid? Basically, there are four full adders. So, the first full adder would delay the carry by 50 nanoseconds. The second full adder would again delay the carry out by another 50 nanoseconds. The third full adder would again delay the carry by another 50 nanoseconds. And finally, the fourth full adder would delay the carry out by another 50 nanoseconds. So, if you have a 4 bit parallel adder, the carry out c 4 would be delayed by 200 nanoseconds. Now, let us assume that you have a 32 bit parallel adder. So, the propagation delay would be too long. You cannot basically wait for the carry to be generated after such a long time. Digital circuits are quite fast. So, you have to find a solution to the delay. Now, this delay happens because the carry has to propagate through all the gates. So, what is the solution? Let us have a look at the solution, but before we look at the solution, let us just revisit that 4 bit full adder. Let us see the propagation of the carry from the first full adder to the last full adder. With the 4 bit parallel adder, the two 4 bit numbers A and B are applied simultaneously to the 8 inputs of the 4 bit parallel adder. Now, after a delay of 50 nanoseconds, c 1 would be available. After another delay of 50 nanoseconds, c 2 would be available. Then after another delay of 50 nanoseconds, c 3 would be available. And after another 50 nanoseconds, c 4 would be available. Although the two numbers A and B are available, they have been applied to the inputs of the 4 bit parallel adder, but the carry, since it propagates from the first adder to the second to the third and ultimately to the fourth, the carry out is not available until after a delay of 200 nanoseconds. So, you have to devise a circuit which looks at the inputs of the 4 bit parallel adders and generates a carry. So, the carry does not need to propagate through the full adder. The propagation of the carry through the full the 4 bit parallel adder is known as carry ripple. We have looked at the propagation of the carry bit through the 4 full adders. Now, if we have a 16 bit full adder, the propagation delay would be even more. And similarly, with 32 bit full adder, the propagation delay would increase even further. Now, we cannot afford to have such long propagation delays due to that carry bit. What is the solution to this? Basically, we need to have a circuit which looks at the inputs and predicts the value of the carry which can be used by the full adder circuit. Now, the look at carry generator circuit needs to be implemented. So, on what basis it is going to be implemented? How does it look at the two inputs or multiple inputs and generates a carry? Let us have a look at the look ahead carry generator circuit. Consider the full adder circuit shown. The term P represents the carry propagate. The term G represents the carry generate. The carry output is going to be 1 if the term G is equal to 1 regardless of Cn. Looking at the circuit, the sum expression can be represented in terms of P and C. So, the sum expression is P exclusive or C, where C is the Cn or the carry n. The carry out can be represented in terms of Cp and G, where C is Cn. So, the carry out is represented by the product term Cn into carry propagate plus the carry generate. Now, let us develop expressions for carry 1 output, carry 2 output, carry 3 output and carry 4 output. Carry 1 output is based on the carry input to the first full adder, the carry propagate term and the carry generate term. So, C1 is equal to the product between C0 and P0 plus G0. Similarly, carry 2 is represented by the expression C1 and it with P1 plus G1. C1 can be represented by the expression C0 P0 plus G0. So, the expression for carry 2 simplifies to G1 plus P1 G0 plus P0 P1 C0. Similarly, the expression for carry 3, C3 is represented by the terms C2 P2 plus G2. Carry 2 has the expression G1 P1 G0 plus P0 P1 C0. So, the expression for C3 becomes G2 plus P2 G1 plus P1 P2 G0 plus P0 P1 P2 C0. Similarly, the expression for carry 4 is G3 plus P3 G2 plus P2 P3 G1 plus P1 P2 P3 G0 plus P0 P1 P2 P3 and C0. In all cases, the carry propagate term is represented by the exclusive OR operation between the term A and B, the two numbers and the carry generate term is represented by the AND operation between the two numbers. So, G1 would be A1 B1 and similarly, P1 would be A1 exclusive OR B1. Let us have a look at the implementation of the look ahead carry generator circuit. It is shown along with the remaining part of the full error circuit. The inputs to the look ahead carry generator circuit are the carry propagate terms P0 P1 P2 and P3 and carry generate terms G0 G1 G2 and G3. The carry propagate and carry generate terms are generated by the exclusive OR and NAND gates after one gate delay. The outputs of the look ahead carry generator circuit are C1 C2 C3 and C4. The output C1 is generated by the circuit represented by the expression C1 equals to C0 P0 plus G0 which requires an AND gate to generate the product term C0 P0 and a second level two input OR gate to sum the terms C0 P0 and G0. Thus, C1 is available after two gate delays within the look ahead carry circuit. Similarly, the output C2 is generated by the circuit represented by the expression C2 equals to G1 plus P1 G0 plus P0 P1 C0 which requires a two input and a three input AND gate to generate the product terms P1 G0 and P0 P1 G0 which requires a two input and three input AND gates to generate the product terms P1 G0 and P0 P1 C0 respectively. A second level three input OR gate is required to sum the three terms thus C2 is available after two gate delays within the look ahead carry circuit. The output C3 is generated by the circuit represented by the expression C3 equals to G2 plus P2 G1 plus P1 P2 G0 plus P0 P1 P2 C0. The expression is implemented by a combination of three AND gates having two three and four inputs respectively and a single four input OR gate. Again, two levels of gates are used C3 is available after a gate delay of two. Finally, the output C4 is generated by the circuit represented by the expression C4 equals to G3 plus P3 G2 plus P2 P3 G1 plus P1 P2 P3 G0 plus P0 P1 P2 P3 C0. To implement the expression two levels of two three four and five input AND gates and a single five input OR gate is used. C4 is available after a gate delay of two. Thus for carry outputs C1, C2, C3 and C4 the delays of the order of two after the proper gate carry and generate carry terms become available. We have looked at the implementation of the look ahead carry generator. Basically we implemented this look ahead carry generator for a four bit parallel binary adder. The expressions we derive for C1, C2, C3 and C4. As we have seen the expressions are based on the carry generate terms and the carry propagate terms. Now to implement these expressions within the look ahead carry generator you need two levels of gates. The AND gates which generate the product terms and the OR gate which sum these product terms. So, the output of the look ahead carry generator is available after a gate delay of two. So, as you can see if you have this look ahead carry generator the propagation delay is reduced considerably and it is constant for all the bits. You have a 16 bit full adder circuit then all the 16 bit full adders would generate a carry after a gate delay of two. The four bit full adder are practically available in the form of integrated circuits. There are two types available the 74 LS 283 and the 74 LS 83A. Both these integrated circuits have the same functionality, but they are pin incompatible. Now both these chips are 16 pin integrated circuits. Four pins are used for the input number A the remaining four pins are used for the number B. You have four outputs to represent the four bit sum output. You have a carry N pin and a carry out pin. So, this sums up to 14 pins you have a pin for the power supply and you have a pin for the ground. So, now you can connect these four bit parallel adders to form 8 bit parallel adders 12 bit parallel adders and 16 bit parallel adders. How would you connect them? Basically you would connect the carry out pin of the first full adder to the carry N pin of the next full adder and similarly the carry out pin of the next full adder to the carry N pin of the third full adder. So, in this way you would be implementing a 12 bit full adder circuit. Now the carry N pin of the first full adder would be connected to ground because there is no carry to the least significant two bits. Let us have a look at the implementation of a 12 bit parallel binary adder using the integrated circuits which we have just discussed. Three integrated circuits would be used they would be connected together. So, the first IC has its C N or the carry N connected to 0 the carry out of the first IC is connected to the carry input of the second chip similarly the carry out of the second chip is connected to the carry N of the third chip. So, let us have a look at the 12 bit binary adder. The 12 bit parallel adder is implemented using 3, 7, 4 LS, 2, 8, 3 chips. The first 4 bit adder chip on the extreme right is used to add bits 0 to 3 the least significant 4 bits of the two 12 bit numbers. The second 4 bit adder chip in the middle is used to add bits 4 to 7 the next most significant bits of the two 12 bit numbers. Finally, the third 4 bit adder chip on the extreme left is used to add the most significant bits 8 to 11 of the 12 bit numbers. Similarly, the 4 bit adder chip on the extreme right generates least significant some outputs 0 to 3. The second 4 bit adder chip generates some outputs for the bits 4 to 7. The third 4 bit adder chip on the extreme left generates the some outputs for the most significant bits 8 to 11. The carry out is generated by the left most 4 bit adder it is shown as C 12. Similarly, the carry N is shown connected to the right most 4 bit adder it is represented by C 0. Carry out of the first 4 bit adder on the extreme right is connected to the carry N of the 4 bit adder in the middle it is represented as C 4. Similarly, the carry out of the middle 4 bit adder is connected to the carry N of the 4 bit adder on the extreme left it is represented by C 8. The 16 bit adder or adders having 24 bits or 32 bits can similarly be implemented by connecting more 4 bit adders. We have looked at the implementation of a 4 bit parallel adder using the commercially available 7 4 L S 283 chips. Now, in today's lecture we basically looked at the adder functional zone at we started with the half adder then we looked at the full adder. I mean, don't know adders key function diagrams behind the expressions derived key here implement gather. Then we said that a single bit full adder cannot do any useful work. So, what do we do? We need to combine such full adders to form a parallel adder. The parallel adder then we said the carry has to propagate through the 4 parallel full adders that is going to delay the carry. So, what is the solution to that? Basically, we said we need to generate a carry based on the input supplied at the full adder circuit. So, we have a look ahead carry generator circuit which generates carries which are delayed by a factor of 2. Finally, we looked at the MSI chips commercially available again as we have just looked at an example we can connect different chips together to form a 12 bit adder. We are going to stop for today. In the next lecture, we would be looking at some more functional devices. Inshallah, we will meet again in the next lecture. Take care of yourself. Adha Hafiz. As-salamu alaikum.