 Welcome to the session on 8086 system bus architecture minimum mode. At the end of this session students will be able to describe the minimum mode operation of an 8086 based system. Let us see minimum mode 8086 system. So if you are observing 8086 microprocessor, the 8086 is configured in minimum mode when its MN oblique MX pin is connected to logic 1. And in this mode all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. To adopt to different situations the 8086 processor can be operated either in the minimum or the maximum mode. The minimum mode is used for small system with single processor and in any system. So here the block diagram consisting components in the system are latches, trans receivers, clock generator, memory and Ivo devices. Clock is provided by the 8284 clock generator. It provides clock reset ready input to the 8086. Latches are generally buffered output D-type flip-flops like 8282 and they are used for separating the valid addresses from the multiplex address and data signals. And they are controlled by the ALE signals generated by 8086 and the data bus is driven through 8286 8-bit trans receivers and two such trans receivers are needed as the data bus is 16-bit. The trans receivers are enabled through the DEN signal while the direction of data is controlled by the DT oblique R signal M oblique Ivo, RD and WR are decoded by 3 as 8 decoder like 7, 4, 1, 3, 8. Bus request is done using the whole and HLDA signal. Now here the microprocessor 8086 pin diagram is available and here if you are observing 8086 is operated in minimum by strapping its Mn oblique MX pin to plus 5 volt or logic 1. Now also one more very important thing is pin configuration that is pin definitions from 24 to 31 are different for minimum mode and by using these pins the 8086 itself generates all bus control signals in the system bus configurations of 8086. So now until 8086 pin details regarding minimum mode operations that is how and what are the number of pins are available in for controlling the minimum mode configuration. So 8086 generates all bus control signals in the minimum mode configuration and these signals are first INTA that is Interrupt Acknowledge its output signal this indicates recognition of an interrupt request. Second ALE address latch enable again its output signal this signal is provided by 8086 to demultiplex the AD0, AD15 into E0 to A15 and D0 to D15 using external latches and the third one DN that is data enable output this signal informs the trans receivers that the CPV is ready to send or receive data. Next DT oblique R that is data transmit and receive output that again its output signal this signal is used to control data flow direction high on this pin indicates that the 8086 is transmitting the data and low indicates that 8086 is receiving the data. And the next pin M oblique IO its output signal it is used to distinguish memory data transfer and IO data transfer when M oblique IO is high there is a memory data transfer and if M oblique IO is low then it is a IO data transfer and the sixth one WR it is a write output and WR is low whenever the 8086 is writing data into memory or an IO device. Seven hold it is a input signal HLDA it is a output signal a high on hold pin indicates that another master is requesting to take over the system bus on receiving hold signal processor output that is HLDA signal high as an acknowledgement. So, here you have a question if Mn oblique Mx is high the 8086 operates in dot dot mode. So, you have four options please think on this question and try to write your answer. Your answer is B if Mn oblique Mx is tied to ground 8086 operates in maximum mode and Mn oblique Mx is tied to VCC the processor 8086 operates in minimum mode. Now, the 8086 bus cycle are depicted with their t states in the figure and the length of bus cycle in the 8086 system is four clock cycles denoted by T1 to T4 plus any number of wait states clock cycles denoted by TW. If the bus is to be inactive or idle after the completion of bus cycle the gap between successive bus cycle is filled with ideal state and the simplified timing diagram for the memory or IO read cycle which requires one wait state in the minimum mode is shown here in this figure if an input operation that is read operation is to be performed already is active low during T2 and the AD 15 AD 0 pin should enter a high impedance state in preparation for receiving the input data and the memory or IO interface is ready to transfer data immediately there are no wait states and the data is put on the bus during T3 after the input data is accepted by the 8086 RD is raised to 1 at the beginning of the T4 and memory or IO interface removes its data upon detecting this transition. Now, we are coming to the part of ride cycle timing diagram in the minimum mode the simplified timing diagram for the memory or IO ride cycle which requires one wait state in the minimum mode is shown here in this figure for an output operation that is write operation the 8086 makes the signal WR equals to 0 and place the output data in the pins AD 15 AD 0 during T2 during T4 WR is made logic 1 and the data is remote for both input and output operation DN is made logic 1 during T4 to disable the trans receiver and the M oblique IO signal is set to according to the next data transfer at this time. Now, we are coming to the summary part 8086 works in minimum mode when Mn oblique MX equals to 1 minimum mode 8086 is the only processor in the system clock is provided by the 8284 clock generator it provides clock reset and ready input to 8086. These are my references. Thank you.