 Hello and welcome to this presentation of the STM32 Management Data Input Output Slave Controller or MDIOS Controller Module. It covers the main features of the controller, which is used to exchange management data with a host device. The MDIOS controller integrated inside STM32 products provides a device management interface allowing a host to manage the STM32 configuration. It offers 32x16-bit wide registers. Applications benefit from a low-pin count standard interface to manage the device configuration. The communication speed can go as high as 20 MHz. The MDIOS controller provides all the functions specified in IEEE RFC 802.3 Chapter 22 needed to interface with a host. It consists of an MDIOS adapter and an advanced peripheral bus or APB interface. The MDIOS adapter provides functions such as frame decoding and checking, asynchronous wake up and interrupt generation, while the APB interface manages the control and status registers, data in registers and data out registers, and synchronous interrupt requests. Two clocks are available for the MDIOS controller, the APB clock or PCLK for the APB interface, and the MDIOS MDC bus clock for the MDIOS adapter. Note that PCLK clock frequency shall be at least 1.5 times higher than the MDC clock frequency. When the MDC bitrate is 20 MHz, the PCLK shall run at least 30 MHz. The MDIO frame format is sent over the MDIO pin with an active MDC clock. The clock may be stopped outside the frame format. The host sends MDIO data on the falling edge of the MDC clock signal. A preamble consisting of 32 bits with MDIO high is clocked in prior to the frame start. The frame start is encoded as a 2-bit value, 01. The frame operation is selected by a 2-bit field, 01 for a register write and 10 for a register read. Then, MDIO slave device address and register address are sent. Up to 32 device registers can be addressed. Subsequently, for a write frame, the host sends a 2-bit turnaround code, 10, followed by the 16-bit register data. When the host issues a read command, it changes the MDIO direction to input in the first turnaround cycle and the slave device drives the MDIO in the second cycle to 0. The slave outputs the data on the rising edge of the MDC clock signal. Following the second turnaround bit, the slave device sends the register data and when finished in the trailing turnaround period, it changes the MDIO direction to input again. When enabled, the MDIOS monitors the MDIO interface for an incoming preamble. At least 32 bits on MDIO shall be received with value 01 to detect a valid preamble. This allows the slave device to synchronize with the MDIO bus. Once synchronized, the 32-bit preamble is required after any received frame. Only after the MDIOS is synchronized, the preamble errors between received frames are reported by the PERF bit. Once the MDIOS is synchronized with the MDIO interface, the preamble check can be disabled by the DPC bit, allowing the host to send frames without preamble. A start condition is detected when an MDIO bit is set to 0. Valid start conditions are 0101 for a write frame and 0110 for a read frame. Start condition errors are reported by the SERF bit. The start condition will be processed by the MDIOS only when a valid preamble has been detected or when preamble detection has been disabled. The physical address allows frames to be sent to different devices on the same MDIO bus. The MDIO device slave address is programmed in the MDIOS port address register. When a frame with a matching physical address is received, it will be further processed by the device. Frames with a different physical address are discarded. The physical address will only be processed by the MDIOS when a valid start condition has been detected. The register address allows the host to access one of the 32 slave registers for write or read. The register address will only be processed by the device MDIOS when the frame's physical address matches. Note, on STM32 devices where the MDIOS implements less than 32 registers, if the host writes to a register which is not implemented, data will be lost and on read, 0 will be returned. When the host reads the data from the slave, the turnaround field is used in read frames to hand over the MDIO line from the host to the slave. The turnaround time is only one and a half cycles long, where half a cycle is used by the host to switch its MDIO pin to input and one cycle by the slave to drive MDIO with 0. There is no turnaround error generated for read frames. When the host writes the data to the slave, the host sends the 1-0 code instead. The turnaround code errors are reported by the TERF bit. The turnaround field will only be processed by the MDIOS device when the frame's physical address matches. MDIO data received from the host is written in the addressed MDIOS register. When enabled, the MDIOS generates a WRF interrupt that's also able to wake up the device from stop mode. The received data will only be processed by the MDIOS device when the write frame turnaround code is valid. MDIO data requested by the host will be read from the addressed MDIOS register. When enabled, the MDIOS will generate an RDF interrupt that is able to wake up the device from stop mode. The trailing turnaround field is only present in read frames to hand over the MDIO line from the slave back to the host. In detail, the trailing turnaround field is only one half cycle long and is used by the slave to switch its MDIO pin to input mode. The MDIOS provides separate read and write registers. The write registers are written by the MDIO host and read by the slave device CPU via the APB bus. The read registers are written by the slave device CPU via APB and read by the MDIO host. Each write and read register has an associated interrupt flag, WRF 31 to 0 and RDF 31 to 0, able to generate an interrupt and wake up the slave device from stop mode when the MDIO host accesses the register. For the D out register to reflect the DN data, the device CPU has to copy the data via the APB bus. The WRF 31 to 0 flags may be used to detect write register updates by the MDIO host. The device CPU has a time of 32-bit preamble plus 4-bit start condition plus 5-bit physical address plus 5-bit register address, MDC clocks to copy the data before the MDIO host can read the D out register again. Here is an overview of the MDIOS interrupt events. Register accesses by the MDIO host are signaled by its WRF 31 to 0 for write registers and its RDF 31 to 0 for read registers. Frame transfer errors are signaled by PERF, SERF and TERF interrupt events. Here is an overview of the peripheral status at specific low power configuration modes. The device is not able to perform any communication in domain or system standby mode. It is important to ensure that all transmissions are completed before the MDIOS controller is disabled or the domain or the system is switched down to standby mode. Here is an example of the MDIO interface used for communication between the station management device or STA and MDIO manageable devices or MMDs. Typically, an MDIO bus is used between the Ethernet MAC and the physical layer or PHY in parallel with the physical layer or PHY bus and is used to detect cable disconnection, speed of the Ethernet link, usage of CSMA CD or full duplex links, auto crossover, etc. Here is a list of peripherals related to the MDIO interface. Users should be familiar with all the relationships between these peripherals to correctly configure and use the MDIOS controller.