 Hello, and welcome to this presentation of the STM32MP1 Low Power Timer, or LP-TIM. It covers the features of this peripheral, which offers a set of timing features, and can generate waveforms even in low power modes. The Low Power Timer peripheral, embedded in the STM32MP1 microprocessor, provides a 16-bit timer that is able to run even in low power modes. This is made possible thanks to a flexible clocking scheme. The Low Power Timer peripheral provides basic general-purpose timer functions. One major function of the Low Power Timer is its capability to keep running even when no internal clock source is active when configured in asynchronous counting mode. The Low Power Timer's main feature is its ability to keep running even in low power mode, when almost all clock sources are turned off. The Low Power Timer has a very flexible clocking scheme. It can be clocked from on-ship clock sources, LSE, LSI, and HIS clock. Or it can be clocked from an external clock source over the Low Power Timer's LP-TIM IN1 or LP-TIM IN2 inputs. This latter feature is used for building pulse counter applications and is a key function for metering applications like gas meters, etc. The Low Power Timer features up to eight external trigger sources with configurable polarity. External trigger inputs feature digital filters to cancel out faulty triggers that could be raised in noisy operating environments. The Low Power Timer can be configured to run either in continuous or one-shot mode. One-shot mode is used for generating pulse landforms, while continuous mode is used to generate PWM waveforms. The Low Power Timer is a peripheral with two clock domains. The APB clock domain contains the peripheral's APB interface. The kernel clock domain contains the Low Power Timer peripheral's core functions. The kernel clock domain can be clocked by internal clock sources from an external clock source through the timer's LP-TIM IN1 input. The Low Power Timer peripheral embeds a 16-bit counter that is fed through a Power of 2 prescaler. The Low Power Timer peripheral features a 16-bit auto-reload register and a 16-bit compare register that are used to set the period and duty cycle respectively for a PWM waveform signal output on the timer's LP-TIM OUT output. The Low Power Timer features an encoder mode function that can be used to interface with incremental quadrature encoder sensors using the peripheral's IP-TIM IN1 MUX and LP-TIM IN2 MUX inputs. Both inputs feature glitch-filting circuitry. The LP-TIM-CMP and LP-TIM-ARR registers in conjunction with the bitfield's wave from the LP-TIM-CFGR register and SNG-STRT from the LP-TIM-CRR register are used to control the output waveform. The output waveform is either a typical PWM signal with its period and duty cycle controlled by the LP-TIM-ARR and LP-TIM-CMP registers respectively or it is a single pulse with the last output state defined by the configured waveform. If the last output state is the same as the one at the waveform's beginning, then one pulse mode is configured. If not, then set once mode is configured. The Low Power Timer's output polarity is controlled through the WAV-POL bitfield in the LP-TIM-CFGR register. The Low Power Timer features a counter-reset function used to reset to zero the contents of the LP-TIM-CNT register. Two counter-reset mechanisms are possible, the synchronous counter-reset mechanism and the asynchronous counter-reset mechanism. A synchronous counter-reset is performed by setting the count RST bit. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of three LP-TIM kernel clock cycles. When the RST-ARE bit is set, an asynchronous counter-reset is performed on the next APB read access to the LP-TIM-CNT register. The Low Power Timer features an encoder mode function that can interface with the incremental quadrature encoder sensors using the peripheral's input 1 and input 2 inputs. Both inputs feature glitch filtering circuitry. The encoder function is similar to the one embedded in the general purpose timers. In order to use the encoder mode function, the Low Power Timer must be running in continuous mode. One important thing to note is that only Low Power Timers 1 and 2 embed the encoder mode function. The Low Power Timer peripheral features six interrupt sources. The Compare Match Interrupt is raised once the content of Counter Register LP-TIM-CNT matches or is greater than the Compare Register LP-TIM-CMP content. The Auto Reload Match Interrupt is raised when the Counter Register's content matches the Auto Reload Register's content. The External Trigger Event Interrupt is raised when a valid External Trigger is detected. The Auto Reload Register Right Completed and the Compare Register Right Completed Interrupts are raised when the transfer of the content of the LP-TIM-ARR register and LP-TIM-CMP register, respectively, is completed from the peripheral's APB interface logic into the peripheral's core logic, which are contained by two different clock domains. These two interrupts are useful in mitigating the overhead of polling on the status of writing to these two registers when the peripheral core clock is too slow compared to the APB interface clock. The up and down direction change interrupts are raised when the encoder mode function is enabled and the counting direction is changed from up to down or vice versa. The counting direction of the Low Power Timers counter reflects the rotation direction of the quadrature's sensor. The Low Power Timer Peripheral is active in run and sleep modes. It is also active in stop and low power stop modes when it is clocked by an oscillator still running in those stop modes. The STM32 MP1 devices embed up to five LP-TIM peripherals, where only LP-TIM-1 and LP-TIM-2 instances embed the encoder mode. Wake up from stop and low power stop modes is supported by all LP-TIM instances. Wake up from LPLV, low voltage and low power stop mode is not supported for all LP-TIM instances. All LP-TIM instances can be allocated at runtime either to the Cortex-M4 core or to the non-secure Cortex-A7 core. For more information related to this peripheral, you can also refer to these peripheral trainings. System Configuration Controller, Reset and Clock Controller, Power Controller, Interrupts Controller and Direct Memory Access Controller. For more details, please refer to the following documentation available on our website. You can also browse through the STM32 MP1 Wiki and find more information on the dedicated page.