 Hello, and welcome to this presentation of the ARM Cortex-M4 Core, which is embedded in the STM32MP1 microprocessor series. The Cortex-M4 Core is part of the ARM Cortex-M group of 32-bit RISC cores. It implements the ARM V7M architecture and features a three-stage pipeline. In addition to scalar integer instructions, it also supports a single precision floating point unit and SIMD integer instructions useful to improve the performance of DSP algorithms. It offers up to 703 core marks when running at 209 MHz. The Cortex-M4 has three AHB Lite master ports, enabling concurrent instruction and data transactions. Interrupts received from STM32MP1 peripherals are handled by the Nested Vector Interrupt Controller, or NVIC. The Memory Protection Unit, or MPU, is in charge of assigning attributes and access permissions to instruction and data requests initiated by the core. Many debug units are implemented. Two protocols can be used to communicate between the serial wire or JTAG debug port, or SWJDP, and the external debug probe, either serial wire or JTAG. Invasive debug is performed by means of the breakpoint and watchpoint units. Regarding non-invasive debug, the Cortex-M4 supports two real-time trace capabilities, the embedded trace macrocell, or ETM, and the instrumentation trace macrocell, or ITM. Trace packets are output to the external Traceport Analyzer through the Traceport Interface Unit, or TPIU. STM32MP1 microprocessors integrate an ARM Cortex-M4 core in order to benefit from the powerful performance of its 32-bit processor architecture and particularly high level of deterministic processing. All Cortex-MCPUs have a 32-bit architecture. The Cortex-M3 was the first Cortex-MCPU released by ARM. Then ARM decided to distinguish two product lines, high performance and low power, while maintaining the compatibility between them. The Cortex-M4 belongs to the high performance product line. The processor core implements a Harvard architecture, as it supports concurrent instruction fetch and data load and store transactions. The instruction pipeline features three stages, fetch, decode and execute. Conditional branch execution is accelerated by early fetching the target instruction. SIMD techniques operate with packed data. For instance, two 12-bit samples acquired with the ADC can be stored in the two half words of the same 32-bit register. In the example described in this slide, two pairs of samples are multiplied and then accumulated into a destination register. Since data signal processing is based on some of products, SIMD instructions contribute to increase the performance with regard to regular scalar fixed point instructions. The Cortex-M4 core embedded in the STM32MP1 microprocessor implements the optional single precision floating point unit, which is compatible with the IEEE 754 standard. Add, subtract and multiply instructions take 1 clock to execute, multiply accumulate instruction takes 3 clocks, divide and square root instructions take 14 clocks. The Cortex-M4 has neither a cache nor an internal RAM. Consequently, any instruction fetch transaction and data access is steered to the internal bus matrix. This bus matrix selects the output AHB light master port according to the address and the access type, instruction or data. Three AHB transactions can be in progress at a time. For instance, an instruction access from flash memory using the iCode master port, a constant data access from flash memory using the decode master port, and an SRAM access using the system master port. The Cortex-M4's bus matrix is connected to the STM32MP1 multi-AHB bus matrix, enabling the CPU to access memories and peripherals. Since transactions are pipelined on AHB light, the best throughput is 32 bits of data or instructions per clock with a minimum 2 clock latency. One of the outputs of the Cortex-M4's bus matrix is the private peripheral bus or PPB, which is internal to the CPU. It is used to access memory mapped registers present in NVIC, MPU and debug units. In the Cortex-M4 core, the memory protection unit or MPU is used to protect address ranges according to the configured access permissions. When enabled, it intercepts any access initiated by the processor core. The memory protection unit or MPU in the STM32MP1 microprocessor offers support for 8 independent memory regions, with independent configurable access permissions for access permission, allowed or not read-write in privileged unprivileged mode, and execution permission, executable region or region prohibited for instruction fetch. The MPU is also in charge of assigning attributes to regions, called normal, device and strongly ordered. Normal is used to map memories. Device and strongly ordered attributes are used to map peripherals. The difference between them is the ability to buffer data during the peripheral access. The device attribute enables write posting, while a store to a strongly ordered region stalls the pipeline until the response is received from the targeted peripheral. The NVIC and debug units are described in separate presentations. For more details, please refer to these application notes and the Cortex-M4 programming manual available on the www.st.com website. Also, visit the ARM website, where you can find more information about the Cortex-M4 core.