 Thanks everybody for coming to the talk tonight. It's called space-time adventures on novena introducing Balboa I'm Andy Isaacson, and I'm star Simpson First a little bit about what this talk is about In the beginning we'll give a little overview about what novena is If this is the first you're catching that word that's the open hardware laptop slash dev board We used to work on this project Next an overview of what FPGAs are and why you might want to use one Then a little summary of the tools that exist today for working with FPGAs And then finally our manifesto and an overview of the work we've done on this project to date So beginning first here's some background. This is a picture of novena It's very exciting. If you're just tuning in on this project It's a completely open hardware laptop. In fact, it just began shipping last week in the very classic style of Hardware as it once was it ships with the complete booklet of all the associated schematics So you can go on and know quite a lot about what you're doing with the hardware in this laptop It has a lot of very powerful hardware Gaggy ethernet dual USB you can see some of that here you might recognize the connectors And most importantly it has an FPGA right there So what is an FPGA? an FPGA is Well the acronym stands for field programmable gate array. So Coming from the concept of an array of transistor gates that you can Reprogram After it's been manufactured to take any arrangement you like Importantly, it's a programmable circuit. So it's a really interesting Combination of both software and hardware in that way which you can use to implement any algorithm you can imagine They're they're used in short to solve any computable problem and any computable problem is Given given that you can implement say complete CPU to solve any computable problem that way Why they're better? Why you'd want to use one is they're often salt faster at solving specific problems Especially problems that can be computed in a highly parallel way Or in a way that's more gate efficient when you use a dedicated processor for it So next a couple of definitions some terms These are some words that you'll want to know when you begin working with FPGAs You'll hear the first term a lot a lot and it stands for a lookup table So I'm gonna get as skin the surface of the hardware side of this talk about as close as we're gonna get in discussing this if anyone here recalls early electrical engineering explorations logic gates You have and or so forth. Those are basically two input Lookup tables themselves. You have two inputs and you get something as a result of what those inputs are in An FPGA you have this concept sort of taken well beyond to the next level. So instead of just two inputs commonly today in Xilinx FPGAs you'll have Six and the outputs aren't defined in terms of like standard canonical logic. It's Anything that you want it to be so any input you can define every output in combinations of six So that's the smallest unit of computational cell you discuss in terms of FPGAs Larger sizes from there logic cells will be your groups of LUTs Along with some flip-flops and multiplexers Those are the things that you set that determine how your FPGA will go about doing its computation bigger than that logic slices or blocks of two cells Or you know a couple of cells in combination logic blocks are a couple of slices maybe four And then zooming out even further you have the FPGA fabric and that's discussed fairly often The fabric is you can imagine that these logic blocks are sort of floating around in a C or mesh Which you also program the connections between And the fabric is that physical layer that those blocks are floating in And Finally a core is the overall definition of how the gates will all be assembled And Going a little bit more so you have this FPGA. So how do you go about programming it? FPGAs are programmed in What are called hardware description languages HDL's? Which are is a human readable source code language similar to C or other system programming languages It's similar to other programming languages. You'll be familiar with in that it has a tool team Which is much like a compiler And it turns your code into a final bit stream, which is analogous for our purposes to an executable and that bit stream actually switches the physical connections and Describes the physical interconnects inside your chip Here's an example of an HDL this is verilog It's one of a couple HDL's It's the one we actually chose for writing our projects in in fact Easter egg This is actually code we wrote for the earlier project, which became this project This is a part of the AES encryption algorithm doing Computation if you're familiar with the verilog you've already read it And if you're familiar with verilog you might be able to find the bug in this code One thing that's interesting about this is if you're familiar with Python or C You'll notice that that beginning line the module sub bytes That looks like a series of arguments, but in fact those are actual Physical inputs here. Those those are thought of as wires that connect it to other things or rapid wires You will see more of those I suppose And So if you're interested in learning more about verilog We worked through this book and found it very useful just a little shout out to verilog by example For those of you looking to go from here and learn more as a counterpoint felt it Prudent to include this VHDL example in evaluating our HDL We decided we like verilog a lot more but for the sake of completeness. Here's what VHDL looks like VHDL just one of many HDLs of those terms are not interchangeable So you write all this code. How do you go about building for the FPGA? What's the process like? It's analogous to compiling but exists in several different concrete parts So the first part is synthesis and during synthesis your definition of what you want your circuits do is converted to a list of internal connections And the output of that is called your net list Then it moves to a stage called place and route and I think this is where it gets interesting for me from the electrical engineering perspective because FPGAs are fundamentally two dimensional and in order to implement the algorithm that you want to Compute you have to actually like physically lay it out inside this chip and it's similar I think to urban planning in some ways in that you might have two different modules That you need to be in communication with each other and if you do this part wrong and run like a connection straight between them They will never be able to communicate It's also called mapping by some vendors. So the the geometric aspect of this is certainly very important And then subsequent to that you have the bit stream generation stage where you take your physical layout and your connections and Turn it into that file with the switches that turn the chip into what it should be It's worth noting that bit stream generation seems like it'd be fairly straightforward, but is Highly vendor-specific the tools for doing that are fairly proprietary But as a note there's some very interesting reverse engineering efforts here to understand and publicly document Those systems find out more on the internet so star described a lot of the hardware of the FPGA and The last part in sort of the system diagram is this idea of an FPGA core so What is an FPGA core? To be very concrete about it The core is just a chunk of source code Which does something which implements some process or algorithm It's probably written in verilog VHDL or possibly in some higher level more abstract hardware description language Which gets turned into verilog or VHDL on its way into being in the chip There's one really interesting distinction in the FPGA world between a soft core versus a hardcore and FPGAs have over the years evolved Such that the vendors realized many people are spending a lot of their space in the FPGA doing some specific things So let's just go ahead and put that down on the chip as as hardwired, and that's a hardcore and then if you're Implementing something using the hardware description language in verilog or or VHDL. That's a soft core. It's software Now many people in this industry when they say core what they mean is IP core and IP here is intellectual property core. So this Is the idea that this source code is owned by someone and they have the right to sell it to sell that idea to market it to others and they can be exclusionary about that not sure if people don't want to So IP here is intellectual property not internet protocol Which is what I kind of was hoping when I first saw the phrase IP core But alas So it's it's interesting because this this FPGA world like the community of people who develop for FPGAs are Almost I would say mentally poisoned by this term the fact that the thing that you're building is a core And while a core is just an IP core that means that I own it It means that everything that is built is owned by someone. I Don't think that's how it has to work and that's one thing that we were really excited about In this project when we realized that open cores exists So open cores is a website open cores org and a project and a philosophy to build free freely licensed cores for FPGAs Amazing project. They've got hundreds of cores Hundreds of different designs you can customize them. You can integrate them. They have a shared bus interface for many of these So they work together really well It's really an amazing example of the free software philosophy in action so open cores is cool and IP cores are less cool, but there's an important concept there But in the Balboa project we use the word core a little bit differently And we'll talk a lot about accelerator cores and what that exactly is I'll get into in a little bit But I wanted to put a pin in that here so that everybody's on the same page So next we'll discuss a little bit more about the environment that this project exists within From the hardware to the software that currently exists to support FPGA development. So here again is Novena And this slide exists to give you a sense of how FPGAs are measured sort of You can see that this has 43,000 logic cells that makes it about a medium-sized FPGA in the Spartan 6 family It's got you know two different kinds of RAM here And then actually the second to last line item here is interesting. It's got a hard core Which is a DSP that DSP 48 a digital signal processor built into it Just as Andy was describing they've chosen to Include that here for so that it's permanently available It gives you a bunch of things you get an 18 by 18 multiplier an adder and accumulator And you don't have to write those things for yourself. They're just they're there A little bit more zoomed out on the Novena laptop itself The FPGA is directly connected to the ARM processor via a very fast bus 16 bits and we will use that more and You know, we've been asked in the course of preparing this talk like it's certainly, you know That's great and everything but like why is there an FPGA on Novena like what what would I want to do with it? And these are not things you might necessarily even want to do with it These are things you could want to do with it. So you could you know, you could have fun An attempt to put some Bitcoin mining into action You could emulate another processor with it so you could have that arm talking to a soft core processor of some other kind You can use it for crypto as I alluded to earlier. Our first project was to implement AES Our goal then was to accelerate SSL computations on the CPU You can do co-processing And you can also use it for processing over, you know, data you might be acquiring Actually, the Novena is pretty great. It's got this amazing analog to digital converter Which lets you get in Star I'm in software is is 500 mega samples per second actually awesome Tell me It's also great for doing the Novena has additional boards For example a software to find radio. You might use it for video or image processing things of that sort So now a little bit about the Ecosystem of open source tools that you could use for Targeting the FPGA for building your course A shout out to the creators and maintainers of all of these projects First this is Yosas. Yosas is something we're actually extremely excited about it exists Not in the same space as Balboa, but in a very complimentary space It strives to be what I think the proprietary tools that you can get today like Xilinx ISE and so forth To do that but in a free way It is not a complete replacement to date It has it can get you through synthesis It has the start of place-in-route system and it doesn't do bit stream generation But we're hopeful that with a couple of Xilinx ISE extensions Yosas could get there. It's also worth noting that this project has existed for about I think only two years And I think has been sort of worked on by like one guy so far. So it's pretty Amazing how far it's come It's open source. It has a very long tool chain and Also outputs to any ASIC or FPGA back in Next a quick word about my gen If you attended previous CCCs, you might be familiar with this board called the milky mist I like the milky mist a lot because it's sole purpose in life was to do really beautiful video Generation using an FPGA And the team that worked on that produced a lot of useful software as well Including this which is a Python toolbox for building hardware It lets you write a high-level description of your circuit in Python and then outputs Feralog or VHDL It's also used in actual projects, which is a strong plus We just thought we'd include a little example of what the code looks like for this and the following three examples So you can sort of get a sense for what it would be like It's a basic my gen example My HDL is a project that I like a whole lot We ended up writing directly in Veralog, but we considered writing in my HDL It is rather than being a toolbox for targeting hardware. It is you're actually designing hardware with Python It has a lot of docs their website is is really good and I really liked with the developers of this project Put into their website to support people who would want to Use it to program their hardware It is sort of like just a Python syntax for Veralog and it also Runs and gives either Veralog or VHDL your your choice So here's a snippet of a my HDL project One thing I really like about this example is it's in a you know, very well documented style all of their documentation is like this and finally Chisel chisel is very different from the previous two examples. It strives to let you design hardware In a embedded in Scala code It's often you know one-to-one with Veralog that you'd be writing But their philosophy is very different and their philosophy is really what's most interesting it's actually produced by a UC Berkeley group led by Jonathan Backrack and One thing that's really interesting is that Risk five which is a new completely open CPU was written entirely in chisel So that's pretty cool There's a paper associated with chisel. That's pretty great Which goes into further depth about the tension between having a general purpose hardware description language versus having a domain specific language for describing your hardware and Here's an example of That Scala code describing hardware So you might ask like why we need a free tool chain like other than you know free software is is great raw One problem is that a lot of the proprietary tools Are sort of monolithic and they seem a little creaky And our hope is that a free FPGA tool chain Would not only let you flexibly target any FPGA you might be working with It'll also lay the groundwork for new hardware description language experiments Which I think is part of what chisel is getting out in their paper about the tension between current monolithic HDLs faster builds Targeting FPGAs today is Naturiously takes a long time our Xilinx our fastest Xilinx ISE builds were about 40 seconds Which is all day, you know, it's enough time to go get a new cup of coffee and you can only drink so much coffee and then finally Longevity the idea here is that you know free software has a greater lifespan than any proprietary software Vendors come and go. You don't want to be locked in GCC has been around for a really long time We think something like that could exist So we promised you space-time adventures So here's the space-time picture from Wikipedia Like Wikipedia a lot in order to get into the space-time adventures. We have to set the stage a little bit Roll back and look at the history Let's go back to 1965 1970 computers existed everyone had read a newspaper article about computers But how did a computer come to solve an actual problem in? 1965 well you had this computer with the CPU and You have a team of programmers who are going to build an application for this computer that's CPU That's computer hardware that application are going to exist together that there's going to be a fixed Thing which exists at the end of this project, which is solving that problem whatever that problem is Maybe it's a banking application. So this bank is going to have this computer and it's it's going to be their computer so you have the CPU and You have the team of programmers and maybe the team of programmers realizes that the CPU doesn't quite do what they want So they they ask well, let's just change the CPU. Let's add an instruction to it So now the CPU gains the ability to do a binary coded decimal because that's what they were going to do in this bank banking application and The team of application programmers are building for this computer So they write in of course in the assembly language for this computer for this CPU with its new custom instruction And that application is obviously only going to run on this computer the one in Poughkeepsie You wouldn't necessarily think of also running it on the computer in Minneapolis So that application and that computer are bound together and the peripherals as well the printer gets wired into that computer the computer is modified to talk to the peripheral and So now you have a printer and maybe a tape drive attached and now you have this this object Which has been created which which solves this problem It's really cool. It solves the problem. This this was really cool, especially at the time But it's it's monolithic it it does exactly one thing so rolling forward a little bit 1972 1972 is the year that Unix was released in a portable form a new operating system not the first operating system not the first operating system to Provide the features that it provided But I would argue at this point clearly one of clearly the most successful long-lived Really groundbreaking operating system Unix brought in amazing innovations for software modularity Unix really popularized multitasking so you could have multiple programs running on a single CPU This was kind of crazy in 1972. Why would you do that? How could you do that in a way that actually works? Unix also introduced virtual memory you no longer had to map the physical addresses directly and Program your overlays so that the thing that so that your code would fit on on the machine and Kind of most revolutionary Unix was programmed in a high-level language at least what was considered high level at the time programming language C So This is just amazing I mean it it's hard looking back today to imagine how amazing it was that that This underlying technology enabled component reusability for software development. I mean Wow Such computer We gained a ton of infrastructure as software developers and it was a really long drawn out painful process Not everyone got it at the beginning the idea that reusability Small components pieces working together in The service of the goals of the final user of the computer Would actually be a good thing and some of these technologies today are so taken for granted that it's hard to even remember that they exist as discrete Controversial at the time technologies virtual memory very controversial I started my career at Cray the super computer company and I had co-workers who remembered this battle now virtual memory is a fad It's never gonna take off Time-sharing the fact that you could have multiple users using the same CPU simultaneously I mean looks good in a research paper, but who's actually gonna deploy that production I Operating systems with these apis like you can just call things and and things happen in a semi reliable manner and you get bug fixes and Your application just keeps calling the same function and it works better. How does it even how does it even happen? Networking I just call socket and TCP does a bunch of packets under the hood and it's it's amazing Device drivers that TCP layer isn't talking directly to the ethernet card. It's going through several layers of abstraction We write all of these Tools that we're building these days in high-level languages and they all rest on the foundation of compilers that turn our expressive thoughts into disc into discrete actions on the hardware and We have libraries. We have these vast libraries of software Some of it's really terrible some of it's better some of it's very new and won't last for very long and others other parts of It are like lindpac and are we're still running code that was written in 1973 It's amazing when you think about it how this infrastructure has really separated us from where we were at the beginning of the computer revolution in Conclusion I can wrap it up and say that we don't program to bear metal anymore We've managed to move up layers of abstraction and have gotten a lot of capability as a result So now given that background it's time to tell you the manifesto of our project Our vision is to let us do more than one thing at a time on the FPGA and to do so flexibly Or in other words writing and using an FPGA accelerator core can and Should be as easy as writing a high-performance C application I actually expected laughter rather than applause there because I blame our test audience Because as as those of you in the audience who've done this know writing a high-performance C application is no easy matter But imagine trying to do that in assembly It would be a lot more work. So I wanted to emphasize that the goal of The Balboa project is to build dynamic reconfigurable computing and each of those words matters It's dynamic because What the hardware is doing at any specific time can be changed with the flip of a switch it's reconfigurable because What you've expressed as the accelerator core can be moved around the FPGA to optimize resources or To allow room for another accelerator core to be loaded and it's computing because Balboa is focused on the idea of Enabling computational acceleration on FPGAs FPGAs are also amazing because they have fantastic IO capabilities They have really fast digital IO really fast analog IO. Those are awesome. Those are fantastic I'm glad they exist. I totally use things that have FPGAs in them But that's not what the Balboa project is about. It's not the killer app for me. So Balboa is Getting down to the actual nuts and bolts of the system that we've built and that we're planning to build Balboa is a library and some control software which runs on the CPU of the Novena platform And the control software makes sure that the FPGA is doing its job and that the apps are able to access it correctly and Balboa is also a bus and management layer on the FPGA implemented in Vero log Which you can plug into you as a developer of a accelerator core can plug into when you're writing the core and we hope that it will provide infrastructure and useful management so that This job becomes a lot easier the Novena hardware platform Looks a lot like this in block diagram leaving out some of the complicated bits We're a little bit further in than we were in the last slide that had this picture on it the FPGA and the ARM CPU are Connected by that fast bus both the FPGA and the ARM have their own DRAM associated with them The ARM CPU has the standard compliment of Interfaces USB gigabit ethernet HDMI and so on the FPGA also has IO I'll put the top for those times when you just have to get out into the outside world and Now diving in to see how the software maps onto this physical architecture we've got the Balboa system here in the FPGA world We have the Balboa bus Which provides the management and the interconnect we have many different cores running on the FPGA simultaneously and then on the software side Interf the interface is mediated by lib Balboa and And talking to lib Balboa, we have the management software FPGA demon and Any apps that are trying to use the FPGA? cores accelerator cores to Compute their favorite function so the Novena Laptop is amazing. It has this really quite large FPGA I say huge here, and I should quantify that There's enough room on the Novena FPGA to have two full 32-bit CPUs running simultaneously with plenty of room to spare So there's a huge unexplored territory here of things that could be done with the FPGA and It's time to go exploring and it's a brave new world so here's the vision where we can go and Why having Balboa will be cool and is pretty cool already Balboa provides interoperability of the accelerator cores so you can use multiple cores simultaneously on a single FPGA and It also We're hoping that we will that the tooling will improve over time currently We're using the vendor tool chain and it's not great although it's getting better as we figure it out and learn the ins and outs FPGA is currently aren't as useful as they could be Many Novena users don't have any plans to use their FPGA because they don't understand what it could possibly be useful for So we think that with some infrastructure the Balboa infrastructure if the FPGA on the Novena will be a lot more useful Now one point that it took me a while to get to here is that the point of Balboa is not building the tools and the compilers The point of Balboa is really to allow us to use the FPGA efficiently With less overhead of doing so It doesn't matter to me if my FPGA can run something really fast If it's a lot of work for me to set up I can't even begin to tell you how many cool FPGA boards I have that I bought because FPGAs are cool and they're sitting in my closet Because there's too much work to set up The point of Balboa is to let us do more than one thing at a time on the FPGA and to do that flexibly So the goals of the Balboa project is That you developers write cores in your chosen HDL Currently I would recommend Verilog because the alternatives aren't completely baked But I can see paths to a better future. You get fast direct access to the core Lib Balboa just sets things up and then gets out of the way You get standard interfaces for both the core and the application I spent several months at the beginning of my of This AES project trying to figure out how the heck I was supposed to connect the Verilog that I was writing to the software that I wanted it to talk to and most importantly to me is that with Balboa the end user chooses what runs and when Drawing a connection back to how software reconfigurability completely changed the world Today no one would think of having a single-purpose Computer that costs enormous amount of money and only does one thing the person who's using the computer chooses what it's doing and with Balboa we can do the same for FPGAs the Authors of accelerator cores and the authors of applications that use them Can build something can build some components in the Unix philosophy build something small that does one thing well and The end user gets to decide when and where that runs and what it does Taking it places that the original author never could have dreamed of So how far along on this ambitious vision are we today? frankly After we started this talk after we started this project Most of a year ago. We're not as far along as I had hoped I would be at Congress this year But we have some really encouraging results We do have multiple cores running on the FPGA one at a time. So we can Bring up one one core Run with it for a while and then say I'm done with this I'm gonna start a different core and start that and the nirvina system continues running flawlessly Apps using the Balboa system can M-map the core and get direct access to the registers exposed by the accelerator core And we're doing this all Currently without a kernel driver I'm not sure that we can keep this up. I think that a kernel driver is going to be a critical part of the system in the Medium to long term, but for now everything can be done from a user land process running as route Yolo So that's the current status of the Balboa project So at this point, we're going to discuss what's coming up next For us on the Balboa project and what we'd like to see happen So first Seven issues. Yeah, so the Introduction of time-sharing and virtual memory in addition to enabling enormous kinds of productivity and creativity Also brought in some security challenges now you have Resource exhaustion issues you can DOS a computer because there are multiple things running and maybe one of them is trying to prevent another one from running Similar many similar kinds of problems can happen. What should we call this? What should we call this seven security issues there? I don't know their challenges things that could happen on an FPGA if you're doing it or seven awesome hacks So seven ideas for potential security problems or awesome hacks Which I hope someone at a future Congress will present on The first one electromagnetic coupling There's this amazing paper by Adrian Thompson from 1996 called an evolved circuit The full title is actually a little poem, but it didn't fit on our slide The picture here is a picture of the circuit which which he evolved And There's some gray. Oh, they're completely unreadable. Unfortunately. They're not visible. Yeah, there's some gray squares up there. Don't don't Around around the edges of that circuit. They're not connected and According to the documentation of the FPGA Unconnected Unconnected functional blocks shouldn't be able to affect the outcome of the circuit at all Shouldn't be able to according to the documentation Turns out that if you remove any of those functional blocks from the design the circuit stops working The documentation isn't telling me the complete truth I'm shocked shocked An interesting side note here so this paper is amazing I recommend that everyone read it It was on the web for like 15 years. It's totally incredible paper Really well done with some high-quality 1996 web design It's it's great and the University of Sussex restructured the website in 2013 and Now that paper is no longer on their website the links on Google go nowhere Adrian's paper is only available on archive org So a shout out to the Internet archive Even the academics are trying to delete the web It's important for us because cores have never really been shared on the same FPGA before so the question This raises is whether you could create an appropriate antenna in hardware to snoop on other processes being computed on the same FPGA Seems like it should be possible documentation says it won't work, but second awesome hack that bit stream that is output from the tool chain and then fed to the FPGA over a hardware interface It's a stream of bits. It's a language in In the in the in the hashtag It's called lang sec the idea of tweaking inputs to a given interpreter to Find unexpected behavior in that interpreter The FPGA bit stream is a language with an interpreter implemented in hardware in the FPGA fabric What happens if you give that interpreter unexpected input? Do we get weird results? I bet we do it's only gotten trusted input so far Which leads to the second option bit stream exploits In our pre-talk prep we Talked to someone who's actually done some reverse engineering in this space Zobbs and he pointed out that the bit stream Apparently can fairly easily be configured to connect power directly to ground and Everyone who laughed has let out the magic smoke at some point by doing exactly that Probably some really interesting fairly expensive experiments that need to be run there You too can talk to zobbs the novena hardware forms are very good. It's true The bus protocol the FPGA on the novena and the CPU on the novena are connected with this EIM bus Some acronym doesn't matter what it says. It's a bus It's pretty complicated because it has a very sophisticated protocol with very strict timing timing requirements, so when the CPU asks the FPGA for a given Memory address the FPGA has a responsibility to return an answer within a certain number of clock cycles And if the FPGA doesn't return the CPU might crash might hang Ask me how I know ask me how many times I power cycled my dev hardware Either the core The accelerator core on the FPGA or the app might be able to trigger this So there's some really interesting fuzzing work to be done Hopefully we can't light things on fire as is as easily at that part of the protocol That leads into the the fifth awesome hack malicious apps once I have an app with Access to an FPGA accelerator core. It's talking over that EAM bus to the Balboa bus on the FPGA What can the app do to trigger unexpected behavior now? Most things are pretty robust. I'm sure that if you do normal things from your app Then nothing bad will happen, but what happens if the app issues an unaligned read to the FPGA? Maybe it works, right? Maybe we see some really interesting behavior Had a joke there, but I've lost it another awesome hack Timing attacks one of the reasons that FPGAs are so cool is that you get down to the cycle The the clock cycle 50 megahertz or 100 megahertz or 200 megahertz Accurate timing information when something happens you can know exactly when it happened Sounds like a great way to build a timing attack on a software algorithm If I can extract the exact cycle when some IO happened I can probably find out some really interesting things about your cache misses The layout of your AES key table Your RSA implementation should be a lot of fun and the 7th awesome hack is Hardware backdoors now There's this interesting idea that some people have bandied about for why we should switch to FPGAs and to Make this make any sense. I have to put on my paranoid tinfoil hat and say, you know I'm worried that the NSA might have put a backdoor in my Intel CPUs AES instructions and I'm going to fix this by not using an Intel CPU to do my critical secure Computation instead. I'm going to use our slides like fine here In the NSA had nothing to do with that. I'm sure I'm not so sure So I'm going to use a soft CPU it's written in Verilog I can look at it read the source code and and convince myself that it's correct And I can look at the bit stream and convince myself that it's correct to the NSA have not backdoored my tool chain And I'm running on an FPGA, which is just a sea of gates. So everything should be fine, right? I can trust that they didn't backdoor every gate on this FPGA It turns out the urban planning metaphor was very accurate You can't just put the parts of your soft CPU anywhere on the FPGA fabric If you have an FPGA the ALU and any AES accelerators that you put are going to end up in a fairly small set of places on that fabric So if I am the NSA and I'm in charge of backdooring an FPGA so that it will Be able to snoop on the AES keys of a soft CPU implemented on that FPGA I can probably manage to do it turns out sad face The backdoors in short the backdoors will probably still work if they exist at all which they don't Because I took off mites in foil hat And our slides are back. So that's good As far as the rest of Balboa goes we could use your help We'd love to have people join our project and we're going to wrap up by describing Seven things that we would like to have help working on So our current proof of concept is Just one core at a time we can build the accelerator core and synthesize it and load it onto the FPGA But as a next step one goal of the project is to make it really easy to take multiple cores synthesize them into a single fixed bit stream and load that onto the FPGA Pretty straightforward how to do it a little bit more code to write could use some help Dynamic reconfiguration of FPGAs is a really interesting area now most people who are using FPGAs Reconfigure the whole thing at once you Configure it once at boot up time and now your FPGA is a software find software to find radio and you If you need to do something else with it if you want to use it as a Bitcoin miner you stop using it as a software to find radio and load the Bitcoin mining bit stream and now it's a Bitcoin miner well, it would be really cool if I could have the software to find radio taking up two-thirds of the FPGA and Dynamically decide. Oh, I would like to do some Bitcoin mining load the the Bitcoin core on the remaining space and Go from there and then decide. Oh, I need to do some secure I need to do lots of crypto So I'm going to unload my Bitcoin mining rig and load up a crypto accelerator without stopping the SDR this is Theoretically possible the documentation says that it should work haven't gotten it working yet having multiple cores on the FPGA running on the FPGA simultaneously using the bus between the FPGA and the CPU In a fair manner, so we need bus arbitration and Related to that allowing multiple apps to use the FPGA bus simultaneously We will require some software work on the Unix side on the Linux side to let the M-Map mappings interoperate cleanly the Balboa FPGA the the Navina FPGA has a bunch of really cool IO and we should be able to use that That's just a matter of teaching the Balboa framework about those resources and giving it a management layer and Related to that using the RAM that RAM that's attached to the FPGA Currently if you wanted to use that in a Balboa core, you would have to do a bunch of hand coding and verilog That should be easier. There's no reason for it to be as complicated as it is and the last and perhaps I think the most important is that we should be able to implement Cores for Balboa using higher-leveling which is not having to write verilog ourselves because writing verilog is kind of a pain So here's how you join. I Will admit that when we found out our talk was accepted. We hastily whipped up a wiki, etc You can join the conversation on Twitter with our cool hashtag And we hope to see you join Finally, I will say that the Balboa FPGA GitHub is a special note clone away. Check it out. We'd love your feedback Today the best way to get in touches via Twitter, which will use to bootstrap to email Thank you so much special thanks to everyone who helps us with this project and The creators of Navina are in fact in the room. It's very exciting and we hope to spur a huge amount of Work and excitement on this project. So thank you Thank you very much We still have some minutes left not too many, but you have some minutes left for questions So as usual, please line up behind the microphones in the room I think the first question goes to you. So start one thing that we never explained in our talk is the name Balboa Where does that name come from? And he wants me to answer where the name Balboa comes from I don't know if you all read Bunny's blog as closely as I do But we learned that Novena the name of the laptop is in fact the name of a Singaporean MRT station Somewhere I apparently close to where Bunny lives We just thought we'd shoot one back Balboa is we think the equivalent Bart stop In San Francisco. So whenever you're passing through Balboa Park station Little nod think of FPGAs Okay, first question from you about this Yes, but I have a question bit about the numbers and the earlier slide you said no venas features a ADC with two times 500 mega samples per second a bit So there's one gigabyte per second How much of this band is available over the Bilbao interface between FPG and arm the question is how much Bandwidth is available between the FPG and the arm or Between the FPG and arm between the FPG and the arm So the the The FPGA on Novena suffers. I'm not an expert in this area, but I can address the question The question is we have a lot of samples coming in to the the ADC converter analog to digital converter And only a smaller amount of bandwidth available to the CPU what you end up doing in a case where you're doing something like that is Doing some kind of down sampling or processing in the FPGA to reduce the Samples to such to a rate that the CPU can accept And there's a lot of work That's one of the primary things that software to find radios do FPGA so for that kind of thing SDR experts are the people to talk to you okay You can build a digital down converter and a numerical oscillator in the FPGA Okay, can I please remind everybody that we're still in Q&A So please keep the volume down and please if you have to leave to it quietly Otherwise we can't hear anything Yeah, please a question from the phone from the other side. This is really cool and exciting what kind of Applications, do you think would be most suited in terms of I don't know performance per watt or a peak performance? And how would it compare to GPU acceleration in terms of what you can do with it? so GPU acceleration The question is GPU acceleration versus FPGA acceleration what applications are well suited for For FPGAs the one Thing that springs immediately to mind is anything where the timing matters a lot So we started out with this project doing AES GCM because it turns out that the GCM mode of AES Requires hardware support In order to be secure you can write software that does GCM, but it will nearly inevitably have a Timing information leak With hardware you can avoid the timing information leak. So there's a case where it matters a lot Another answer would be I'm personally very excited about the potential additional uses of novena as an oscilloscope and Just off the cuff I can imagine a project where you're sampling a high-speed circuit and you have some action that the FPGA takes by Sampling that and Outputting I know Andy lives in an IO devoid world, but that would be something I think would think was pretty cool Next question When swapping out cause is the state fully preserved that you have to use Sorry, I can't we can't hear you could you speak a little close to the mic very close to the mic when this When you're swapping out cause is the state fully preserved or do you have to continue from a safe state? When you're switching between course, yes when you're switching back to one years before yeah Excellent question is state preserved or do you restart a new state was the question exactly? The I Don't want to answer incorrectly here. So I'm taking a second When switching between cores if the core has state in the in its FPGA circuit That state needs to be preserved when you swap back or else you can preserve state at a higher level where the application or rather the library the Balboa library Preserves the transaction before it's sent to the to the FPGA So that when it's swapped back in you can restart that calculation One good way to define the future is to help us write it Next question. Hey, thanks for giving a talk and the nice project really So although I've backed a new Vena project I'm wondering how heavily tied is the Balboa architecture to the way To the how tight is the new Vena the Balboa project to the way that the new Vena has the FPGA attached to the processor How portable is it to out of pieces of hardware? So our goal is to be able to sorry the question is how heavily tied is Balboa to No Vena and specific And our answer I think is that our goal is to target any FPGA ultimately At present we're using no Vena as a dev board platform to get started You need somewhere that's exactly right and I'll expand on it by saying that you need somewhere to run the software Component of this that doesn't have to be an arm CPU attached to an EAM bus one of the goals of having the abstraction layer is that you could have different interconnects and I hope that someone will Make a computer I can actually afford which has an FPGA on the hyper transport directly attached to an opt-ron or similar Computer Kray actually makes a supercomputer like this. They started like ten million dollars In the interim an interesting project you might want to look at is the zinc FPGA platform which has a hardcore CPU on board for very high speed throughput between the FPGA part and the CPU part It's another possible starting point. That's a great starting a great next step And the last next step is that I really want to see the Balboa architecture or something like it running on a soft CPU that's running on the FPGA while reconfiguring its own FPGA and if we can Your dog Thank you So I have to cut your shark here because we run out of time and the next talk is going to be really crowded We want to answer all your questions. We'll be outside. All right So all people that are having certain questions, please start them outside and again, I asked before one moment of applause Thank you very much One last request could someone could someone please make a free Twitter replacement So I can stop using Twitter as my primary means of talking to people about stuff like this