 Hello everyone, welcome to lecture on test bench for decoder. At the end of this session, students will be able to write a test bench for decoder. Also able to verify the VHDL model designed for decoder with the help of this test bench. Now, before starting with the actual session, let's pause the video and think about what is a decoder. If you remember in the previous video lectures, we have completed the different VHDL modules for circuits like half adder, full adder, decoders, encoders, multiplexers, comparator. So we have already designed that and if you remember, decoder is something which converts one form into the another form or it going to be mapped inputs in a different output form. So this is the decoder which is called 3S to 8 decoder. Here three inputs are there which are mapped with the eight outputs. So that's why it is called 3S to 8 decoder. So three inputs are mapped with the eight outputs. So i is having three bits i0, i1, i2 and z is having eight bits output z0 to z7. Now if you remember that, we have formed the table for that decoder also 3S to 8 decoder. So these are the three inputs and these are the eight bit output. So which bit is 1 from the output for what combination of inputs, so that given by this table. Whenever the input bits 00 is 0, in that case your z of 0 bit is 1, remaining bits are 0. And if 001 is there on input side, z of 1 bit is 1 and remaining bits are 0. So this is how the combination because of three input bits are there, eight combinations and according that each bit is made 1 and all other bits are 0. You can see. Now we already done the VHDL code writing for this, so let's have a look at that and then we go for the directly test bench writing for 3S to 8 decoder. So this is the VHDL code which is having three important parts, first is a library declaration as I said. So library is included, library IEEE, then package is included, STD logic 1164 from that we are using all whatever declared in the package, so that's why dot all is mentioned. Then second important part is entity. So entity is then, in entity we have to write the inputs and outputs associated with your decoder. Now in this case, now in this case we are having three inputs and eight bit output, so three bit input and eight bit output. So I is the input of vector type having two down to zero range is given, that is three bit and z is output again vector type, so that's why it is having a range seven down to zero, eight bit. Once we done with the input and output declaration, we have to end the entity, so end entity name. Then third important part of your code is architecture writing, so architecture, architecture name of for which entity you are writing architecture, that entity name supposed to be here. So here it is that decoder three eight, so it is same as entity name. After that begin keyword you have to use, then we are going to write the actual behavior of your decoder, so we have to write in the process, so process I, I is in bracket of the process written as sensitivity list, which affix the output of your circuit. Now in this case I is the only signal which affects your output, so in the sensitivity list we have mentioned I over here, right. Then process begin. Now after that we are going to write the actual behavior of your architecture. So with the help of case statement here we have done, case signal I is when that signal is zero zero zero, so case I is when having value this zero zero zero, in that case we are assigning z with the value this, that is z of zero bit one remaining beta zero. So how to write this, you can refer to the previous slide stable, so input having this value your output z is having this value, then input having zero zero one, when then z is having value z of one bit is one remaining bit is zero, so this is how we have to complete all the combinations of the input and you have to write the according value of z assigning. After that last condition we have mentioned that when other than this value is there, if it is not from this, in that case we are assigning output z with the high impedance, so that is why I mentioned z z z over here, all z bits, right. Once we done with the writing of all the cases we have to end the process, so end process, before that we have to end case, so end case end process, then we have to end the architecture, so architecture end architecture name. So this is the code for the 3S28 decoder, this code can be designed with the help of any tool available in the market, I have used Xilinx and after that you can use the any simulation software to perform the simulation, I use the inbuilt simulator from the Xilinx itself called ISEEM simulator and if you perform the code, this code and perform the simulation, you will get the output something like this, so this is the inputs and this is the output, input is of 3 bits, so that is why it is shown like this and output is of 8 bits, again that is why it is having like this. Now if you observe the previous first condition, first as the input is of a stereologic vector type, the value is not assigned, so it is undefined, that is why it is showing u and this u u u, if you check the code, it is not from that table from the value 0 0 to 1 1 1, we have written others condition, so it satisfy the others condition, that is why the output having all the Z and the remaining conditions you can check when 0 0 0 is there, then in that case last bit is 1, again for 0 0 1 second bit is 1, so this is how you can verify the VSD code with the help of simulation. Now for this 3S28 decoder, we are going to write the test bench now, so test bench for 3S28 decoder and the same it is having 3 parts library declaration, then entity part, but the entity is supposed to be empty, so empty entity is there, the thing to declare in that entity, third part is architecture, in architecture which design you are using that is used as a component, so component declaration is done, component is nothing but the having the same entity whatever you created previously, only the instead of entity keyword here the component keyword are used, remaining part is same, you have to end the component end component, after that we have to mention the inputs and outputs, so inputs are there, two inputs, sorry one input I and output is Z, input is of vector type 2 down to 0, output is of again vector type 7 down to 0, right. Once we done with the input and output declaration, signals declaration, we have to write the constant period, this one is optional you can directly go for the process writing, after that we have to begin the architecture, then component instantiation is done, so this component we are declared over here and the component instantiation is over here, for syntax you already know to perform the component instantiation, you have to write the component name, label is there first, then component name, then port map keyword you have to use and then in the bracket you have to map the signals, right, so I is mapped with the I and Z is mapped with the Z, so this I is mapped with the this I and Z is mapped with the this Z, right. Once you done with the component instantiation, you have to write the process, now here your process begin, so begin process, in that we are making the input values modify and according that we are checking for the output, so how to write that let us see, first we made I value assigned with the 0 0 0, we waited for period, period we declared as a constant in previous slide you can verify, then we are use assert statement, assert statement which checks for the Boolean condition and if that fails it generates the report statement, report statements of different type whether they are note type, they are warning type, they are error type, right, here it is error type, severity error, right and if that condition true Boolean it go for the next, it generates the report statement, assert statement generates the report only when the Boolean condition fails, it is opposite to if condition, if condition executes the comes in a loop when the condition is true, it is opposite, right. This is the one case when I is assigned with the value 0 0, output supposed to be this, similarly we have to write the remaining cases, I is having value 0 0 1, output is having value is this, similarly all the cases you have to write, right. Once you done with the all the cases, you have to end the process, right and after that you have to end the architecture, so end architecture. So, this is how you can write the test bench for 3S to 8 decoder and once you done with the code writing, you can verify again the test bench with the help of simulation and if you perform that you will get the output something like this. So, this one is perform with the again in a ICIM simulator from the Zidings, right. So, these are the inputs I and this one is the output, right second light. Third one is a period they shown, how much duration we have performed, right. So, for 0 0 0, 3 0 input signal, 3 bit input, in that case last bit is 1, for 0 0 1, second bit is 1. So, if this one is performing correctly as per our code whatever you mentioned, right. So, this is how you can verify your VHDL design module with the help of test bench, right. So, these are the references. Thank you.