 Hello and welcome to this presentation of the Flexible Data Rate Controller Area Network Interface. It will cover the main features of this interface, which is widely used to connect the microcontroller to a CAN network. The Flexible Data Rate Controller Area Network, or FD-CAN, is a standard serial differential bus broadcast interface that enables the microcontroller to communicate with external devices connected to the same network bus. The FD-CAN interface is highly configurable, enabling nodes to easily connect using just two wires. Applications benefit from a multi-master concept with message priority, object-oriented communication, no node addressing but content identification, real-time capability with low message transfer latency, and system-wide message consistency, error detection, and management mechanism. The CAN subsystem supports two FD-CAN controllers named FD-CAN 1 and FD-CAN 2. These two controllers are independent, except for the clock calibration unit and RAM, which are shared, and have the same functionalities, except for the TT-CAN, which is supported only by FD-CAN 1. These controllers support both the basic extended CAN protocol versions 2.0, A, and B, with a maximum bitrate of 1 megabit per second, as well as CAN FD protocol version 1.0, with up to 64 data bytes, and a data bitrate of up to 8 megabits per second. A shared 10-kilobyte message RAM memory is available. Fully programmable, this RAM is used to contain the filters, buffers, FIFOs, and the triggers for the time-triggered CAN, or TT-CAN. The total amount of memory that would be required to support the full configuration for a single controller is 17.4 kilobytes max. As only 10-kilobyte RAM memory is available, some trade-offs have to be made in function of the application. Each controller also supports two independent maskable interrupts, each one having 30 fully configurable interrupt flags. The controllers have a power-down mode. They support error logging, auto SAR, J1939, and separate signaling on reception of high-priority messages. Controller FD-CAN-1 supports the time-triggered CAN, or TT-CAN, including event-synchronized time-triggered communication, global system time, and clock-drift compensation. The clock calibration unit can be optionally used to generate a calibrated clock for both FD-CAN-1 and FD-CAN-2 controllers. It uses the HSI internal RC oscillator and the PLL by evaluating CAN messages received by the FD-CAN-1. The FD-CAN has three main operating modes, initialization, normal, and sleep. After a hardware reset, the FD-CAN enters initialization mode via software. In this mode, the peripheral must be configured, bit timings, and RAM allocation. In the bit timing configuration, the rate is set, then the sampling point is adjusted according to the actual serial bus line. The CAN controller then synchronizes itself with the CAN bus by waiting for 11 consecutive recessive bits. When the CAN is in normal mode, the user can select different specific modes. FD-CAN mode, it can be long-frame and or fast-frame mode, TT-CAN mode, time-triggered communication. In this mode, the automatic retransmission feature must be disabled, or DAR mode. Restricted mode, the controller is able to receive data frames and acknowledge them, but does not send frames. It can be used in applications that adapt themselves to different CAN bit rates. Bus monitoring mode, the controller is able to receive data frames, but cannot acknowledge them. It can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits. Test modes, external loopback mode, the controller treats its own transmitted messages as received messages. Or internal loopback mode, the controller can be tested without affecting a running CAN system. Upon a CPU request, the FD-CAN is in sleep mode, which operates at a lower power. Note, in sleep mode, the internal pull-up is active on PIN CAN-TX. This simplified block diagram of the CAN subsystem in a single FD-CAN configuration shows its basic functional and control features. Three types of registers. Control configuration registers, file configuration registers, and status registers. Time-triggered registers are showed independently as they are only present in the FD-CAN-1 controller. A fully configurable RAM memory stores all the filters and messages needed by the TX and RX handlers. The allocation of these different sections is done by programming the RAM configuration registers. The TX handler manages prioritization and frame synchronization before sending the messages to the CAN-CORE protocol handler. The RX handler receives messages from the CAN-CORE and accepts or not the message function of the filters loaded from the RAM. Finally, a clock calibration unit can be used to generate a calibrated clock from the HSI internal RC oscillator and the PLL by evaluating CAN messages received by FD-CAN-1. Filters and triggers are directly sent by the CPU through the APB bus. This simplified block diagram of the FD-CAN in a dual CAN configuration shows its basic functional and control features. Compared to a single configuration, we can see that the register map, TX handler, RX handler and CAN-CORE are duplicated. Note nevertheless that the time-triggered registers are only present for FD-CAN-1. The RAM memory also stores two sets of data sections, one for FD-CAN-1 and the other for FD-CAN-2. Finally, the clock calibration unit, when used, generates a clock for both FD-CAN-1 and FD-CAN-2. The controller area network or CAN bus was originally designed for automotive applications, but is now also used in many other contexts. An FD-CAN controller peripheral provides two independent interrupt lines. The CAN subsystem provides then four independent interrupt lines for the controllers and one interrupt line for the clock calibration unit. You can see in this slide the complete list of possible interrupt events. Here is an overview of the CAN low power configuration modes. The device is not able to perform any communications in stop or standby modes. It is important to ensure that all CAN traffic is completed before the peripheral enters stop or standby modes. While the CPU core is in debug mode, that is stopped at a breakpoint, then FD-CAN remains in its normal functioning mode. In particular, reception continues as normal, and this may lead to reception overrun errors when FIFOs or buffers are full. Registers of the type reset on read or set on read are disabled. Reading them will not affect their value. For additional information, refer to the training for these peripherals which may affect FD-CAN behavior. Reset and clock controller or RCC for more information about the CAN clock control and enable or reset. Interrupts for more information about the mapping of the FD-CAN's interrupts. General Purpose IOs or GPIO for more information about the FD-CAN's input and output pins. Or debug support or DBG for more information about the FD-CAN's behavior in debug mode. Application notes covering the CAN topic are available on www.st.com. To learn more about the CAN interface, you can also visit a wide range of webpages discussing the CAN communication protocol and bus monitoring tools. Many digital oscilloscopes support direct reading and analysis of data transmitted over the CAN bus.