 Welcome to the presentation of the STM32L4 Direct Memory Access or DMA Controller. It covers the main features of this module, which is widely used to handle the STM32 peripheral data transfers. The STM32L4 has two direct memory access controllers designed to efficiently support data transfers from peripherals and memories without any loading on the CPU. The DMA controllers are fully configurable and manage hardware and software priorities between channels as well as data transfer modes. The two DMA controllers, DMA1 and DMA2, have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each channel has flexible hardware requests or software trigger. The channel's software priority is programmable and a hardware priority is used in case of equality. Channels are independently configurable. Each channel has its own data format, increment type, and data address for both source and destination. Independent channel interrupt flags allow you to trigger half transfer, transfer complete, and transfer error events. A global flag is also available to facilitate the software efficiency. In case of an error, the faulty channel is automatically disabled without any impact on the other active DMA channels. For each channel, the source and destination data size format is independently configured for 8, 16, or 32-bit packets. The source and destination address and pointer increment are also independently configurable. The transfer data size can be pre-programmed up to 65, 535. Circular buffer mode is available to support a continuous flow of data. The source and destination addresses and the number of data to be transferred are automatically reloaded after the complete transfer. Memory to memory mode allows transfers from one address location to another without a hardware request. Once the channel is configured and enabled, the transfer starts immediately. When data is transferred from or to a peripheral, the hardware request coming from the selected peripheral is used to trigger the data transfer. Once the transfer is completed, the request is acknowledged. The STM32L4 implements two instances of the DMA with seven channels each. DMA1 peripheral requests are mapped through a multiplexer for each corresponding channel. Each channel has a fixed group of peripheral requests and the multiplexer allows only one peripheral request for each channel. The DMA2 controller also provides access to seven channels with independent multiplexers for each channel. Some of the peripheral requests are similar to the DMA1, but there are unique peripheral requests as well. For example, TIM5, TIM8, LPUART, SWMPI1, UART4, UART5, and AES. Each DMA channel is designed with this group of interrupt events. The half-transfer interrupt flag is set when half the data has been transferred. The transfer complete flag is set when the transfer is complete. The transfer error flag is set when an error occurs during the data transfer. The global interrupt flag is set whenever a half-transfer, a transfer complete, or a full-transfer event occurs. The DMA is active in run, sleep, low-power run, and low-power sleep mode. DMA interrupts will wake the STM32L4 from sleep and low-power sleep modes. In stop mode, the DMA is stopped and the contents of the DMA registers are retained. The DMA is powered down in standby and shutdown modes, and the DMA registers must be re-initialized after exiting standby or shutdown mode.