 Hello and welcome to this presentation of the STM32L5 Analog to Digital Converter block. It will cover the main features of this block, which is used to convert the external analog voltage-like sensor outputs to digital values for further processing in the digital domain. The analog to digital converter inside the STM32L5 microcontroller allows the microcontroller to accept an analog value, like from a sensor output, and convert the signal for use in the digital domain. There are 21 analog inputs available across the two ADCs. The oversampling unit pre-processes the data to offload the main processor. It can handle multiple conversions and average them into a single data with an increased data width up to 16 bits. The ADC module itself is a 12-bit successive approximation converter with additional oversampling hardware. The sampling speed is 5.33 mega-samples per second for 12-bit resolution. The data can be made available to the system, either through DMA transfers, interrupts, or polling. This ADC is designed for low power and high performance. There are a number of triggering mechanisms and the data management can be configured to minimize the CPU workload. The ADC module also integrates an analog watchdog. Two analog to digital converters are integrated inside STM32L5XX products. The input channel is connected to up to 21 channels capable of converting signals in either single-end or differential mode. The ADCs can convert signals at 5.33 mega-samples per second in 12-bit mode when ADC clock frequency is 80 megahertz. There are several functional modes which will be explained later. There are also several different triggering methods. In order to offload the CPU, the ADC has an analog watchdog for monitoring thresholds. The analog watchdog has new filtering features. The ADC also offers oversampling to extend the number of bits presented in the final conversion value. For power-sensitive applications, the ADC offers a number of low power features. This slide shows the general block diagram of the ADC. The main important subunits of the ADC are the power supplies and on-off control, the analog front end, the trigger logic, the digital back end including the analog watchdogs and the AHB slave interface and the clocking. The next slides detail all these subunits. The ADC has two clock inputs, ADC12CK and ADCHCLK. The AHB interface belongs to the ADCHCLK clock domain. Regarding the digital part of the SAR ADC, there are two options, either using ADCHCLK as the reference clock or using ADC12CK, which is dedicated and independent of ADCHCLK. With this second option, dynamic frequency scaling can be implemented in the AHB and CPU clock domain while the sampling clock is fixed. However, samples acquired in the ADC12CK clock domain have to pass to the AHB clock domain to be read by CPU or DMA, which requires a synchronization delay. An uncertainty of the trigger instant is also added by the resynchronizations between the two clock domains. The analog part of the ADC needs two power supplies, VRF+, which is the positive analog reference, and VDDA, which is the analog power supply. By default, the ADC is in deep power down mode, where its supply is internally switched off to reduce the leakage currents. To start ADC operations, it is first needed to exit deep power down mode by setting the deep power down bit to zero. It is possible to save power by also disabling the ADC voltage regulator. This is done by writing ADVREGEN to zero. Setting ADIS to 1 disables the ADC. ADEN and ADIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled. The analog switch inside the IO has a resistance, which increases when the analog switch supply decreases. So for cases where VDDA and VDD are low, there is a possibility to enable a voltage booster which will supply the analog switch and guarantee low resistance. The recommended supply for the analog switch is to use VDDA. But when VDDA is lower than 2.4 volts and VDD is larger than 2.4 volts, the power supply can be switched to VDD. If both VDDA and VDD are lower than 2.4 volts, the voltage booster should be enabled. It is possible to provide the internal reference voltage VREF internally using the VREF buff. Two voltage levels are available. This can be used only when there is a VREF pin in the package. All packages except 32 pin STM32L531, UFQFPN32 and LQFP32 packages. When VREF is provided by internal VREF buff, decoupling capacitors must be placed to the VREF pin. The STM32L5 supports up to two ADCs. Each of them is connected to external analog channels and internal analog sources. The internal channels are the internal reference voltage or VREF int, the internal temperature sensor or V-sense, the V-BAT monitoring channel or V-BAT 3, and DAC out 1 and 2 voltage. Note that analog inputs can be configured to be single-ended or differential. The ADC offers an auto calibration mechanism. Calibration is preliminary to any ADC operation. It removes the offset error, which may vary from chip to chip due to process, supply voltage or temperature variation. Single-ended inputs and differential inputs are calibrated separately according to the state of the ADC CalDIF bit feature. Software can request a calibration by setting the AD CalBit to 1. The resulting calibration factor can be read from the ADC CalFact register. It is recommended to run the calibration on the application if the reference voltage changes more than 10%, so this would include emerging from reset or from a low-power state where the analog voltage supply has been removed and re-established. High temperature excursion may also require running the offset calibration. This table indicates how the internal analog channels connected to two ADCs. Conversions are organized in two groups, the regular group and the injected group. The injected group can preempt the execution of the regular group sampling sequence. The user is in charge of selecting the size of each group, maximum 16 acquisitions in the regular group and four in the injected group. They also have to assign the analog channels for each sampling within the sequence. Each group has its own trigger logic. The trigger can be an external signal coming from GPIOs or timer outputs. A sequence of acquisition can also be triggered by software. The digital back end performs processing on the samples obtained in the SAR ADC in the oversampler and offset unit. Raw samples may be processed by the oversampler and offset compensation units before being provided to the software. The results are then stored into registers that are accessible from the AHB slave interface. AHB supports a higher bandwidth and minimizes latency because the CPU and DMA are also connected to the AHB interconnect. The ADC is able to assert a request to the DMA so that samples coming from regular channels are automatically moved to memory. Injected channels do not support DMA requests. The ADC includes the oversampling hardware which accumulates data and then divides without CPU assistance. The oversampler can accommodate from 2 to 256 time samples and right shift from 1 to 8 binary digits. 12-bit data can be extended to be presented as 16-bit data. This functionality can be used as an averaging function or for data rate reduction and signal-to-noise ratio improvement as well as for basic filtering. An offset Y, Y equals 1234 can be applied to a channel by setting the bit offset Y, EN equals 1 into ADC OFRY register. The channel to which the offset will be applied is programmed into the bits offset Y, CH4 to 0 of ADC OFRY register. In this case, the converted value is decreased by the user-defined offset written in the bits offset Y, 11 to 0. The result may be a negative value so the read data is signed. When auto-delay mode is active, the ADCs wait until the last conversion data is read or the end of conversion flag is cleared before starting the next conversion. This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. This also avoids unnecessary conversions and thus reduces power consumption. This auto-delay mode does not apply to injected conversions except the last one when switching back to the regular conversions. Power consumption from VDDA power supply depends on sampling time from 16.6 microamps at 10 kilo-samples per second to 860 microamps at 5 mega-samples per second. For low sampling rates, the current consumption is reduced almost proportionally. The global conversion time is equal to the sampling time plus the conversion time. The ADC needs a minimum of 2.5 clock cycles for the sampling and 12.5 clock cycles for conversion for 12-bit mode. With an 80 MHz ADC clock, it can achieve 5.33 mega-samples per second. For a higher sampling speed, it is possible to reduce the resolution down to 10, 8 or 6 bits. When associating a master and a slave ADC, the interleaved mode maximum performance is one sample every 8 clocks, so 10 mega-samples per second at 80 MHz clock. The first set of conversion consists in loading the sample and hold capacitor with the voltage to be measured. Longer sample times ensure that signals having a higher impedance are correctly converted. The sampling times listed in this slide in ADC clock cycles are available. The sampling time can be programmed individually for each input channel of the analog to digital converters. The ADC supports several conversion modes. Single mode, which converts only one channel in single shot or continuous mode. Scan mode, which converts a complete set of defined programmed input channels in single shot or continuous mode. And discontinuous mode, which converts a short sequence or subgroup of N conversions, N being less than or greater than 8, that is part of the sequence of conversions. When an external trigger occurs, it starts the next N conversion selected in the ADC SQR registers until all the conversions in the sequence are done. Each ADC has three integrated analog watchdogs, with high and low threshold settings. The ADC conversion value is compared to this window threshold. If the result exceeds the threshold, an interrupt or external signal can be generated, or a timer can be immediately stopped without CPU intervention. The ADC conversion result is stored in a 16-bit data register. In dual mode, two samples are combined into a 32-bit register called ADCX-CDR. Thus minimizing the number of transactions on AHB. The system can use CPU polling, interrupts or the DMA controller to make use of the conversion data. An overrun flag can be generated if data is not read before the next conversion data is ready. In case of overrun, either the new sample is dropped or the previous sample is overwritten. For injected channel conversions, four dedicated data registers are available. An injected conversion is used to interrupt the regular conversion, then insert up to four channel conversions. Once an injected conversion is finished, the regular conversion sequence can be resumed. The injected conversion result is stored in dedicated data registers. Flags and interrupts are available for the end of conversion or end of sequence. The choices for an injected channel can be reprogrammed on the fly. Even if a regular or injected conversion is in progress, you can add a different channel to the queue so that the next injected channel can be different from the previous one. The STM32L5 embeds two ADCs. ADC1 and ADC2 can be configured to work together in dual mode so that each analog to digital conversion can be synchronized between the two modules. Four possible dual ADC modes are implemented. Injected simultaneous mode, regular simultaneous mode, interleaved mode, and alternate trigger mode. It is also possible to use these modes combined in the following ways. Injected simultaneous mode plus regular simultaneous mode, regular simultaneous mode plus alternate trigger mode, and injected simultaneous mode plus interleaved mode. In dual ADC mode, operations can be started either simultaneously or alternately on ADC master and ADC slave. The converted data of the master and slave ADC can be read in parallel by reading the ADC common data register or ADCX-CDR. Do not convert the same channel on the two ADCs. This slide describes the injected simultaneous mode and the regular simultaneous mode. Trigger is used to simultaneously start the sequence of conversions on both master and slave ADC. Conversion sequences must be equal on master and slave or must ensure that the interval between triggers is longer than both sequences. In discontinuous mode, every simultaneous conversion requires an injected trigger. Interleaved mode converts a regular channel group, usually one channel. The external trigger source, which starts from the conversion, comes from ADC master. ADC master starts immediately. ADC slave starts after a configurable delay after the end of the sampling of the master. It prevents an ADC from starting a conversion while the complementary ADC is still sampling the input. An EOC is generated at the end of each channel conversion. In discontinuous mode, every simultaneous conversion requires a regular trigger. When a sampling time of 2.5 ADC clock cycles is selected, the total conversion time becomes 15 cycles in 12-bit mode. If the dual interleaved mode is used, the sampling interval cannot be equal to 2.5 ADC clock cycles since an even number of cycles is required for the sampling time plus conversion time. In the timing diagram on the right, the sampling time on the slave ADC has to be increased to 3.5 clock cycles while the sampling time for the master ADC is 2.5 clock cycles. The SMP plus bit can be used to change the sampling time 2.5 ADC clock cycles into 3.5 ADC clock cycles. In this way, the total conversion time becomes 16 clock cycles, thus making it possible to interleave every 8 cycles. The maximum number of samples per second is equal to 80 MHz divided by 8 equals 10 MHz per second. The alternate trigger mode converts an injected group of channels. Conversions are started only by using hardware triggers. The external trigger source comes from the injected group multiplexer of the master ADC. When discontinuous mode is disabled and the first trigger occurs, all injected master ADC channels in the group are converted. When the second trigger occurs, all injected slave ADC channels in the group are converted. When discontinuous mode is enabled and the first trigger occurs, the first injected channel of the master ADC is converted. When the second trigger occurs, injected channel of the slave ADC is converted. Each ADC can generate nine different interrupts. ADC ready, end of conversion, end of sequence, end of injected conversion, end of injected sequence, analog watchdog, end of sampling, data overrun, and the overflow of the injected sequence context queue. DMA requests can be generated at each end of conversion when the ADC output data is ready. The ADCs are active in run, sleep, low power run, and low power sleep modes. In stop zero, stop one mode, the ADCs are not available, but the contents of their registers are kept. In standby or shutdown mode, the ADCs are powered down and must be reinitialized when returning to a higher power state. There is a deep power down mode in each ADC itself which reduces leakage by turning off an on-chip power switch. This is the recommended mode whenever an ADC is not used. The following table shows performance parameters for the ADC. This table highlights the new features implemented in the STM32L5's ADCs with regard to the STM32F3's ADCs. These peripherals may need to be specifically configured for correct use with the ADCs. Please refer to the corresponding peripheral training modules for more information. Several application notes dedicated to analog to digital converters are available. To learn more about ADCs, you can visit a wide range of webpages discussing successive approximation analog to digital converters.