 Hello, and welcome to this presentation about the STM32H7X5 and STM32H7X7 dual-core lines ART or Adaptive Real-Time Accelerator. The ART or Adaptive Real-Time Accelerator block speeds up instruction fetch accesses of the Cortex-M4 core to D1 domain internal memories, Flash-A memory, Flash-B memory, and AXIS-RAM. D1 domain external memories attached via the Quad-SPI controller or QSPI and Flash-Memory controller or FMC. The acceleration is achieved by loading selected code into an embedded cache and making it instantly available to the Cortex-M4 core, thus avoiding latency due to memory weight states. This figure shows the block schematic and the environment of the ART accelerator. Instruction fetch accesses can be qualified as cacheable or non-cacheable. The cache memory is organized in 64 lines of 256 bits each. Each line contains 8 32-bit segments. Each segment can contain one 32-bit or two 16-bit instruction codes. The cache buffer is an extra line of 256 bits, keeping a copy of one of the cache lines. The cache manager checks whether the incoming memory instruction fetch access is cacheable and controls the AHB switch accordingly. For a cacheable access, it allows the instruction fetch from cache in case of a cache hit and it manages the cache memory line refill or instruction code load in case of a cache miss. For non-cacheable memory accesses, the instruction is directly fetched from memory. The cache accelerator features 32-bit AHB slave port to interface with the D2 domain, 32-bit AHB master port for non-cacheable memory accesses, 64-bit AXI master port to load the code from memory to cache, 64 cache lines of 256 bits, fully associative cache, programmable page, and cache content consistency checker. The instruction fetch accesses can be qualified as cacheable or non-cacheable depending on MPU attributes. For cacheable accesses, the instruction fetch follows the cacheable access path. Non-cacheable accesses are directed to the master AHB port following the non-cacheable access path. The appropriate access path is selected with the AHB switch controlled by the cache manager. The cache memory is organized in 64 lines of 256 bits each. Every line contains 8 32-bit segments. Each segment can contain one 32-bit or two 16-bit instruction codes. The cache buffer is an extra line of 256 bits, keeping a copy of one of the cache lines or buffer source line. It allows fetching instruction code by the core while the corresponding buffer source line is in refill progress. The following cases can cause the code in the cache to become inconsistent with the code at the corresponding address of the addressed memory. A write access modifies a piece of data in the cacheable page of the addressed memory. The software modifies the cacheable page index in the art accelerators control register. A data transfer error occurs during the cache buffer and or cache memory line refill. The device incorporates a mechanism preventing software corruption due to the cache in consistency. It detects the above cases and flags all the cache memory lines and the cache buffer as invalid. As a consequence, the next cacheable accesses result in a cache miss and so the cache line refills with new data.